x64 emitter: Add a few missing instructions

2 files changed, 34 insertions, 1 deletions

diff --git a/Source/Core/Common/x64Emitter.cpp b/Source/Core/Common/x64Emitter.cpp
index 7693236a62..f727f105d9 100644
--- a/Source/Core/Common/x64Emitter.cpp
+++ b/Source/Core/Common/x64Emitter.cpp
@@ -1636,6 +1636,11 @@ void XEmitter::PSRLQ(X64Reg reg, OpArg arg)
 	WriteSSEOp(0x66, 0xd3, reg, arg);
 }
 
+void XEmitter::PSRLDQ(X64Reg reg, int shift) {
+	WriteSSEOp(0x66, 0x73, (X64Reg)3, R(reg));
+	Write8(shift);
+}
+
 void XEmitter::PSLLW(X64Reg reg, int shift)
 {
 	WriteSSEOp(0x66, 0x71, (X64Reg)6, R(reg));
@@ -1654,6 +1659,12 @@ void XEmitter::PSLLQ(X64Reg reg, int shift)
 	Write8(shift);
 }
 
+void XEmitter::PSLLDQ(X64Reg reg, int shift) {
+	WriteSSEOp(0x66, 0x73, (X64Reg)7, R(reg));
+	Write8(shift);
+}
+
+
 // WARNING not REX compatible
 void XEmitter::PSRAW(X64Reg reg, int shift)
 {
@@ -1761,7 +1772,7 @@ void XEmitter::PMINSW(X64Reg dest, OpArg arg)   {WriteSSEOp(0x66, 0xEA, dest, ar
 void XEmitter::PMINUB(X64Reg dest, OpArg arg)   {WriteSSEOp(0x66, 0xDA, dest, arg); }
 
 void XEmitter::PMOVMSKB(X64Reg dest, OpArg arg)    {WriteSSEOp(0x66, 0xD7, dest, arg); }
-
+void XEmitter::PSHUFD(X64Reg regOp, OpArg arg, u8 shuffle)    {WriteSSEOp(0x66, 0x70, regOp, arg, 1); Write8(shuffle);}
 void XEmitter::PSHUFLW(X64Reg regOp, OpArg arg, u8 shuffle)   {WriteSSEOp(0xF2, 0x70, regOp, arg, 1); Write8(shuffle);}
 
 // VEX
diff --git a/Source/Core/Common/x64Emitter.h b/Source/Core/Common/x64Emitter.h
index 9f41194edc..917053ffee 100644
--- a/Source/Core/Common/x64Emitter.h
+++ b/Source/Core/Common/x64Emitter.h
@@ -101,6 +101,17 @@ enum NormalOp {
 	nrmXCHG,
 };
 
+enum {
+	CMP_EQ = 0,
+	CMP_LT = 1,
+	CMP_LE = 2,
+	CMP_UNORD = 3,
+	CMP_NEQ = 4,
+	CMP_NLT = 5,
+	CMP_NLE = 6,
+	CMP_ORD = 7,
+};
+
 enum FloatOp {
 	floatLD = 0,
 	floatST = 2,
@@ -526,6 +537,14 @@ public:
 	void CMPSS(X64Reg regOp, OpArg arg, u8 compare);
 	void CMPSD(X64Reg regOp, OpArg arg, u8 compare);
 
+	inline void CMPEQSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_EQ); }
+	inline void CMPLTSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_LT); }
+	inline void CMPLESS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_LE); }
+	inline void CMPUNORDSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_UNORD); }
+	inline void CMPNEQSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_NEQ); }
+	inline void CMPNLTSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_NLT); }
+	inline void CMPORDSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_ORD); }
+
 	// SSE/SSE2: Floating point packed arithmetic (x4 for float, x2 for double)
 	void ADDPS(X64Reg regOp, OpArg arg);
 	void ADDPD(X64Reg regOp, OpArg arg);
@@ -690,6 +709,7 @@ public:
 	void PMINUB(X64Reg dest, OpArg arg);
 
 	void PMOVMSKB(X64Reg dest, OpArg arg);
+	void PSHUFD(X64Reg dest, OpArg arg, u8 shuffle);
 	void PSHUFB(X64Reg dest, OpArg arg);
 
 	void PSHUFLW(X64Reg dest, OpArg arg, u8 shuffle);
@@ -698,10 +718,12 @@ public:
 	void PSRLD(X64Reg reg, int shift);
 	void PSRLQ(X64Reg reg, int shift);
 	void PSRLQ(X64Reg reg, OpArg arg);
+	void PSRLDQ(X64Reg reg, int shift);
 
 	void PSLLW(X64Reg reg, int shift);
 	void PSLLD(X64Reg reg, int shift);
 	void PSLLQ(X64Reg reg, int shift);
+	void PSLLDQ(X64Reg reg, int shift);
 
 	void PSRAW(X64Reg reg, int shift);
 	void PSRAD(X64Reg reg, int shift);