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| author | skidau <skidau@gmail.com> | 2014-11-05 12:13:42 +1100 |
|---|---|---|
| committer | skidau <skidau@gmail.com> | 2014-11-05 12:13:42 +1100 |
| commit | a66b34cfc6732ee32c1fca67e07828dd380ee38e (patch) | |
| tree | 169f69b75fafb0def9ea9f31705484d04e9cbba2 /Source/Core | |
| parent | 50f442ac31c11356067014b6ab52cf863281baa3 (diff) | |
| parent | b81686b582b41787ff6441e70d61ea7f1e1e7f0d (diff) | |
Merge pull request #1492 from FioraAeterna/fixregpreload
JIT: fix register preloading
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/PowerPC/Jit64/Jit.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/PowerPC/Jit64/Jit.cpp index 2294dbcfb0..8de45ae981 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit.cpp @@ -747,12 +747,12 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc if (ops[i].gprInReg[reg] && !gpr.R(reg).IsImm()) gpr.BindToRegister(reg, true, false); } - for (int reg : ops[i].regsOut) + for (int reg : ops[i].fregsIn) { if (fpr.NumFreeRegisters() < 2) break; if (ops[i].fprInXmm[reg]) - gpr.BindToRegister(reg, true, false); + fpr.BindToRegister(reg, true, false); } Jit64Tables::CompileInstruction(ops[i]); |