Workaround for a missing feature in the FPU parts of the JIT.

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@246 8ced0084-cf51-0410-be5f-012b33b47a6e

5 files changed, 45 insertions, 1 deletions

diff --git a/Source/Core/Core/Src/PowerPC/Jit64/JitAsm.cpp b/Source/Core/Core/Src/PowerPC/Jit64/JitAsm.cpp
index 91d201deae..5e741d084e 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64/JitAsm.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64/JitAsm.cpp
@@ -48,6 +48,7 @@ const u8 *dispatcher;
 const u8 *dispatcherNoCheck;

 const u8 *dispatcherPcInEAX;

 const u8 *computeRc;

+const u8 *computeRcFp;

 

 const u8 *fifoDirectWrite8;

 const u8 *fifoDirectWrite16;

@@ -336,6 +337,11 @@ void GenerateCommon()
 	GenFifoWrite(32);

 	fifoDirectWriteFloat = AlignCode4();

 	GenFifoFloatWrite();

+

+	computeRcFp = AlignCode16();

+	//CMPSD(R(XMM0), M(&zero), 

+	// TODO

+

 	// Fast write routines - special case the most common hardware write

 	// TODO: use this.

 	// Even in x86, the param values will be in the right registers.

diff --git a/Source/Core/Core/Src/PowerPC/Jit64/JitAsm.h b/Source/Core/Core/Src/PowerPC/Jit64/JitAsm.h
index 88c3a25053..1565c96e0e 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64/JitAsm.h
+++ b/Source/Core/Core/Src/PowerPC/Jit64/JitAsm.h
@@ -30,6 +30,7 @@ namespace Jit64
 

 		extern const u8 *fpException;

 		extern const u8 *computeRc;

+		extern const u8 *computeRcFp;

 		extern const u8 *testExceptions;

 		extern const u8 *dispatchPcInEAX;

 		extern const u8 *doTiming;

diff --git a/Source/Core/Core/Src/PowerPC/Jit64/JitRegCache.cpp b/Source/Core/Core/Src/PowerPC/Jit64/JitRegCache.cpp
index 22aa2ac808..16649ba64a 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64/JitRegCache.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64/JitRegCache.cpp
@@ -349,8 +349,12 @@ namespace Jit64
 			xregs[xr].free = false;

 			xregs[xr].dirty = makeDirty;

 			OpArg newloc = ::Gen::R(xr);

-			if (doLoad)

+			if (doLoad) {

+				if (!regs[i].location.IsImm() && (regs[i].location.offset & 0xF)) {

+					PanicAlert("WARNING - misaligned fp register location %i", i);

+				}

 				MOVAPD(xr, regs[i].location);

+			}

 			regs[i].location = newloc;

 			regs[i].away = true;

 		}

diff --git a/Source/Core/Core/Src/PowerPC/Jit64/Jit_FloatingPoint.cpp b/Source/Core/Core/Src/PowerPC/Jit64/Jit_FloatingPoint.cpp
index b07e95b7d4..3dd8774bb4 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64/Jit_FloatingPoint.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64/Jit_FloatingPoint.cpp
@@ -79,6 +79,9 @@ namespace Jit64
 	void fp_arith_s(UGeckoInstruction inst)

 	{

 		INSTRUCTION_START;

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 		bool dupe = inst.OPCD == 59;

 		switch (inst.SUBOP5)

 		{

@@ -100,6 +103,9 @@ namespace Jit64
 	void fmaddXX(UGeckoInstruction inst)

 	{

 		INSTRUCTION_START;

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 		int a = inst.FA;

 		int b = inst.FB;

 		int c = inst.FC;

@@ -139,6 +145,9 @@ namespace Jit64
 	void fmrx(UGeckoInstruction inst)

 	{

 		INSTRUCTION_START;

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 		int d = inst.FD;

 		int b = inst.FB;

 		fpr.LoadToX64(d, true);  // we don't want to destroy the high bit

diff --git a/Source/Core/Core/Src/PowerPC/Jit64/Jit_Paired.cpp b/Source/Core/Core/Src/PowerPC/Jit64/Jit_Paired.cpp
index dce84fb784..f234a5e312 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64/Jit_Paired.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64/Jit_Paired.cpp
@@ -53,6 +53,9 @@ namespace Jit64
 	void ps_mr(UGeckoInstruction inst)

 	{

 		INSTRUCTION_START;

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 		int d = inst.FD;

 		int b = inst.FB;

 		if (d == b)

@@ -67,6 +70,9 @@ namespace Jit64
 		Default(inst);

 		return;

 		

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 		// GRR can't get this to work 100%. Getting artifacts in D.O.N. intro.

 		int d = inst.FD;

 		int a = inst.FA;

@@ -92,6 +98,9 @@ namespace Jit64
 	void ps_sign(UGeckoInstruction inst)

 	{

 		INSTRUCTION_START;

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 		int d = inst.FD;

 		int b = inst.FB;

 

@@ -125,6 +134,9 @@ namespace Jit64
 	void ps_rsqrte(UGeckoInstruction inst)

 	{

 		INSTRUCTION_START;

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 		int d = inst.FD;

 		int b = inst.FB;

 		fpr.Lock(d, b);

@@ -193,6 +205,9 @@ namespace Jit64
 	void ps_arith(UGeckoInstruction inst)

 	{	

 		INSTRUCTION_START;

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 		switch (inst.SUBOP5)

 		{

 		case 18: tri_op(inst.FD, inst.FA, inst.FB, false, &DIVPD); break; //div

@@ -214,6 +229,9 @@ namespace Jit64
 	void ps_mergeXX(UGeckoInstruction inst)

 	{

 		INSTRUCTION_START;

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 		int d = inst.FD;

 		int a = inst.FA;

 		int b = inst.FB;

@@ -252,6 +270,9 @@ namespace Jit64
 	void ps_maddXX(UGeckoInstruction inst)

 	{

 		INSTRUCTION_START;

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 		int a = inst.FA;

 		int b = inst.FB;

 		int c = inst.FC;

@@ -295,6 +316,9 @@ namespace Jit64
 		INSTRUCTION_START;

 		Default(inst);

 		return;

+		if (inst.Rc) {

+			Default(inst); return;

+		}

 

 		switch (inst.SUBOP5)

 		{