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authorTilka <tilkax@gmail.com>2024-08-04 23:27:40 +0100
committerGitHub <noreply@github.com>2024-08-04 23:27:40 +0100
commitbc722266684e2359061ac2f0e6482e09dfe12e73 (patch)
tree460958568056887b535058180c1ebbfc07f3cd0f /Source/Core
parentc824ee9758fed656652356bc8c3a989119e8c091 (diff)
parentd877cfa4e2c3baf3cb8b8449d1608e1c2f05208c (diff)
Merge pull request #12891 from Sintendo/jitarm64-subfic
JitArm64_Integer: Optimize subfic for zero
Diffstat (limited to 'Source/Core')
-rw-r--r--Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp14
1 files changed, 10 insertions, 4 deletions
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
index 7e5817ac0c..f3d263379c 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
@@ -1392,13 +1392,19 @@ void JitArm64::subfic(UGeckoInstruction inst)
}
else
{
- const bool allocate_reg = d == a;
- gpr.BindToRegister(d, allocate_reg);
+ const bool will_read = d == a;
+ const bool is_zero = imm == 0;
+ const bool allocate_reg = will_read && !is_zero;
+ gpr.BindToRegister(d, will_read);
// d = imm - a
ARM64Reg RD = gpr.R(d);
- ARM64Reg WA = allocate_reg ? gpr.GetReg() : RD;
- MOVI2R(WA, imm);
+ ARM64Reg WA = ARM64Reg::WZR;
+ if (!is_zero)
+ {
+ WA = will_read ? gpr.GetReg() : RD;
+ MOVI2R(WA, imm);
+ }
CARRY_IF_NEEDED(SUB, SUBS, RD, WA, gpr.R(a));
if (allocate_reg)