Add the missing FPR cache

2 files changed, 230 insertions, 0 deletions

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitFPRCache.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitFPRCache.cpp
new file mode 100644
index 0000000000..08f10df826
--- /dev/null
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitFPRCache.cpp
@@ -0,0 +1,168 @@
+// Copyright (C) 2003 Dolphin Project.
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, version 2.0.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License 2.0 for more details.
+
+// A copy of the GPL 2.0 should have been included with the program.
+// If not, see http://www.gnu.org/licenses/
+
+// Official SVN repository and contact information can be found at
+// http://code.google.com/p/dolphin-emu/
+
+#include "JitFPRCache.h"
+
+ArmFPRCache::ArmFPRCache()
+{
+	emit = 0;
+}
+
+void ArmFPRCache::Init(ARMXEmitter *emitter)
+{
+	emit = emitter;
+	ARMReg *PPCRegs = GetPPCAllocationOrder(NUMPPCREG);
+	ARMReg *Regs = GetAllocationOrder(NUMARMREG);
+
+	for(u8 a = 0; a < NUMPPCREG; ++a)
+	{
+		ArmCRegs[a].PPCReg = 33;
+		ArmCRegs[a].Reg = PPCRegs[a];
+		ArmCRegs[a].LastLoad = 0;
+		ArmCRegs[a].PS1 = false;
+	}
+	for(u8 a = 0; a < NUMARMREG; ++a)
+	{
+		ArmRegs[a].Reg = Regs[a];
+		ArmRegs[a].free = true;
+	}
+}
+void ArmFPRCache::Start(PPCAnalyst::BlockRegStats &stats)
+{
+	for(u8 a = 0; a < NUMPPCREG; ++a)
+	{
+		ArmCRegs[a].PPCReg = 33;
+		ArmCRegs[a].LastLoad = 0;
+	}
+}
+ARMReg *ArmFPRCache::GetPPCAllocationOrder(int &count)
+{
+	// This will return us the allocation order of the registers we can use on
+	// the ppc side.
+	static ARMReg allocationOrder[] = 
+	{
+		D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
+		D11, D12, D13, D14, D15, D16, D17, D18, D19,
+		D20, D21, D22, D23, D24, D25, D26, D27
+	};
+	count = sizeof(allocationOrder) / sizeof(const int);
+	return allocationOrder;
+}
+ARMReg *ArmFPRCache::GetAllocationOrder(int &count)
+{
+	// This will return us the allocation order of the registers we can use on
+	// the host side.
+	static ARMReg allocationOrder[] = 
+	{
+		D31, D30, D29, D28
+	};
+	count = sizeof(allocationOrder) / sizeof(const int);
+	return allocationOrder;
+}
+
+ARMReg ArmFPRCache::GetReg(bool AutoLock)
+{
+	for(u8 a = 0; a < NUMARMREG; ++a)
+		if(ArmRegs[a].free)
+		{
+			// Alright, this one is free
+			if (AutoLock)
+				ArmRegs[a].free = false;
+			return ArmRegs[a].Reg;
+		}
+	// Uh Oh, we have all them locked....
+	_assert_msg_(_DYNA_REC_, false, "All available registers are locked dumb dumb");
+	return D31;
+}
+void ArmFPRCache::Unlock(ARMReg V0)
+{
+	for(u8 RegNum = 0; RegNum < NUMARMREG; ++RegNum)
+	{
+		if(ArmRegs[RegNum].Reg == V0)
+		{
+			_assert_msg_(_DYNA_REC, !ArmRegs[RegNum].free, "This register is already unlocked");
+			ArmRegs[RegNum].free = true;
+		}
+	}
+}
+ARMReg ArmFPRCache::GetPPCReg(u32 preg, bool PS1, bool preLoad)
+{
+	u32 HighestUsed = 0;
+	u8 Num = 0;
+	for(u8 a = 0; a < NUMPPCREG; ++a){
+		++ArmCRegs[a].LastLoad;
+		if (ArmCRegs[a].LastLoad > HighestUsed)
+		{
+			HighestUsed = ArmCRegs[a].LastLoad;
+			Num = a;
+		}
+	}
+	// Check if already Loaded
+	for(u8 a = 0; a < NUMPPCREG; ++a)
+		if (ArmCRegs[a].PPCReg == preg && ArmCRegs[a].PS1 == PS1)
+		{
+			ArmCRegs[a].LastLoad = 0;
+			return ArmCRegs[a].Reg;
+		}
+	// Check if we have a free register
+	for (u8 a = 0; a < NUMPPCREG; ++a)
+		if (ArmCRegs[a].PPCReg == 33)
+		{
+			u16 offset = STRUCT_OFF(PowerPC::ppcState, ps) + (preg * 16) + (PS1 ? 8 : 0);
+			if (preLoad)
+				emit->VLDR(ArmCRegs[a].Reg, R9, offset);
+			ArmCRegs[a].PPCReg = preg;
+			ArmCRegs[a].LastLoad = 0;
+			ArmCRegs[a].PS1 = PS1;
+			return ArmCRegs[a].Reg;
+		}
+	// Alright, we couldn't get a free space, dump that least used register
+	u16 offsetOld = STRUCT_OFF(PowerPC::ppcState, ps) + (ArmCRegs[Num].PPCReg * 16) + (ArmCRegs[Num].PS1 ? 8 : 0);
+	emit->VSTR(ArmCRegs[Num].Reg, R9, offsetOld);
+	
+	u16 offsetNew = STRUCT_OFF(PowerPC::ppcState, ps) + (preg * 16) + (PS1 ? 8 : 0);
+	if (preLoad)
+		emit->VLDR(ArmCRegs[Num].Reg, R9, offsetNew);
+	ArmCRegs[Num].PPCReg = preg;
+	ArmCRegs[Num].LastLoad = 0;
+	ArmCRegs[Num].PS1 = PS1;
+	return ArmCRegs[Num].Reg;		 
+
+}
+
+ARMReg ArmFPRCache::R0(u32 preg, bool preLoad)
+{
+	return GetPPCReg(preg, false, preLoad);
+}
+
+ARMReg ArmFPRCache::R1(u32 preg, bool preLoad)
+{
+	return GetPPCReg(preg, true, preLoad);
+}
+
+void ArmFPRCache::Flush()
+{
+	for(u8 a = 0; a < NUMPPCREG; ++a)
+		if (ArmCRegs[a].PPCReg != 33)
+		{
+			u16 offset =  STRUCT_OFF(PowerPC::ppcState, ps) + (ArmCRegs[a].PPCReg * 16) + (ArmCRegs[a].PS1 ? 8 : 0);
+			emit->VSTR(ArmCRegs[a].Reg, R9, offset);
+			ArmCRegs[a].PPCReg = 33;
+			ArmCRegs[a].LastLoad = 0;
+		}
+}
+
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitFPRCache.h b/Source/Core/Core/Src/PowerPC/JitArm32/JitFPRCache.h
new file mode 100644
index 0000000000..6b4f056409
--- /dev/null
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitFPRCache.h
@@ -0,0 +1,62 @@
+// Copyright (C) 2003 Dolphin Project.
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, version 2.0.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License 2.0 for more details.
+
+// A copy of the GPL 2.0 should have been included with the program.
+// If not, see http://www.gnu.org/licenses/
+
+// Official SVN repository and contact information can be found at
+// http://code.google.com/p/dolphin-emu/
+
+#ifndef _JITARMFPRCACHE_H
+#define _JITARMFPRCACHE_H
+
+#include "ArmEmitter.h"
+#include "../Gekko.h"
+#include "../PPCAnalyst.h"
+#include "JitRegCache.h"
+
+#define ARMFPUREGS 32
+using namespace ArmGen;
+
+class ArmFPRCache
+{
+private:
+	PPCCachedReg regs[32];
+	JRCPPC ArmCRegs[ARMFPUREGS];
+	JRCReg ArmRegs[ARMFPUREGS]; 
+	
+	int NUMPPCREG;
+	int NUMARMREG;
+
+	ARMReg *GetAllocationOrder(int &count);
+	ARMReg *GetPPCAllocationOrder(int &count);
+
+	ARMReg GetPPCReg(u32 preg, bool PS1, bool preLoad);
+
+protected:
+	ARMXEmitter *emit;
+	
+public:
+	ArmFPRCache();
+	~ArmFPRCache() {}
+
+	void Init(ARMXEmitter *emitter);
+	void Start(PPCAnalyst::BlockRegStats &stats);
+
+	void SetEmitter(ARMXEmitter *emitter) {emit = emitter;}
+	
+	ARMReg GetReg(bool AutoLock = true); // Return a ARM register we can use.
+	void Unlock(ARMReg V0);
+	void Flush();
+	ARMReg R0(u32 preg, bool preLoad = true); // Returns a cached register
+	ARMReg R1(u32 preg, bool preLoad = true);
+};
+#endif