diff options
| author | skidau <skidau@gmail.com> | 2010-09-02 15:10:12 +0000 |
|---|---|---|
| committer | skidau <skidau@gmail.com> | 2010-09-02 15:10:12 +0000 |
| commit | c08144f89320bc602d5864eee4e4f6e47bfb04b3 (patch) | |
| tree | c887f2ce07c56aae41db0d09c8869442e6001e2c /Source/Core | |
| parent | 38d6d539d2d5b20cae4bbfc7c5b28ab17e5ee1ae (diff) | |
Fixed F-Zero GX in JITIL 32bit builds by using a vmem mask for memory loads.
Enabled the lbzu instruction in JITIL.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6167 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp | 7 | ||||
| -rw-r--r-- | Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_LoadStore.cpp | 3 | ||||
| -rw-r--r-- | Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Tables.cpp | 2 |
3 files changed, 8 insertions, 4 deletions
diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp index 9320145b29..d3ea0dfbfa 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp @@ -543,7 +543,12 @@ static void regEmitMemLoad(RegInfo& RI, InstLoc I, unsigned Size) { if (RI.MakeProfile) { RI.Jit->MOV(32, M(&ProfiledLoads[RI.numProfiledLoads++]), R(ECX)); } - RI.Jit->TEST(32, R(ECX), Imm32(0x0C000000)); + u32 mem_mask = 0; + + if (SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU || SConfig::GetInstance().m_LocalCoreStartupParameter.iTLBHack) + mem_mask = 0x20000000; + + RI.Jit->TEST(32, R(ECX), Imm32(0x0C000000 | mem_mask)); FixupBranch argh = RI.Jit->J_CC(CC_Z); // Slow safe read using Memory::Read_Ux routines diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_LoadStore.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_LoadStore.cpp index c973dec728..65e2c4097f 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_LoadStore.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_LoadStore.cpp @@ -63,7 +63,7 @@ void JitIL::lXz(UGeckoInstruction inst) { case 32: val = ibuild.EmitLoad32(addr); break; //lwz case 40: val = ibuild.EmitLoad16(addr); break; //lhz - case 34: val = ibuild.EmitLoad8(addr); break; //lbz - lbzu crashes GFZP01 @ 0x8008575C + case 34: val = ibuild.EmitLoad8(addr); break; //lbz default: PanicAlert("lXz: invalid access size"); val = 0; break; } ibuild.EmitStoreGReg(val, inst.RD); @@ -72,7 +72,6 @@ void JitIL::lXz(UGeckoInstruction inst) void JitIL::lbzu(UGeckoInstruction inst) { INSTRUCTION_START JITDISABLE(LoadStore) - // FIXME: lbzu crashes GFZP01(F-Zero GX) @ 0x8008575C const IREmitter::InstLoc uAddress = ibuild.EmitAdd(ibuild.EmitLoadGReg(inst.RA), ibuild.EmitIntConst((int)inst.SIMM_16)); const IREmitter::InstLoc temp = ibuild.EmitLoad8(uAddress); ibuild.EmitStoreGReg(temp, inst.RD); diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Tables.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Tables.cpp index 7272cc265a..f9316d6e40 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Tables.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL_Tables.cpp @@ -82,7 +82,7 @@ static GekkoOPTemplate primarytable[] = {32, &JitIL::lXz}, //"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {33, &JitIL::lXz}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {34, &JitIL::lXz}, //"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, - {35, &JitIL::Default}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, + {35, &JitIL::lbzu}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {40, &JitIL::lXz}, //"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {41, &JitIL::lXz}, //"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {42, &JitIL::lha}, //"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, |