summaryrefslogtreecommitdiff
path: root/Source/Core
diff options
context:
space:
mode:
authorSintendo <bram.speeckaert@gmail.com>2015-02-21 11:12:03 +0100
committerSintendo <bram.speeckaert@gmail.com>2015-03-22 17:22:27 +0100
commitc19482c9a39f420b769ba9386bd4254fbcb309b9 (patch)
tree02c4167565ff356fc36e78688a7e34857b59373f /Source/Core
parentb35c34186c5a1ae04af7a5d8a4b1f213cc61ee0e (diff)
Add function to emit CMP, or TEST when possible
Also, a spelling mistake.
Diffstat (limited to 'Source/Core')
-rw-r--r--Source/Core/Common/x64Emitter.cpp12
-rw-r--r--Source/Core/Common/x64Emitter.h2
-rw-r--r--Source/Core/Core/DSP/Jit/DSPJitRegCache.cpp2
-rw-r--r--Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp2
4 files changed, 16 insertions, 2 deletions
diff --git a/Source/Core/Common/x64Emitter.cpp b/Source/Core/Common/x64Emitter.cpp
index cc3c51da08..7b46863d16 100644
--- a/Source/Core/Common/x64Emitter.cpp
+++ b/Source/Core/Common/x64Emitter.cpp
@@ -1278,6 +1278,18 @@ void XEmitter::MOV (int bits, const OpArg &a1, const OpArg &a2)
void XEmitter::TEST(int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(bits, nrmTEST, a1, a2);}
void XEmitter::CMP (int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(bits, nrmCMP, a1, a2);}
void XEmitter::XCHG(int bits, const OpArg &a1, const OpArg &a2) {WriteNormalOp(bits, nrmXCHG, a1, a2);}
+void XEmitter::CMP_or_TEST(int bits, const OpArg &a1, const OpArg &a2)
+{
+ CheckFlags();
+ if (a1.IsSimpleReg() && a2.IsImm() && a2.offset == 0) // turn 'CMP reg, 0' into shorter 'TEST reg, reg'
+ {
+ WriteNormalOp(bits, nrmTEST, a1, a1);
+ }
+ else
+ {
+ WriteNormalOp(bits, nrmCMP, a1, a2);
+ }
+}
void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a1, OpArg a2)
{
diff --git a/Source/Core/Common/x64Emitter.h b/Source/Core/Common/x64Emitter.h
index 23927cb88a..80c161ead4 100644
--- a/Source/Core/Common/x64Emitter.h
+++ b/Source/Core/Common/x64Emitter.h
@@ -465,6 +465,8 @@ public:
void MOV (int bits, const OpArg &a1, const OpArg &a2);
void TEST(int bits, const OpArg &a1, const OpArg &a2);
+ void CMP_or_TEST(int bits, const OpArg &a1, const OpArg &a2);
+
// Are these useful at all? Consider removing.
void XCHG(int bits, const OpArg &a1, const OpArg &a2);
void XCHG_AHAL();
diff --git a/Source/Core/Core/DSP/Jit/DSPJitRegCache.cpp b/Source/Core/Core/DSP/Jit/DSPJitRegCache.cpp
index 589ad41b15..357c8bf30f 100644
--- a/Source/Core/Core/DSP/Jit/DSPJitRegCache.cpp
+++ b/Source/Core/Core/DSP/Jit/DSPJitRegCache.cpp
@@ -756,7 +756,7 @@ void DSPJitRegCache::getReg(int reg, OpArg &oparg, bool load)
{
emitter.INT3();
}
- // no nead to actually emit code for load or rotate if caller doesn't
+ // no need to actually emit code for load or rotate if caller doesn't
// use the contents, but see above for a reason to force the load
movToHostReg(real_reg, load);
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
index 1cc0782980..948aa9a785 100644
--- a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
+++ b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
@@ -1154,7 +1154,7 @@ void Jit64::divwux(UGeckoInstruction inst)
MOV(32, R(EAX), gpr.R(a));
XOR(32, R(EDX), R(EDX));
gpr.KillImmediate(b, true, false);
- CMP(32, gpr.R(b), Imm32(0));
+ CMP_or_TEST(32, gpr.R(b), Imm32(0));
FixupBranch not_div_by_zero = J_CC(CC_NZ);
MOV(32, gpr.R(d), R(EDX));
if (inst.OE)