diff options
| author | skidau <skidau@gmail.com> | 2010-01-16 04:43:07 +0000 |
|---|---|---|
| committer | skidau <skidau@gmail.com> | 2010-01-16 04:43:07 +0000 |
| commit | efe20c93e839cdf5e378b8b77cda3146100e4bd8 (patch) | |
| tree | 85ce5f5384eeefaed170783901ad464e47a0d6a4 /Source/Core | |
| parent | fa5823ad9ae75b56576a11b2baddfec19825d423 (diff) | |
In the Interpreter, marked mtmsr as an "end of block" instruction, making it consistent with the JIT tables.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4849 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp b/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp index acf74ca0f9..3878723cce 100644 --- a/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp +++ b/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp @@ -236,6 +236,7 @@ void mtmsr(UGeckoInstruction _inst) { // Privileged? MSR = m_GPR[_inst.RS]; + m_EndBlock = true; } // Segment registers. MMU control. @@ -264,8 +265,8 @@ void mtsrin(UGeckoInstruction _inst) void mftb(UGeckoInstruction _inst) { int iIndex = (_inst.TBR >> 5) | ((_inst.TBR & 0x1F) << 5); - if (iIndex == 268) m_GPR[_inst.RD] = TL; - else if (iIndex == 269) m_GPR[_inst.RD] = TU; + if (iIndex == SPR_TL) m_GPR[_inst.RD] = TL; + else if (iIndex == SPR_TU) m_GPR[_inst.RD] = TU; else _dbg_assert_(POWERPC, 0); } |