diff options
| author | Bram Speeckaert <bram.speeckaert@guardsquare.com> | 2024-05-04 17:36:10 +0200 |
|---|---|---|
| committer | Bram Speeckaert <bram.speeckaert@guardsquare.com> | 2024-05-07 21:12:24 +0200 |
| commit | f7c97ae6545c39e6b16f1634a8e649c194836904 (patch) | |
| tree | 64177aaad8c23fb1593139dabb6dffa66cf17b3a /Source/Core | |
| parent | 0189692ea37f2fa3d590c72fdb1937ed56d98b83 (diff) | |
JitArm64: srawx - Conditionally skip temp reg allocation
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index 311bd31d91..dbcb6370ec 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -2009,9 +2009,11 @@ void JitArm64::srawx(UGeckoInstruction inst) } else { - gpr.BindToRegister(a, a == b || a == s); + const bool will_read = a == b || a == s; + gpr.BindToRegister(a, will_read); - ARM64Reg WA = gpr.GetReg(); + const bool allocate_reg = will_read || js.op->wantsCA; + ARM64Reg WA = allocate_reg ? gpr.GetReg() : gpr.R(a); LSL(EncodeRegTo64(WA), EncodeRegTo64(gpr.R(s)), 32); ASRV(EncodeRegTo64(WA), EncodeRegTo64(WA), EncodeRegTo64(gpr.R(b))); @@ -2024,7 +2026,8 @@ void JitArm64::srawx(UGeckoInstruction inst) ComputeCarry(WA); } - gpr.Unlock(WA); + if (allocate_reg) + gpr.Unlock(WA); } if (inst.Rc) |