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| author | flacs <tilkax@gmail.com> | 2015-06-06 17:31:55 +0200 |
|---|---|---|
| committer | flacs <tilkax@gmail.com> | 2015-06-06 17:31:55 +0200 |
| commit | d3e47dfcf573e3fef422517799a52e3b5aa5c91d (patch) | |
| tree | a786208a94712154d6bac5005bb622faa6509bfe /Source/UnitTests/Common/x64EmitterTest.cpp | |
| parent | f9b5571ddd49e212de229dd6567a5ae076e6fd1a (diff) | |
| parent | 794a311b114f6e7f561a847457e52ced296ba111 (diff) | |
Merge pull request #2496 from Tilka/fma4
Jit64: add FMA4 support to fmaddXX
Diffstat (limited to 'Source/UnitTests/Common/x64EmitterTest.cpp')
| -rw-r--r-- | Source/UnitTests/Common/x64EmitterTest.cpp | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/Source/UnitTests/Common/x64EmitterTest.cpp b/Source/UnitTests/Common/x64EmitterTest.cpp index adbdf76a77..6659542dee 100644 --- a/Source/UnitTests/Common/x64EmitterTest.cpp +++ b/Source/UnitTests/Common/x64EmitterTest.cpp @@ -1046,4 +1046,43 @@ FMA3_TEST(VFNMSUB, S, false) FMA3_TEST(VFMADDSUB, P, true) FMA3_TEST(VFMSUBADD, P, true) +// for VEX instructions that take the form op reg, reg, r/m, reg OR reg, reg, reg, r/m +#define VEX_RRMR_RRRM_TEST(Name, sizename) \ + TEST_F(x64EmitterTest, Name) \ + { \ + struct { \ + int bits; \ + std::vector<NamedReg> regs; \ + std::string out_name; \ + std::string size; \ + } regsets[] = { \ + { 64, xmmnames, "xmm0", sizename }, \ + }; \ + for (const auto& regset : regsets) \ + for (const auto& r : regset.regs) \ + { \ + emitter->Name(r.reg, XMM0, R(XMM0), r.reg); \ + emitter->Name(XMM0, XMM0, r.reg, MatR(R12)); \ + emitter->Name(XMM0, r.reg, MatR(R12), XMM0); \ + ExpectDisassembly(#Name " " + r.name+ ", " + regset.out_name + ", " + regset.out_name + ", " + r.name + " " \ + #Name " " + regset.out_name + ", " + regset.out_name + ", " + r.name + ", " + regset.size + " ptr ds:[r12] " \ + #Name " " + regset.out_name + ", " + r.name + ", " + regset.size + " ptr ds:[r12], " + regset.out_name); \ + } \ + } + +#define FMA4_TEST(Name, P, packed) \ + VEX_RRMR_RRRM_TEST(Name ## P ## S, packed ? "dqword" : "dword") \ + VEX_RRMR_RRRM_TEST(Name ## P ## D, packed ? "dqword" : "qword") + +FMA4_TEST(VFMADD, P, true) +FMA4_TEST(VFMADD, S, false) +FMA4_TEST(VFMSUB, P, true) +FMA4_TEST(VFMSUB, S, false) +FMA4_TEST(VFNMADD, P, true) +FMA4_TEST(VFNMADD, S, false) +FMA4_TEST(VFNMSUB, P, true) +FMA4_TEST(VFNMSUB, S, false) +FMA4_TEST(VFMADDSUB, P, true) +FMA4_TEST(VFMSUBADD, P, true) + } // namespace Gen |