diff options
| author | degasus <wickmarkus@web.de> | 2015-09-05 13:32:39 +0200 |
|---|---|---|
| committer | degasus <wickmarkus@web.de> | 2015-09-05 13:48:29 +0200 |
| commit | 24fec3ebca40a8adf187065e32adf6edea2e5919 (patch) | |
| tree | fffc397caa028d3fbfd411089c80f83befab4030 /Source | |
| parent | 36902c58eb257f162026b01441480686476fe396 (diff) | |
JitArm64: Fix float load & store
Diffstat (limited to 'Source')
| -rw-r--r-- | Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp index 08f3550050..c37da385a2 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp @@ -73,12 +73,12 @@ void JitArm64::lfXX(UGeckoInstruction inst) RegType type = !!(flags & BackPatchInfo::FLAG_SIZE_F64) ? REG_LOWER_PAIR : REG_DUP; - ARM64Reg VD = fpr.RW(inst.FD, type); - ARM64Reg addr_reg = W0; - gpr.Lock(W0, W30); fpr.Lock(Q0); + ARM64Reg VD = fpr.RW(inst.FD, type); + ARM64Reg addr_reg = W0; + if (update) { // Always uses RA @@ -262,12 +262,12 @@ void JitArm64::stfXX(UGeckoInstruction inst) u32 imm_addr = 0; bool is_immediate = false; - ARM64Reg V0 = fpr.R(inst.FS, REG_IS_LOADED); - ARM64Reg addr_reg = W1; - gpr.Lock(W0, W1, W30); fpr.Lock(Q0); + ARM64Reg V0 = fpr.R(inst.FS, REG_IS_LOADED); + ARM64Reg addr_reg = W1; + if (update) { // Always uses RA |
