diff options
| author | Markus Wick <degasus@users.noreply.github.com> | 2020-06-29 09:20:19 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-29 09:20:19 +0200 |
| commit | 4095fb6c200022ef34527fcf1825a4d8219f0543 (patch) | |
| tree | b0e0d06bc411523d74d7eb9efccc9a0f75586d1c /Source | |
| parent | 961f93701065f099ba68fb610f699f89b804a2b4 (diff) | |
| parent | 089ffb9ef48858ccc08d139134853afe142a0401 (diff) | |
Merge pull request #8911 from OatmealDome/arm64-fastmem-off
JitArm64: Don't assume fastmem arena is available
Diffstat (limited to 'Source')
| -rw-r--r-- | Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp | 6 | ||||
| -rw-r--r-- | Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp index 3df65cf644..74955b66bf 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp @@ -121,7 +121,7 @@ void JitArm64::SafeLoadToReg(u32 dest, s32 addr, s32 offsetReg, u32 flags, s32 o if (is_immediate) mmio_address = PowerPC::IsOptimizableMMIOAccess(imm_addr, access_size); - if (is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr)) + if (jo.fastmem_arena && is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr)) { EmitBackpatchRoutine(flags, true, false, dest_reg, XA, BitSet32(0), BitSet32(0)); } @@ -256,7 +256,7 @@ void JitArm64::SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s STR(INDEX_UNSIGNED, X0, PPC_REG, PPCSTATE_OFF(gather_pipe_ptr)); js.fifoBytesSinceCheck += accessSize >> 3; } - else if (is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr)) + else if (jo.fastmem_arena && is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr)) { MOVI2R(XA, imm_addr); EmitBackpatchRoutine(flags, true, false, RS, XA, BitSet32(0), BitSet32(0)); @@ -599,7 +599,7 @@ void JitArm64::dcbz(UGeckoInstruction inst) { INSTRUCTION_START JITDISABLE(bJITLoadStoreOff); - FALLBACK_IF(jo.memcheck); + FALLBACK_IF(jo.memcheck || !jo.fastmem_arena); FALLBACK_IF(SConfig::GetInstance().bLowDCBZHack); int a = inst.RA, b = inst.RB; diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp index 78e7168f72..b158560cb2 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp @@ -167,7 +167,7 @@ void JitArm64::lfXX(UGeckoInstruction inst) fprs_in_use[0] = 0; // Q0 fprs_in_use[VD - Q0] = 0; - if (is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr)) + if (jo.fastmem_arena && is_immediate && PowerPC::IsOptimizableRAMAddress(imm_addr)) { EmitBackpatchRoutine(flags, true, false, VD, XA, BitSet32(0), BitSet32(0)); } @@ -384,7 +384,7 @@ void JitArm64::stfXX(UGeckoInstruction inst) MOVI2R(gpr.R(a), imm_addr); } } - else if (PowerPC::IsOptimizableRAMAddress(imm_addr)) + else if (jo.fastmem_arena && PowerPC::IsOptimizableRAMAddress(imm_addr)) { EmitBackpatchRoutine(flags, true, false, V0, XA, BitSet32(0), BitSet32(0)); } |