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authordegasus <wickmarkus@web.de>2016-02-11 11:19:19 +0100
committerdegasus <wickmarkus@web.de>2016-02-25 19:47:06 +0100
commit6572790d8b2e2f82e1cb0d20bbeea60cfb8fbd13 (patch)
tree679daf6e79e24bf840e41aa4370d7d5a21fb5689 /Source
parent55062951236723d8d72504cb487df7101d55f9bd (diff)
JitArm64: Track singles in ps_mergeXX.
Diffstat (limited to 'Source')
-rw-r--r--Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp29
1 files changed, 17 insertions, 12 deletions
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
index c17c22b549..04e9d2ed76 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
@@ -25,36 +25,41 @@ void JitArm64::ps_mergeXX(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, d = inst.FD;
- ARM64Reg VA = fpr.R(a, REG_REG);
- ARM64Reg VB = fpr.R(b, REG_REG);
- ARM64Reg VD = fpr.RW(d, REG_REG);
+ bool singles = fpr.IsSingle(a) && fpr.IsSingle(b);
+ RegType type = singles ? REG_REG_SINGLE : REG_REG;
+ u8 size = singles ? 32 : 64;
+ ARM64Reg (*reg_encoder)(ARM64Reg) = singles ? EncodeRegToDouble : EncodeRegToQuad;
+
+ ARM64Reg VA = fpr.R(a, type);
+ ARM64Reg VB = fpr.R(b, type);
+ ARM64Reg VD = fpr.RW(d, type);
switch (inst.SUBOP10)
{
case 528: //00
- m_float_emit.TRN1(64, VD, VA, VB);
+ m_float_emit.TRN1(size, VD, VA, VB);
break;
case 560: //01
- m_float_emit.INS(64, VD, 0, VA, 0);
- m_float_emit.INS(64, VD, 1, VB, 1);
+ m_float_emit.INS(size, VD, 0, VA, 0);
+ m_float_emit.INS(size, VD, 1, VB, 1);
break;
case 592: //10
if (d != a && d != b)
{
- m_float_emit.INS(64, VD, 0, VA, 1);
- m_float_emit.INS(64, VD, 1, VB, 0);
+ m_float_emit.INS(size, VD, 0, VA, 1);
+ m_float_emit.INS(size, VD, 1, VB, 0);
}
else
{
ARM64Reg V0 = fpr.GetReg();
- m_float_emit.INS(64, V0, 0, VA, 1);
- m_float_emit.INS(64, V0, 1, VB, 0);
- m_float_emit.ORR(VD, V0, V0);
+ m_float_emit.INS(size, V0, 0, VA, 1);
+ m_float_emit.INS(size, V0, 1, VB, 0);
+ m_float_emit.ORR(reg_encoder(VD), reg_encoder(V0), reg_encoder(V0));
fpr.Unlock(V0);
}
break;
case 624: //11
- m_float_emit.TRN2(64, VD, VA, VB);
+ m_float_emit.TRN2(size, VD, VA, VB);
break;
default:
_assert_msg_(DYNA_REC, 0, "ps_merge - invalid op");