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authorPierre Bourdon <delroth@gmail.com>2018-08-11 01:12:49 +0200
committerPierre Bourdon <delroth@gmail.com>2018-08-11 01:12:49 +0200
commitc8d4fa530831d00b6e20f33fcd03ce0012bbb5c4 (patch)
tree87aafe63d3da476fee2f235558f139dddc830e0c /Source
parent185f971e2a3d37a607da48f393e5b8980d76cb04 (diff)
Jit64: fix crset implementation
At some point SetCRFieldBit was modified to operate on RSCRATCH, but the function was only partially changed. As such, setting SO, GT or LT would write the right bit to cr_field, but then cr_field would just get overwritten with RSCRATCH, undoing the work.
Diffstat (limited to 'Source')
-rw-r--r--Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
index 9e103808aa..1cb5ddbbfa 100644
--- a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
+++ b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
@@ -131,7 +131,7 @@ void Jit64::SetCRFieldBit(int field, int bit)
switch (bit)
{
case PowerPC::CR_SO_BIT:
- BTS(64, PPCSTATE(cr_val[field]), Imm8(61));
+ BTS(64, R(RSCRATCH), Imm8(61));
break;
case PowerPC::CR_EQ_BIT:
@@ -140,11 +140,11 @@ void Jit64::SetCRFieldBit(int field, int bit)
break;
case PowerPC::CR_GT_BIT:
- BTR(64, PPCSTATE(cr_val[field]), Imm8(63));
+ BTR(64, R(RSCRATCH), Imm8(63));
break;
case PowerPC::CR_LT_BIT:
- BTS(64, PPCSTATE(cr_val[field]), Imm8(62));
+ BTS(64, R(RSCRATCH), Imm8(62));
break;
}