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authorMichael Maltese <michaeljosephmaltese@gmail.com>2017-06-03 14:38:04 -0700
committerMichael Maltese <michaeljosephmaltese@gmail.com>2017-06-03 15:16:39 -0700
commit3872437eacdfafc2de36b2bcc191adce481acfc1 (patch)
treea46d4f16889643298bd84776dfbcb85b5c6137c9 /docs
parent2267ddeb1710fe5b9d0ace3916650b7d315883f5 (diff)
Add sample logs for GBA ucode register state/HW interactions
Diffstat (limited to 'docs')
-rw-r--r--docs/DSP/free_dsp_rom/GBA-BillyHatcher-log.txt388
-rw-r--r--docs/DSP/free_dsp_rom/GBA-CrystalChronicles-log.txt355
-rw-r--r--docs/DSP/free_dsp_rom/GBA-FourSwordsAdventures-log.txt457
-rw-r--r--docs/DSP/free_dsp_rom/GBA-MetroidPrime-log.txt1264
4 files changed, 2464 insertions, 0 deletions
diff --git a/docs/DSP/free_dsp_rom/GBA-BillyHatcher-log.txt b/docs/DSP/free_dsp_rom/GBA-BillyHatcher-log.txt
new file mode 100644
index 0000000000..0f662b352d
--- /dev/null
+++ b/docs/DSP/free_dsp_rom/GBA-BillyHatcher-log.txt
@@ -0,0 +1,388 @@
+dsp dmem write 0010 = 0000
+dsp dmem write 0011 = 0000
+dsp dmem write 0012 = 0000
+dsp dmem write 0013 = 0000
+dsp dmem write 0014 = 0000
+dsp dmem write 0015 = 0000
+dsp dmem write 0016 = 0000
+dsp dmem write 0017 = 0000
+dsp dmem write 0018 = 0000
+dsp dmem write 0019 = 0000
+dsp dmem write 001a = 0000
+dsp dmem write 001b = 0000
+dsp dmem write 001c = 0000
+dsp dmem write 001d = 0000
+dsp dmem write 001e = 0000
+dsp dmem write 001f = 0000
+dsp dmem write 0020 = 0000
+dsp dmem write 0021 = 0000
+dsp dmem write 0022 = 0000
+dsp dmem write 0023 = 0000
+dsp dmem write 0024 = 0000
+dsp dmem write 0025 = 0000
+dsp dmem write 0026 = 0000
+dsp dmem write 0027 = 0000
+dsp dmem write 0028 = 0000
+dsp dmem write 0029 = 0000
+dsp dmem write 002a = 0000
+dsp dmem write 002b = 0000
+dsp dmem write 002c = 0000
+dsp dmem write 002d = 0000
+dsp dmem write 002e = 0000
+dsp dmem write 002f = 0000
+0093 : Coefficient Read @ 1456
+dsp dmem read 1456 = 102f
+009e : Coefficient Read @ 15f6
+dsp dmem read 15f6 = 7f65
+00a1 : Coefficient Read @ 1766
+dsp dmem read 1766 = 0273
+call at 00a5 -> 88e5
+STARTED 00a4 -> 88e5
+== Registers ==
+AR0: 0000 AR1: 0030 AR2: 001f AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 0073 AX0.L: 34c0 AX1.H: 0000 AX1.L: 1000
+AC0.H: 007f AC0.M: 6500 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0073 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem read 001f = 0000
+dsp dmem read 0020 = 0000
+dsp dmem write 001f = 6573
+dsp dmem write 0020 = 0000
+STOPPED: 00a6
+== Registers ==
+AR0: 0000 AR1: 002f AR2: 0020 AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 0073 AX0.L: 34c0 AX1.H: 0000 AX1.L: 1000
+AC0.H: 007f AC0.M: 6573 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3950
+dsp dmem read 0000 = ceb4
+call at 00ad -> 8809
+STARTED 00ac -> 8809
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0020 AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 00ce AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00ce AC0.L: b400
+AC1.H: 0000 AC1.M: b400 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem write 0020 = 0000
+dsp dmem write 0020 = b4ce
+STOPPED: 00ae
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0021 AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 00ce AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00ce AC0.L: b400
+AC1.H: 0000 AC1.M: b4ce AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3958
+call at 00af -> 8723
+STARTED 00ae -> 8723
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0021 AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 00ce AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00ce AC0.L: b400
+AC1.H: 0000 AC1.M: b4ce AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3958
+dsp dmem write 0021 = d1bd
+STOPPED: 00b0
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0020 AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 00ce AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00ce AC0.L: b400
+AC1.H: 0000 AC1.M: d1bd AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3978
+00b4 : Coefficient Read @ 166c
+dsp dmem read 166c = 06f2
+00b9 : Coefficient Read @ 1231
+dsp dmem read 1231 = 64fc
+call at 00be -> 88e5
+STARTED 00bd -> 88e5
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 001e AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 0064 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 6f00 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0064 AC1.L: fc00
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem read 001e = 0000
+dsp dmem read 001f = 6573
+dsp dmem write 001e = 6f64
+dsp dmem write 001f = 6573
+STOPPED: 00bf
+== Registers ==
+AR0: 0001 AR1: 002e AR2: 001f AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 0064 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 6f64 AC0.L: 6573
+AC1.H: 0000 AC1.M: 0000 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3940
+dsp dmem read 0001 = 4f51
+call at 00c6 -> 8809
+STARTED 00c5 -> 8809
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 001f AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 004f AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 004f AC0.L: 5100
+AC1.H: 0000 AC1.M: 5100 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem write 001f = 6573
+dsp dmem write 001f = 514f
+STOPPED: 00c7
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0020 AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 004f AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 004f AC0.L: 5100
+AC1.H: 0000 AC1.M: 514f AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3940
+call at 00c8 -> 8723
+STARTED 00c7 -> 8723
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0020 AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 004f AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 004f AC0.L: 5100
+AC1.H: 0000 AC1.M: 514f AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3940
+dsp dmem write 0020 = 3e2b
+STOPPED: 00c9
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 001f AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0000 IX3: 0000
+AX0.H: 004f AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 004f AC0.L: 5100
+AC1.H: 0000 AC1.M: 3e2b AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem read 0005 = 0001
+00f9 : Coefficient Read @ 1285
+dsp dmem read 1285 = 5aff
+dsp dmem read 0003 = 0000
+call at 0101 -> 8809
+STARTED 0100 -> 8809
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0010 AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3978
+dsp dmem write 0010 = 0000
+dsp dmem write 0011 = 0000
+STOPPED: 0102
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0012 AR3: 0f08
+IX0: 8027 IX1: 93d0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3964
+dsp dmem write 0013 = 0000
+dsp dmem write 0014 = 0000
+dsp dmem read 0007 = 7390
+010c : Coefficient Read @ 11b8
+dsp dmem read 11b8 = 007f
+call at 0110 -> 81f4
+STARTED 010f -> 81f4
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0012 AR3: 0013
+IX0: 8027 IX1: 93d0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0070 AC0.L: 0000
+AC1.H: 0000 AC1.M: 7390 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3970
+dsp dmem write 0013 = 0000
+dsp dmem write 0014 = 7390
+STOPPED: 0111
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0015
+IX0: 8027 IX1: 93d0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0070 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 7390
+PROD: 0000000000070000
+SR: 3964
+call at 0113 -> 8458
+STARTED 0112 -> 8458
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0015
+IX0: 8027 IX1: 93d0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0070 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 7390 AC1.L: 0000
+PROD: 0000000000070000
+SR: 3940
+dsp dmem write 0015 = 0000
+dsp dmem write 0016 = 7397
+STOPPED: 0114
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0017
+IX0: 8027 IX1: 93d0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 7397
+PROD: 0000000000070000
+SR: 3964
+dsp dmem read 0006 = 0003
+011b : Coefficient Read @ 165b
+dsp dmem read 165b = 0000
+call at 011c -> 88e5
+STARTED 011b -> 88e5
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0015 AR3: 0017
+IX0: 8027 IX1: 93d0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0003 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 7397
+PROD: 0000000000070000
+SR: 7964
+dsp dmem read 0015 = 0000
+dsp dmem read 0016 = 7397
+dsp dmem write 0015 = 0003
+dsp dmem write 0016 = 7397
+STOPPED: 011d
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0016 AR3: 0017
+IX0: 8027 IX1: 93d0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0003 AC0.L: 7397
+AC1.H: 0000 AC1.M: 0000 AC1.L: 7397
+PROD: 0000000000070000
+SR: 7960
+dsp dmem write 0016 = 0003
+dsp dmem write 0017 = 7390
+0125 : Coefficient Read @ 1723
+dsp dmem read 1723 = ffe0
+0128 : Coefficient Read @ 166b
+dsp dmem read 166b = 0000
+call at 0129 -> 88e5
+STARTED 0128 -> 88e5
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0016 AR3: 0017
+IX0: 8027 IX1: 93d0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: ffff AC0.M: ffff AC0.L: fe00
+AC1.H: 0000 AC1.M: 0000 AC1.L: 7397
+PROD: 0000000000070000
+SR: 7968
+dsp dmem read 0016 = 0003
+dsp dmem read 0017 = 7390
+dsp dmem write 0016 = 0003
+dsp dmem write 0017 = 7190
+STOPPED: 012a
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8027 IX1: 93d0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0003 AC0.L: 7190
+AC1.H: 0000 AC1.M: 0003 AC1.L: 7390
+PROD: 0000000000070000
+SR: 7961
+0132 : Coefficient Read @ 1491
+dsp dmem read 1491 = 6a0f
+0137 : Coefficient Read @ 1468
+dsp dmem read 1468 = f808
+0139 : Coefficient Read @ 11fc
+dsp dmem read 11fc = 0003
+013d : Coefficient Read @ 11b8
+dsp dmem read 11b8 = 007f
+dsp dmem read 0012 = 0000
+dsp dmem write 0012 = 5c32
+dsp dmem read 0011 = 0000
+dsp dmem write 0011 = 0001
+dsp dmem read 0011 = 0001
+dsp dmem read 0012 = 5c32
+dsp dmem read 0012 = 5c32
+dsp dmem read 0011 = 0001
+dsp dmem read 0012 = 5c32
+017a : Coefficient Read @ 15f1
+dsp dmem read 15f1 = 0200
+0194 : Coefficient Read @ 10ca
+dsp dmem read 10ca = 3461
+0198 : Coefficient Read @ 1043
+dsp dmem read 1043 = 0076
+dsp dmem write 0022 = eef6
+019f : Coefficient Read @ 1259
+dsp dmem read 1259 = 6143
+01a1 : Coefficient Read @ 16fe
+dsp dmem read 16fe = 0008
+dsp dmem write 0023 = bdf9
+dsp dmem read 0008 = 802c
+dsp dmem read 0009 = 34e0
+call at 01b2 -> 808b
+STARTED 01b1 -> 808b
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8027 IX1: dcb2 IX2: 3f80 IX3: 0000
+AX0.H: 802c AX0.L: 34e0 AX1.H: 0020 AX1.L: 0008
+AC0.H: 506d AC0.M: bdf9 AC0.L: 0000
+AC1.H: 0034 AC1.M: dcb2 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3958
+dsp dmem write ffce = 802c
+dsp dmem write ffcf = 34e0
+dsp dmem write ffc9 = 0001
+dsp dmem write ffcd = 0020
+dsp dmem write ffcb = 0008
+dsp dmem read ffc9 = 0001
+STOPPED: 01b3
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8027 IX1: dcb2 IX2: 3f80 IX3: 0000
+AX0.H: 802c AX0.L: 34e0 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0034 AC1.M: dcb2 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3964
+call at 0044 -> 807e
+STARTED 0043 -> 807e
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8027 IX1: dcb2 IX2: 3f80 IX3: 0000
+AX0.H: 802c AX0.L: 34e0 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0034 AC1.M: dcb2 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3964
+dsp dmem read fffc = 5cd1
+STOPPED: 0045
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8027 IX1: dcb2 IX2: 3f80 IX3: 0000
+AX0.H: 802c AX0.L: 34e0 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 5cd1 AC0.L: 0000
+AC1.H: 0034 AC1.M: dcb2 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3964
+dsp dmem write fffc = dcd1
+dsp dmem write fffd = 0003
+dsp dmem write fffb = 0001
+call at 004d -> 8078
+STARTED 004c -> 8078
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8027 IX1: dcb2 IX2: 3f80 IX3: 0000
+AX0.H: 802c AX0.L: 34e0 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 5cd1 AC0.L: 0000
+AC1.H: 0034 AC1.M: dcb2 AC1.L: 0008
+PROD: 0000000000070000
+SR: 7964
diff --git a/docs/DSP/free_dsp_rom/GBA-CrystalChronicles-log.txt b/docs/DSP/free_dsp_rom/GBA-CrystalChronicles-log.txt
new file mode 100644
index 0000000000..1bb8dd6a81
--- /dev/null
+++ b/docs/DSP/free_dsp_rom/GBA-CrystalChronicles-log.txt
@@ -0,0 +1,355 @@
+dsp dmem write 0010 = 0000
+dsp dmem write 0011 = 0000
+dsp dmem write 0012 = 0000
+dsp dmem write 0013 = 0000
+dsp dmem write 0014 = 0000
+dsp dmem write 0015 = 0000
+dsp dmem write 0016 = 0000
+dsp dmem write 0017 = 0000
+dsp dmem write 0018 = 0000
+dsp dmem write 0019 = 0000
+dsp dmem write 001a = 0000
+dsp dmem write 001b = 0000
+dsp dmem write 001c = 0000
+dsp dmem write 001d = 0000
+dsp dmem write 001e = 0000
+dsp dmem write 001f = 0000
+dsp dmem write 0020 = 0000
+dsp dmem write 0021 = 0000
+dsp dmem write 0022 = 0000
+dsp dmem write 0023 = 0000
+dsp dmem write 0024 = 0000
+dsp dmem write 0025 = 0000
+dsp dmem write 0026 = 0000
+dsp dmem write 0027 = 0000
+dsp dmem write 0028 = 0000
+dsp dmem write 0029 = 0000
+dsp dmem write 002a = 0000
+dsp dmem write 002b = 0000
+dsp dmem write 002c = 0000
+dsp dmem write 002d = 0000
+dsp dmem write 002e = 0000
+dsp dmem write 002f = 0000
+Coefficient Read @ 1456 = 102f
+dsp dmem read 1456 = 102f
+Coefficient Read @ 15f6 = 7f65
+dsp dmem read 15f6 = 7f65
+Coefficient Read @ 1766 = 0273
+dsp dmem read 1766 = 0273
+call at 00a5 -> 88e5
+STARTED 00a4 -> 88e5
+== Registers ==
+AR0: 0000 AR1: 0030 AR2: 001f AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 0073 AX0.L: 72c0 AX1.H: 0000 AX1.L: 1000
+AC0.H: 007f AC0.M: 6500 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0073 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem read 001f = 0000
+dsp dmem read 0020 = 0000
+dsp dmem write 001f = 6573
+dsp dmem write 0020 = 0000
+STOPPED: 00a6
+== Registers ==
+AR0: 0000 AR1: 002f AR2: 0020 AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 0073 AX0.L: 72c0 AX1.H: 0000 AX1.L: 1000
+AC0.H: 007f AC0.M: 6573 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3950
+dsp dmem read 0000 = c79a
+call at 00ad -> 8809
+STARTED 00ac -> 8809
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0020 AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 00c7 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00c7 AC0.L: 9a00
+AC1.H: 0000 AC1.M: 9a00 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem write 0020 = 0000
+dsp dmem write 0020 = 9ac7
+STOPPED: 00ae
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0021 AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 00c7 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00c7 AC0.L: 9a00
+AC1.H: 0000 AC1.M: 9ac7 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3958
+call at 00af -> 8723
+STARTED 00ae -> 8723
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0021 AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 00c7 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00c7 AC0.L: 9a00
+AC1.H: 0000 AC1.M: 9ac7 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3958
+dsp dmem write 0021 = ffb4
+STOPPED: 00b0
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0020 AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 00c7 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00c7 AC0.L: 9a00
+AC1.H: 0000 AC1.M: ffb4 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3978
+Coefficient Read @ 166c = 06f2
+dsp dmem read 166c = 06f2
+Coefficient Read @ 1231 = 64fc
+dsp dmem read 1231 = 64fc
+call at 00be -> 88e5
+STARTED 00bd -> 88e5
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 001e AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 0064 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 6f00 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0064 AC1.L: fc00
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem read 001e = 0000
+dsp dmem read 001f = 6573
+dsp dmem write 001e = 6f64
+dsp dmem write 001f = 6573
+STOPPED: 00bf
+== Registers ==
+AR0: 0001 AR1: 002e AR2: 001f AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 0064 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 6f64 AC0.L: 6573
+AC1.H: 0000 AC1.M: 0000 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3940
+dsp dmem read 0001 = afc4
+call at 00c6 -> 8809
+STARTED 00c5 -> 8809
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 001f AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 00af AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00af AC0.L: c400
+AC1.H: 0000 AC1.M: c400 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem write 001f = 6573
+dsp dmem write 001f = c4af
+STOPPED: 00c7
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0020 AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 00af AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00af AC0.L: c400
+AC1.H: 0000 AC1.M: c4af AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3978
+call at 00c8 -> 8723
+STARTED 00c7 -> 8723
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0020 AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 00af AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00af AC0.L: c400
+AC1.H: 0000 AC1.M: c4af AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3978
+dsp dmem write 0020 = abcb
+STOPPED: 00c9
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 001f AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0000 IX3: 0000
+AX0.H: 00af AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00af AC0.L: c400
+AC1.H: 0000 AC1.M: abcb AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3958
+dsp dmem read 0005 = 0002
+Coefficient Read @ 1285 = 5aff
+dsp dmem read 1285 = 5aff
+dsp dmem read 0003 = 0006
+call at 0101 -> 8809
+STARTED 0100 -> 8809
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0010 AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0001 IX3: 0000
+AX0.H: 0060 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0060 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0002 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3978
+dsp dmem write 0010 = 0000
+dsp dmem write 0011 = 0062
+STOPPED: 0102
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0012 AR3: 0f45
+IX0: 8021 IX1: ba38 IX2: 0001 IX3: 0000
+AX0.H: 0060 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0060 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0062 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem write 0013 = 0060
+dsp dmem write 0014 = 0000
+dsp dmem read 0007 = e058
+Coefficient Read @ 11b8 = 007f
+dsp dmem read 11b8 = 007f
+call at 0110 -> 81f4
+STARTED 010f -> 81f4
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0012 AR3: 0013
+IX0: 8021 IX1: ba38 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0070 AC0.L: 0000
+AC1.H: 0000 AC1.M: e058 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3970
+dsp dmem write 0013 = 0000
+dsp dmem write 0014 = e058
+STOPPED: 0111
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0015
+IX0: 8021 IX1: ba38 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0070 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: e058
+PROD: 0000000000070000
+SR: 3964
+call at 0113 -> 8458
+STARTED 0112 -> 8458
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0015
+IX0: 8021 IX1: ba38 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0070 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: e058 AC1.L: 0000
+PROD: 0000000000070000
+SR: 3970
+dsp dmem write 0015 = 0000
+dsp dmem write 0016 = e05f
+STOPPED: 0114
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0017
+IX0: 8021 IX1: ba38 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: e05f
+PROD: 0000000000070000
+SR: 3964
+dsp dmem read 0006 = 0002
+Coefficient Read @ 165b = 0000
+dsp dmem read 165b = 0000
+call at 011c -> 88e5
+STARTED 011b -> 88e5
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0015 AR3: 0017
+IX0: 8021 IX1: ba38 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0002 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: e05f
+PROD: 0000000000070000
+SR: 7964
+dsp dmem read 0015 = 0000
+dsp dmem read 0016 = e05f
+dsp dmem write 0015 = 0002
+dsp dmem write 0016 = e05f
+STOPPED: 011d
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0016 AR3: 0017
+IX0: 8021 IX1: ba38 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0002 AC0.L: e05f
+AC1.H: 0000 AC1.M: 0000 AC1.L: e05f
+PROD: 0000000000070000
+SR: 7960
+dsp dmem write 0016 = 0002
+dsp dmem write 0017 = e058
+Coefficient Read @ 1723 = ffe0
+dsp dmem read 1723 = ffe0
+Coefficient Read @ 166b = 0000
+dsp dmem read 166b = 0000
+call at 0129 -> 88e5
+STARTED 0128 -> 88e5
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0016 AR3: 0017
+IX0: 8021 IX1: ba38 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: ffff AC0.M: ffff AC0.L: fe00
+AC1.H: 0000 AC1.M: 0000 AC1.L: e05f
+PROD: 0000000000070000
+SR: 7968
+dsp dmem read 0016 = 0002
+dsp dmem read 0017 = e058
+dsp dmem write 0016 = 0002
+dsp dmem write 0017 = de58
+STOPPED: 012a
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8021 IX1: ba38 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0002 AC0.L: de58
+AC1.H: 0000 AC1.M: 0002 AC1.L: e058
+PROD: 0000000000070000
+SR: 7961
+Coefficient Read @ 1491 = 6a0f
+dsp dmem read 1491 = 6a0f
+Coefficient Read @ 1468 = f808
+dsp dmem read 1468 = f808
+Coefficient Read @ 11fc = 0003
+dsp dmem read 11fc = 0003
+Coefficient Read @ 11b8 = 007f
+dsp dmem read 11b8 = 007f
+dsp dmem read 0012 = 0000
+dsp dmem write 0012 = 374b
+dsp dmem read 0011 = 0062
+dsp dmem write 0011 = 0063
+dsp dmem read 0011 = 0063
+dsp dmem read 0012 = 374b
+dsp dmem read 0012 = 374b
+dsp dmem read 0011 = 0063
+dsp dmem read 0012 = 374b
+Coefficient Read @ 15f1 = 0200
+dsp dmem read 15f1 = 0200
+Coefficient Read @ 10e2 = 376f
+dsp dmem read 10e2 = 376f
+Coefficient Read @ 103b = 0065
+dsp dmem read 103b = 0065
+dsp dmem write 0022 = 8a87
+Coefficient Read @ 1229 = 657c
+dsp dmem read 1229 = 657c
+Coefficient Read @ 11f8 = 0009
+dsp dmem read 11f8 = 0009
+dsp dmem write 0023 = d2b8
+dsp dmem read 0008 = 8032
+dsp dmem read 0009 = 72e0
+call at 01b2 -> 808b
+STARTED 01b1 -> 808b
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8021 IX1: b7cb IX2: 3f80 IX3: 0000
+AX0.H: 8032 AX0.L: 72e0 AX1.H: 0020 AX1.L: 0008
+AC0.H: 1b23 AC0.M: d2b8 AC0.L: 0000
+AC1.H: 0037 AC1.M: b7cb AC1.L: 0009
+PROD: 0000000000070000
+SR: 3978
+dsp dmem write ffce = 8032
+dsp dmem write ffcf = 72e0
+dsp dmem write ffc9 = 0001
+dsp dmem write ffcd = 0020
+dsp dmem write ffcb = 0008
+dsp dmem read ffc9 = 0001
+STOPPED: 01b3
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8021 IX1: b7cb IX2: 3f80 IX3: 0000
+AX0.H: 8032 AX0.L: 72e0 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0037 AC1.M: b7cb AC1.L: 0009
+PROD: 0000000000070000
+SR: 3964
diff --git a/docs/DSP/free_dsp_rom/GBA-FourSwordsAdventures-log.txt b/docs/DSP/free_dsp_rom/GBA-FourSwordsAdventures-log.txt
new file mode 100644
index 0000000000..9066f3cc78
--- /dev/null
+++ b/docs/DSP/free_dsp_rom/GBA-FourSwordsAdventures-log.txt
@@ -0,0 +1,457 @@
+// Initial ucode load
+STARTED 80b5 -> 80b5
+== Registers ==
+AR0: 0000 AR1: 0000 AR2: 0000 AR3: 0000
+IX0: 8049 IX1: 36a0 IX2: 0000 IX3: 1d20
+AX0.H: 0000 AX0.L: 0000 AX1.H: 0000 AX1.L: 0000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: d001 AC1.L: 0000
+PROD: 0000000000000000
+SR: 2064
+80d5 : dsp dmem write ffce = 8049
+80d7 : dsp dmem write ffcf = 36a0
+80db : dsp dmem write ffc9 = 0002
+80dd : dsp dmem write ffcd = 0000
+80df : dsp dmem write ffcb = 1d20
+DMA pc: 80df, Control: 0006, Address: 804936a0, DSP Address: 0000, Size: 1d20
+Core/HW/DSPLLE/DSPHost.cpp:70 N[DSPLLE]: g_dsp.iram_crc: 2fcdf1ec
+Core/DSP/DSPHWInterface.cpp:264 N[DSPLLE]: *** Copy new UCode from 0x804936a0 to 0x0000
+80e1 : dsp dmem read ffc9 = 0002
+STOPPED: 80e5 -> 0000
+== Registers ==
+AR0: 0000 AR1: 0000 AR2: 0000 AR3: 0000
+IX0: 8049 IX1: 36a0 IX2: 0000 IX3: 1d20
+AX0.H: 0000 AX0.L: 0000 AX1.H: 0000 AX1.L: 0000
+AC0.H: 0000 AC0.M: 0002 AC0.L: 0000
+AC1.H: 0000 AC1.M: 1d20 AC1.L: 0000
+PROD: 0000000000000000
+SR: 2060
+
+// GBA ucode load
+// - jumps to AR0
+STARTED 80b5 -> 80b5
+== Registers ==
+AR0: 0010 AR1: 0393 AR2: 0420 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0380
+AX0.H: 8000 AX0.L: 0000 AX1.H: 0000 AX1.L: 0000
+AC0.H: 0000 AC0.M: 0001 AC0.L: 0000
+AC1.H: 0000 AC1.M: 8000 AC1.L: 0000
+PROD: 0000000000000000
+SR: 2064
+80d5 : dsp dmem write ffce = 8049
+80d7 : dsp dmem write ffcf = 85d0
+80db : dsp dmem write ffc9 = 0002
+80dd : dsp dmem write ffcd = 0000
+80df : dsp dmem write ffcb = 0380
+DMA pc: 80df, Control: 0006, Address: 804985d0, DSP Address: 0000, Size: 0380
+Core/HW/DSPLLE/DSPHost.cpp:70 N[DSPLLE]: g_dsp.iram_crc: dd7e72d5
+Core/HW/DSPLLE/DSPSymbols.cpp:84 E[DSPLLE]: Bah! ReadAnnotatedAssembly couldn't find the file ../../docs/DSP/DSP_UC_GBA.txt
+Core/DSP/DSPHWInterface.cpp:264 N[DSPLLE]: *** Copy new UCode from 0x804985d0 to 0x0000 (crc: dd7e72d5)
+80e1 : dsp dmem read ffc9 = 0002
+STOPPED: 80e5 -> 0010
+== Registers ==
+AR0: 0010 AR1: 0393 AR2: 0420 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0380
+AX0.H: 8000 AX0.L: 0000 AX1.H: 0000 AX1.L: 0000
+AC0.H: 0000 AC0.M: 0002 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0380 AC1.L: 0000
+PROD: 0000000000000000
+SR: 2060
+
+// skip some boring stuff
+
+dsp dmem write 0010 = 0000
+dsp dmem write 0011 = 0000
+dsp dmem write 0012 = 0000
+dsp dmem write 0013 = 0000
+dsp dmem write 0014 = 0000
+dsp dmem write 0015 = 0000
+dsp dmem write 0016 = 0000
+dsp dmem write 0017 = 0000
+dsp dmem write 0018 = 0000
+dsp dmem write 0019 = 0000
+dsp dmem write 001a = 0000
+dsp dmem write 001b = 0000
+dsp dmem write 001c = 0000
+dsp dmem write 001d = 0000
+dsp dmem write 001e = 0000
+dsp dmem write 001f = 0000
+dsp dmem write 0020 = 0000
+dsp dmem write 0021 = 0000
+dsp dmem write 0022 = 0000
+dsp dmem write 0023 = 0000
+dsp dmem write 0024 = 0000
+dsp dmem write 0025 = 0000
+dsp dmem write 0026 = 0000
+dsp dmem write 0027 = 0000
+dsp dmem write 0028 = 0000
+dsp dmem write 0029 = 0000
+dsp dmem write 002a = 0000
+dsp dmem write 002b = 0000
+dsp dmem write 002c = 0000
+dsp dmem write 002d = 0000
+dsp dmem write 002e = 0000
+dsp dmem write 002f = 0000
+Coefficient Read @ 1456 = 102f
+dsp dmem read 1456 = 102f
+Coefficient Read @ 15f6 = 7f65
+dsp dmem read 15f6 = 7f65
+Coefficient Read @ 1766 = 0273
+dsp dmem read 1766 = 0273
+call at 00a5 -> 88e5
+STARTED 00a4 -> 88e5
+== Registers ==
+AR0: 0000 AR1: 0030 AR2: 001f AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 0073 AX0.L: 9b60 AX1.H: 0000 AX1.L: 1000
+AC0.H: 007f AC0.M: 6500 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0073 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3860
+dsp dmem read 001f = 0000
+dsp dmem read 0020 = 0000
+dsp dmem write 001f = 6573
+dsp dmem write 0020 = 0000
+STOPPED: 00a6
+== Registers ==
+AR0: 0000 AR1: 002f AR2: 0020 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 0073 AX0.L: 9b60 AX1.H: 0000 AX1.L: 1000
+AC0.H: 007f AC0.M: 6573 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3850
+dsp dmem read 0000 = c3cf
+call at 00ad -> 8809
+STARTED 00ac -> 8809
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0020 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 00c3 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00c3 AC0.L: cf00
+AC1.H: 0000 AC1.M: cf00 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3860
+dsp dmem write 0020 = 0000
+dsp dmem write 0020 = cfc3
+STOPPED: 00ae
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0021 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 00c3 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00c3 AC0.L: cf00
+AC1.H: 0000 AC1.M: cfc3 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3878
+call at 00af -> 8723
+STARTED 00ae -> 8723
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0021 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 00c3 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00c3 AC0.L: cf00
+AC1.H: 0000 AC1.M: cfc3 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3878
+dsp dmem write 0021 = aab0
+STOPPED: 00b0
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0020 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 00c3 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00c3 AC0.L: cf00
+AC1.H: 0000 AC1.M: aab0 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3858
+Coefficient Read @ 166c = 06f2
+dsp dmem read 166c = 06f2
+Coefficient Read @ 1231 = 64fc
+dsp dmem read 1231 = 64fc
+call at 00be -> 88e5
+STARTED 00bd -> 88e5
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 001e AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 0064 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 6f00 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0064 AC1.L: fc00
+PROD: 001000fffff00000
+SR: 3860
+dsp dmem read 001e = 0000
+dsp dmem read 001f = 6573
+dsp dmem write 001e = 6f64
+dsp dmem write 001f = 6573
+STOPPED: 00bf
+== Registers ==
+AR0: 0001 AR1: 002e AR2: 001f AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 0064 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 6f64 AC0.L: 6573
+AC1.H: 0000 AC1.M: 0000 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3840
+dsp dmem read 0001 = a4b2
+call at 00c6 -> 8809
+STARTED 00c5 -> 8809
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 001f AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 00a4 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00a4 AC0.L: b200
+AC1.H: 0000 AC1.M: b200 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3860
+dsp dmem write 001f = 6573
+dsp dmem write 001f = b2a4
+STOPPED: 00c7
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0020 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 00a4 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00a4 AC0.L: b200
+AC1.H: 0000 AC1.M: b2a4 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3858
+call at 00c8 -> 8723
+STARTED 00c7 -> 8723
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0020 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 00a4 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00a4 AC0.L: b200
+AC1.H: 0000 AC1.M: b2a4 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3858
+dsp dmem write 0020 = ddc0
+STOPPED: 00c9
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 001f AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0000 IX3: 0000
+AX0.H: 00a4 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00a4 AC0.L: b200
+AC1.H: 0000 AC1.M: ddc0 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3878
+dsp dmem read 0005 = 0002
+Coefficient Read @ 1285 = 5aff
+dsp dmem read 1285 = 5aff
+dsp dmem read 0003 = 0006
+call at 0101 -> 8809
+STARTED 0100 -> 8809
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0010 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0001 IX3: 0000
+AX0.H: 0060 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0060 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0002 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3878
+dsp dmem write 0010 = 0000
+dsp dmem write 0011 = 0062
+STOPPED: 0102
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0012 AR3: 0618
+IX0: 8049 IX1: 85d0 IX2: 0001 IX3: 0000
+AX0.H: 0060 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0060 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0062 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3860
+dsp dmem write 0013 = 0060
+dsp dmem write 0014 = 0000
+dsp dmem read 0007 = 829c
+Coefficient Read @ 11b8 = 007f
+dsp dmem read 11b8 = 007f
+call at 0110 -> 81f4
+STARTED 010f -> 81f4
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0012 AR3: 0013
+IX0: 8049 IX1: 85d0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0070 AC0.L: 0000
+AC1.H: 0000 AC1.M: 829c AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3870
+dsp dmem write 0013 = 0000
+dsp dmem write 0014 = 829c
+STOPPED: 0111
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0015
+IX0: 8049 IX1: 85d0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0070 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 829c
+PROD: 0000000000070000
+SR: 3864
+call at 0113 -> 8458
+STARTED 0112 -> 8458
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0015
+IX0: 8049 IX1: 85d0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0070 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 829c AC1.L: 0000
+PROD: 0000000000070000
+SR: 3850
+dsp dmem write 0015 = 0000
+dsp dmem write 0016 = 82a3
+STOPPED: 0114
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0017
+IX0: 8049 IX1: 85d0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 82a3
+PROD: 0000000000070000
+SR: 3864
+dsp dmem read 0006 = 0000
+Coefficient Read @ 165b = 0000
+dsp dmem read 165b = 0000
+call at 011c -> 88e5
+STARTED 011b -> 88e5
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0015 AR3: 0017
+IX0: 8049 IX1: 85d0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 82a3
+PROD: 0000000000070000
+SR: 7864
+dsp dmem read 0015 = 0000
+dsp dmem read 0016 = 82a3
+dsp dmem write 0015 = 0000
+dsp dmem write 0016 = 82a3
+STOPPED: 011d
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0016 AR3: 0017
+IX0: 8049 IX1: 85d0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 82a3
+AC1.H: 0000 AC1.M: 0000 AC1.L: 82a3
+PROD: 0000000000070000
+SR: 7860
+dsp dmem write 0016 = 0000
+dsp dmem write 0017 = 82a0
+Coefficient Read @ 1723 = ffe0
+dsp dmem read 1723 = ffe0
+Coefficient Read @ 166b = 0000
+dsp dmem read 166b = 0000
+call at 0129 -> 88e5
+STARTED 0128 -> 88e5
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0016 AR3: 0017
+IX0: 8049 IX1: 85d0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: ffff AC0.M: ffff AC0.L: fe00
+AC1.H: 0000 AC1.M: 0000 AC1.L: 82a3
+PROD: 0000000000070000
+SR: 7868
+dsp dmem read 0016 = 0000
+dsp dmem read 0017 = 82a0
+dsp dmem write 0016 = 0000
+dsp dmem write 0017 = 80a0
+STOPPED: 012a
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8049 IX1: 85d0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 80a0
+AC1.H: 0000 AC1.M: 0000 AC1.L: 82a0
+PROD: 0000000000070000
+SR: 7861
+Coefficient Read @ 1491 = 6a0f
+dsp dmem read 1491 = 6a0f
+Coefficient Read @ 1468 = f808
+dsp dmem read 1468 = f808
+Coefficient Read @ 11fc = 0003
+dsp dmem read 11fc = 0003
+Coefficient Read @ 11b8 = 007f
+dsp dmem read 11b8 = 007f
+dsp dmem read 0012 = 0000
+dsp dmem write 0012 = 2014
+dsp dmem read 0011 = 0062
+dsp dmem write 0011 = 0062
+dsp dmem read 0011 = 0062
+dsp dmem read 0012 = 2014
+dsp dmem read 0012 = 2014
+dsp dmem read 0011 = 0062
+dsp dmem read 0012 = 2014
+Coefficient Read @ 15f1 = 0200
+dsp dmem read 15f1 = 0200
+Coefficient Read @ 10ca = 3461
+dsp dmem read 10ca = 3461
+Coefficient Read @ 1043 = 0076
+dsp dmem read 1043 = 0076
+dsp dmem write 0022 = f795
+Coefficient Read @ 1259 = 6143
+dsp dmem read 1259 = 6143
+Coefficient Read @ 16fe = 0008
+dsp dmem read 16fe = 0008
+dsp dmem write 0023 = c1df
+dsp dmem read 0008 = 804b
+dsp dmem read 0009 = 9b80
+call at 01b2 -> 808b
+STARTED 01b1 -> 808b
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8049 IX1: a094 IX2: 3f80 IX3: 0000
+AX0.H: 804b AX0.L: 9b80 AX1.H: 0020 AX1.L: 0008
+AC0.H: 590c AC0.M: c1df AC0.L: 0000
+AC1.H: 0034 AC1.M: a094 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3878
+dsp dmem write ffce = 804b
+dsp dmem write ffcf = 9b80
+dsp dmem write ffc9 = 0001
+dsp dmem write ffcd = 0020
+dsp dmem write ffcb = 0008
+dsp dmem read ffc9 = 0001
+STOPPED: 01b3
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 8049 IX1: a094 IX2: 3f80 IX3: 0000
+AX0.H: 804b AX0.L: 9b80 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0034 AC1.M: a094 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3864
+
+// skip more boring stuff
+
+// back to original ucode
+// runs two DMAs!
+STARTED 80b5 -> 80b5
+== Registers ==
+AR0: 0010 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 0049 IX1: 36a0 IX2: 0000 IX3: 1d20
+AX0.H: 004b AX0.L: 2a00 AX1.H: 0000 AX1.L: 2000
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: a094 AC1.L: 0008
+PROD: 0000000000070000
+SR: 2060
+80be : dsp dmem write ffce = 004b
+80c0 : dsp dmem write ffcf = 2a00
+80c4 : dsp dmem write ffc9 = 0000
+80c6 : dsp dmem write ffcd = 0000
+80c8 : dsp dmem write ffcb = 2000
+DMA pc: 80c8, Control: 0004, Address: 004b2a00, DSP Address: 0000, Size: 2000
+*** ddma_in RAM (0x004b2a00) -> DRAM_DSP (0x0000) : size (0x00002000)
+80ca : dsp dmem read ffc9 = 0000
+80d5 : dsp dmem write ffce = 0049
+80d7 : dsp dmem write ffcf = 36a0
+80db : dsp dmem write ffc9 = 0002
+80dd : dsp dmem write ffcd = 0000
+80df : dsp dmem write ffcb = 1d20
+DMA pc: 80df, Control: 0006, Address: 004936a0, DSP Address: 0000, Size: 1d20
+23:17:191 Core/HW/DSPLLE/DSPHost.cpp:70 N[DSPLLE]: g_dsp.iram_crc: 2fcdf1ec
+23:17:213 Core/DSP/DSPHWInterface.cpp:264 N[DSPLLE]: *** Copy new UCode from 0x004936a0 to 0x0000 (crc: 2fcdf1ec)
+80e1 : dsp dmem read ffc9 = 0002
+STOPPED: 80e5 -> 0010
+== Registers ==
+AR0: 0010 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 0049 IX1: 36a0 IX2: 0000 IX3: 1d20
+AX0.H: 004b AX0.L: 2a00 AX1.H: 0000 AX1.L: 2000
+AC0.H: 0000 AC0.M: 0002 AC0.L: 0000
+AC1.H: 0000 AC1.M: 1d20 AC1.L: 0000
+PROD: 0000000000070000
+SR: 2060
diff --git a/docs/DSP/free_dsp_rom/GBA-MetroidPrime-log.txt b/docs/DSP/free_dsp_rom/GBA-MetroidPrime-log.txt
new file mode 100644
index 0000000000..b3420c8bb2
--- /dev/null
+++ b/docs/DSP/free_dsp_rom/GBA-MetroidPrime-log.txt
@@ -0,0 +1,1264 @@
+dsp dmem write 0010 = 0000
+dsp dmem write 0011 = 0000
+dsp dmem write 0012 = 0000
+dsp dmem write 0013 = 0000
+dsp dmem write 0014 = 0000
+dsp dmem write 0015 = 0000
+dsp dmem write 0016 = 0000
+dsp dmem write 0017 = 0000
+dsp dmem write 0018 = 0000
+dsp dmem write 0019 = 0000
+dsp dmem write 001a = 0000
+dsp dmem write 001b = 0000
+dsp dmem write 001c = 0000
+dsp dmem write 001d = 0000
+dsp dmem write 001e = 0000
+dsp dmem write 001f = 0000
+dsp dmem write 0020 = 0000
+dsp dmem write 0021 = 0000
+dsp dmem write 0022 = 0000
+dsp dmem write 0023 = 0000
+dsp dmem write 0024 = 0000
+dsp dmem write 0025 = 0000
+dsp dmem write 0026 = 0000
+dsp dmem write 0027 = 0000
+dsp dmem write 0028 = 0000
+dsp dmem write 0029 = 0000
+dsp dmem write 002a = 0000
+dsp dmem write 002b = 0000
+dsp dmem write 002c = 0000
+dsp dmem write 002d = 0000
+dsp dmem write 002e = 0000
+dsp dmem write 002f = 0000
+0093 : Coefficient Read @ 1456
+dsp dmem read 1456 = 102f
+009e : Coefficient Read @ 15f6
+dsp dmem read 15f6 = 7f65
+00a1 : Coefficient Read @ 1766
+dsp dmem read 1766 = 0273
+call at 00a5 -> 88e5
+STARTED 00a4 -> 88e5
+== Registers ==
+AR0: 0000 AR1: 0030 AR2: 001f AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 0073 AX0.L: a0e0 AX1.H: 0000 AX1.L: 1000
+AC0.H: 007f AC0.M: 6500 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0073 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem read 001f = 0000
+dsp dmem read 0020 = 0000
+dsp dmem write 001f = 6573
+dsp dmem write 0020 = 0000
+STOPPED: 00a6
+== Registers ==
+AR0: 0000 AR1: 002f AR2: 0020 AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 0073 AX0.L: a0e0 AX1.H: 0000 AX1.L: 1000
+AC0.H: 007f AC0.M: 6573 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3950
+dsp dmem read 0000 = dec5
+call at 00ad -> 8809
+STARTED 00ac -> 8809
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0020 AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 00de AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00de AC0.L: c500
+AC1.H: 0000 AC1.M: c500 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem write 0020 = 0000
+dsp dmem write 0020 = c5de
+STOPPED: 00ae
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0021 AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 00de AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00de AC0.L: c500
+AC1.H: 0000 AC1.M: c5de AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3978
+call at 00af -> 8723
+STARTED 00ae -> 8723
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0021 AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 00de AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00de AC0.L: c500
+AC1.H: 0000 AC1.M: c5de AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3978
+dsp dmem write 0021 = a0ad
+STOPPED: 00b0
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 0020 AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 00de AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 00de AC0.L: c500
+AC1.H: 0000 AC1.M: a0ad AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3958
+00b4 : Coefficient Read @ 166c
+dsp dmem read 166c = 06f2
+00b9 : Coefficient Read @ 1231
+dsp dmem read 1231 = 64fc
+call at 00be -> 88e5
+STARTED 00bd -> 88e5
+== Registers ==
+AR0: 0001 AR1: 002f AR2: 001e AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 0064 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 6f00 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0064 AC1.L: fc00
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem read 001e = 0000
+dsp dmem read 001f = 6573
+dsp dmem write 001e = 6f64
+dsp dmem write 001f = 6573
+STOPPED: 00bf
+== Registers ==
+AR0: 0001 AR1: 002e AR2: 001f AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 0064 AX0.L: 0000 AX1.H: 6573 AX1.L: 1000
+AC0.H: 0000 AC0.M: 6f64 AC0.L: 6573
+AC1.H: 0000 AC1.M: 0000 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3940
+dsp dmem read 0001 = 628b
+call at 00c6 -> 8809
+STARTED 00c5 -> 8809
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 001f AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 0062 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0062 AC0.L: 8b00
+AC1.H: 0000 AC1.M: 8b00 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem write 001f = 6573
+dsp dmem write 001f = 8b62
+STOPPED: 00c7
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0020 AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 0062 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0062 AC0.L: 8b00
+AC1.H: 0000 AC1.M: 8b62 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3958
+call at 00c8 -> 8723
+STARTED 00c7 -> 8723
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0020 AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 0062 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0062 AC0.L: 8b00
+AC1.H: 0000 AC1.M: 8b62 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3958
+dsp dmem write 0020 = e406
+STOPPED: 00c9
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 001f AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0000 IX3: 0000
+AX0.H: 0062 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0062 AC0.L: 8b00
+AC1.H: 0000 AC1.M: e406 AC1.L: 6573
+PROD: 001000fffff00000
+SR: 3978
+dsp dmem read 0005 = 0002
+00f9 : Coefficient Read @ 1285
+dsp dmem read 1285 = 5aff
+dsp dmem read 0003 = 0002
+call at 0101 -> 8809
+STARTED 0100 -> 8809
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0010 AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0001 IX3: 0000
+AX0.H: 0020 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0020 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0002 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3978
+dsp dmem write 0010 = 0000
+dsp dmem write 0011 = 0022
+STOPPED: 0102
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0012 AR3: 0ca2
+IX0: 803f IX1: 71a0 IX2: 0001 IX3: 0000
+AX0.H: 0020 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0020 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0022 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3960
+dsp dmem write 0013 = 0020
+dsp dmem write 0014 = 0000
+dsp dmem read 0007 = c628
+010c : Coefficient Read @ 11b8
+dsp dmem read 11b8 = 007f
+call at 0110 -> 81f4
+STARTED 010f -> 81f4
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0012 AR3: 0013
+IX0: 803f IX1: 71a0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 6f64 AX1.L: 1000
+AC0.H: fff0 AC0.M: 0070 AC0.L: 0000
+AC1.H: 0000 AC1.M: c628 AC1.L: 0000
+PROD: 001000fffff00000
+SR: 3970
+dsp dmem write 0013 = 0000
+dsp dmem write 0014 = c628
+STOPPED: 0111
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0015
+IX0: 803f IX1: 71a0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0070 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: c628
+PROD: 0000000000070000
+SR: 3964
+call at 0113 -> 8458
+STARTED 0112 -> 8458
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0015
+IX0: 803f IX1: 71a0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0070 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: c628 AC1.L: 0000
+PROD: 0000000000070000
+SR: 3970
+dsp dmem write 0015 = 0000
+dsp dmem write 0016 = c62f
+STOPPED: 0114
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0012 AR3: 0017
+IX0: 803f IX1: 71a0 IX2: 0001 IX3: 0000
+AX0.H: 0070 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: c62f
+PROD: 0000000000070000
+SR: 3964
+dsp dmem read 0006 = 0000
+011b : Coefficient Read @ 165b
+dsp dmem read 165b = 0000
+call at 011c -> 88e5
+STARTED 011b -> 88e5
+== Registers ==
+AR0: 0002 AR1: 002f AR2: 0015 AR3: 0017
+IX0: 803f IX1: 71a0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0000 AC1.M: 0000 AC1.L: c62f
+PROD: 0000000000070000
+SR: 7964
+dsp dmem read 0015 = 0000
+dsp dmem read 0016 = c62f
+dsp dmem write 0015 = 0000
+dsp dmem write 0016 = c62f
+STOPPED: 011d
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0016 AR3: 0017
+IX0: 803f IX1: 71a0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: c62f
+AC1.H: 0000 AC1.M: 0000 AC1.L: c62f
+PROD: 0000000000070000
+SR: 7960
+dsp dmem write 0016 = 0000
+dsp dmem write 0017 = c628
+0125 : Coefficient Read @ 1723
+dsp dmem read 1723 = ffe0
+0128 : Coefficient Read @ 166b
+dsp dmem read 166b = 0000
+call at 0129 -> 88e5
+STARTED 0128 -> 88e5
+== Registers ==
+AR0: 0002 AR1: 002e AR2: 0016 AR3: 0017
+IX0: 803f IX1: 71a0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: ffff AC0.M: ffff AC0.L: fe00
+AC1.H: 0000 AC1.M: 0000 AC1.L: c62f
+PROD: 0000000000070000
+SR: 7968
+dsp dmem read 0016 = 0000
+dsp dmem read 0017 = c628
+dsp dmem write 0016 = 0000
+dsp dmem write 0017 = c428
+STOPPED: 012a
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: 71a0 IX2: 0001 IX3: 0000
+AX0.H: 0000 AX0.L: 6573 AX1.H: 0000 AX1.L: 1000
+AC0.H: 0000 AC0.M: 0000 AC0.L: c428
+AC1.H: 0000 AC1.M: 0000 AC1.L: c628
+PROD: 0000000000070000
+SR: 7961
+0132 : Coefficient Read @ 1491
+dsp dmem read 1491 = 6a0f
+0137 : Coefficient Read @ 1468
+dsp dmem read 1468 = f808
+0139 : Coefficient Read @ 11fc
+dsp dmem read 11fc = 0003
+013d : Coefficient Read @ 11b8
+dsp dmem read 11b8 = 007f
+dsp dmem read 0012 = 0000
+dsp dmem write 0012 = 3105
+dsp dmem read 0011 = 0022
+dsp dmem write 0011 = 0022
+dsp dmem read 0011 = 0022
+dsp dmem read 0012 = 3105
+dsp dmem read 0012 = 3105
+dsp dmem read 0011 = 0022
+dsp dmem read 0012 = 3105
+017a : Coefficient Read @ 15f1
+dsp dmem read 15f1 = 0200
+0194 : Coefficient Read @ 10ca
+dsp dmem read 10ca = 3461
+0198 : Coefficient Read @ 1043
+dsp dmem read 1043 = 0076
+dsp dmem write 0022 = b9d5
+019f : Coefficient Read @ 1259
+dsp dmem read 1259 = 6143
+01a1 : Coefficient Read @ 16fe
+dsp dmem read 16fe = 0008
+dsp dmem write 0023 = d0ce
+dsp dmem read 0008 = 8056
+dsp dmem read 0009 = a100
+call at 01b2 -> 808b
+STARTED 01b1 -> 808b
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 1b4c AC0.M: d0ce AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3978
+dsp dmem write ffce = 8056
+dsp dmem write ffcf = a100
+dsp dmem write ffc9 = 0001
+dsp dmem write ffcd = 0020
+dsp dmem write ffcb = 0008
+dsp dmem read ffc9 = 0001
+STOPPED: 01b3
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3964
+call at 0044 -> 807e
+STARTED 0043 -> 807e
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 0000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3964
+dsp dmem read fffc = 5cd1
+STOPPED: 0045
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 5cd1 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3964
+dsp dmem write fffc = dcd1
+dsp dmem write fffd = 0003
+dsp dmem write fffb = 0001
+call at 004d -> 8078
+STARTED 004c -> 8078
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 5cd1 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 7964
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
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+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
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+dsp dmem read fffe = 0056
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+dsp dmem read fffe = 0056
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+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
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+dsp dmem read fffe = 0056
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+dsp dmem read fffe = 0056
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+dsp dmem read fffe = 0056
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+dsp dmem read fffe = 0056
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+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = cdd1
+STOPPED: 004e
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: ffff AC0.M: cdd1 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 7964
+dsp dmem read ffff = 0001
+call at 0060 -> 8078
+STARTED 005f -> 8078
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 0001 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3965
+dsp dmem read fffe = 4dd1
+dsp dmem read fffe = 8000
+STOPPED: 0061
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3965
+dsp dmem read ffff = 0000
+call at 0063 -> 8078
+STARTED 0062 -> 8078
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3965
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 8000
+STOPPED: 0064
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3965
+dsp dmem read ffff = 0000
+call at 0066 -> 8078
+STARTED 0065 -> 8078
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3965
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 8000
+STOPPED: 0067
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3965
+dsp dmem read ffff = 0000
+call at 0069 -> 8078
+STARTED 0068 -> 8078
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3965
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 803f
+STOPPED: 006a
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 803f IX1: b185 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 803f AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3965
+dsp dmem read ffff = 4a80
+call at 0070 -> 8078
+STARTED 006f -> 8078
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 003f AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read fffe = 003f
+dsp dmem read fffe = 003f
+dsp dmem read fffe = 8000
+STOPPED: 0071
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 3f80 IX3: 0000
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read ffff = 19e0
+call at 0074 -> 8078
+STARTED 0073 -> 8078
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 3f80 IX3: 19e0
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 8000
+STOPPED: 0075
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 3f80 IX3: 19e0
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read ffff = 0000
+call at 0078 -> 8078
+STARTED 0077 -> 8078
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 0000 IX3: 19e0
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 8000
+STOPPED: 0079
+== Registers ==
+AR0: 0002 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 0000 IX3: 19e0
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read ffff = 0030
+call at 007c -> 8078
+STARTED 007b -> 8078
+== Registers ==
+AR0: 0030 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 0000 IX3: 19e0
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 8056
+STOPPED: 007d
+== Registers ==
+AR0: 0030 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 0000 IX3: 19e0
+AX0.H: 8056 AX0.L: a100 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8056 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read ffff = 7900
+call at 0082 -> 8078
+STARTED 0081 -> 8078
+== Registers ==
+AR0: 0030 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 0000 IX3: 19e0
+AX0.H: 0056 AX0.L: 7900 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 0056 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 0056
+dsp dmem read fffe = 8000
+STOPPED: 0083
+== Registers ==
+AR0: 0030 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 0000 IX3: 19e0
+AX0.H: 0056 AX0.L: 7900 AX1.H: 0020 AX1.L: 0008
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read ffff = 2000
+call at 0085 -> 8078
+STARTED 0084 -> 8078
+== Registers ==
+AR0: 0030 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 0000 IX3: 19e0
+AX0.H: 0056 AX0.L: 7900 AX1.H: 0020 AX1.L: 2000
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 0000
+dsp dmem read fffe = 8000
+STOPPED: 0086
+== Registers ==
+AR0: 0030 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 0000 IX3: 19e0
+AX0.H: 0056 AX0.L: 7900 AX1.H: 0020 AX1.L: 2000
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 3960
+dsp dmem read ffff = 0000
+STARTED 0089 -> 80b5
+== Registers ==
+AR0: 0030 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 0000 IX3: 19e0
+AX0.H: 0056 AX0.L: 7900 AX1.H: 0000 AX1.L: 2000
+AC0.H: 0000 AC0.M: 8000 AC0.L: 0000
+AC1.H: 0034 AC1.M: b185 AC1.L: 0008
+PROD: 0000000000070000
+SR: 2160
+dsp dmem write ffce = 0056
+dsp dmem write ffcf = 7900
+dsp dmem write ffc9 = 0000
+dsp dmem write ffcd = 0000
+dsp dmem write ffcb = 2000
+dsp dmem read ffc9 = 0000
+dsp dmem write ffce = 003f
+dsp dmem write ffcf = 4a80
+dsp dmem write ffc9 = 0002
+dsp dmem write ffcd = 0000
+dsp dmem write ffcb = 19e0
+Core/HW/DSPLLE/DSPHost.cpp:70 N[DSPLLE]: g_dsp.iram_crc: 4e8a8b21
+Core/HW/DSPLLE/DSPSymbols.cpp:84 E[DSPLLE]: Bah! ReadAnnotatedAssembly couldn't find the file ../../docs/DSP/DSP_UC_AX_4E8A8B21.txt
+Core/DSP/DSPHWInterface.cpp:247 N[DSPLLE]: *** Copy new UCode from 0x003f4a80 to 0x0000 (crc: 4e8a8b21)
+STOPPED: 0030
+== Registers ==
+AR0: 0030 AR1: 002d AR2: 0017 AR3: 0017
+IX0: 003f IX1: 4a80 IX2: 0000 IX3: 19e0
+AX0.H: 0056 AX0.L: 7900 AX1.H: 0000 AX1.L: 2000
+AC0.H: 0000 AC0.M: 0002 AC0.L: 0000
+AC1.H: 0000 AC1.M: 19e0 AC1.L: 0000
+PROD: 0000000000070000
+SR: 2160
generated by cgit v1.2.3 (git 2.25.1) at 2026-09-22 19:05:14 +0000