diff options
| author | Pokechu22 <Pokechu022@gmail.com> | 2021-08-14 17:36:55 -0700 |
|---|---|---|
| committer | Pokechu22 <Pokechu022@gmail.com> | 2021-08-21 17:07:14 -0700 |
| commit | 408623b6e92c0e3e00fb4ddb3bd18b3fe00b2e2d (patch) | |
| tree | 2ef7f006876c4da2d500d3d79f931737fa02f621 /docs | |
| parent | 8fa649e1d64baacc5dc0b474e6fc914c7e348fe9 (diff) | |
docs/DSP: Document behavior of LRS/SRS/SI with CR
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex b/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex index 6980489b8c..615a834bc0 100644 --- a/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex +++ b/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex @@ -534,7 +534,7 @@ If the value is not zero, then the PC is modified by the value from call stack \ \section{Config register} -Its purpose is unknown at this time. It is written with \Value{0x00FF} and \Value{0x0004} values. +Serves as a base offset for \Opcode{SRS} and \Opcode{LRS}. Zelda uCode writes it with \Value{0x0004}, but otherwise it is usually \Value{0x00FF}. This is an 8-bit register. Writes to the upper 8 bits are ignored and those bits always read back as 0. @@ -2558,12 +2558,12 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th \end{DSPOpcodeFormat} \begin{DSPOpcodeDescription} - \item Move value from data memory pointed by address \Address{M} (8-bit sign-extended) to register \Register{\$(0x18+D)}. + \item Move value from data memory pointed by address \Address{(\$cr << 8) | M} to register \Register{\$(0x18+D)}. Perform an additional operation depending on destination register. \end{DSPOpcodeDescription} \begin{DSPOpcodeOperation} - $(0x18+D) = MEM[M] + $(0x18+D) = MEM[($cr << 8) | M] $pc++ \end{DSPOpcodeOperation} @@ -3843,14 +3843,18 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th \end{DSPOpcodeFormat} \begin{DSPOpcodeDescription} - \item Store 16-bit immediate value \Value{I} to a memory location pointed by address \Address{M} (\Address{M} is an 8-bit sign-extended value). + \item Store 16-bit immediate value \Value{I} to a memory location pointed by address \Address{0xFF00 | M}. \end{DSPOpcodeDescription} \begin{DSPOpcodeOperation} - MEM[M] = I + MEM[0xFF00 | M] = I $pc += 2 \end{DSPOpcodeOperation} + \begin{DSPOpcodeNote} + \item Unlike \Opcode{LRS} and \Opcode{SRS}, \Opcode{SI} does not use \Register{\$cr} to decide the base address and instead always uses \Address{0xFF00}. + \end{DSPOpcodeNote} + \DSPOpcodeFlagsUnchanged \end{DSPOpcode} @@ -3979,12 +3983,12 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th \end{DSPOpcodeFormat} \begin{DSPOpcodeDescription} - \item Store value from register \Register{\$(0x18+S)} to a memory pointed by address \Address{M} (8-bit sign-extended). + \item Store value from register \Register{\$(0x18+S)} to a memory pointed by address \Address{(\$cr << 8) | M}. Perform an additional operation depending on destination register. \end{DSPOpcodeDescription} \begin{DSPOpcodeOperation} - MEM[M] = $(0x18+S) + MEM[($cr << 8) | M] = $(0x18+S) $pc++ \end{DSPOpcodeOperation} |
