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authorPokechu22 <Pokechu022@gmail.com>2021-08-13 11:44:52 -0700
committerPokechu22 <Pokechu022@gmail.com>2021-08-21 16:05:06 -0700
commit79664d419cbf98be1cd0585ac5912f295ca43926 (patch)
treed3a2b5ef5790fdb571712d109a298481e092d7cd /docs
parent1bcea561e9a020b2a3642923b6a38d7b7fccd94b (diff)
docs/DSP: Document rounding behavior of CLRL
Diffstat (limited to 'docs')
-rw-r--r--docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex12
1 files changed, 10 insertions, 2 deletions
diff --git a/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex b/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex
index 23f04f8324..74d3a30901 100644
--- a/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex
+++ b/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex
@@ -1736,14 +1736,22 @@ There are two pairs of conditions that work similarly: \texttt{EQ}/\texttt{NE} a
\end{DSPOpcodeFormat}
\begin{DSPOpcodeDescription}
- \item Clears \Register{\$acR.l} - low 16 bits of accumulator \Register{\$acR}.
+ \item Rounds \Register{\$acR} such that \Register{\$acR.l} is 0. This is a round-to-even operation.
\end{DSPOpcodeDescription}
\begin{DSPOpcodeOperation}
- $acR.l = 0
+ IF ($acR & 0x10000) != 0
+ $acR = ($acR + 0x8000) & ~0xffff
+ ELSE
+ $acR = ($acR + 0x7fff) & ~0xffff
+ ENDIF
FLAGS($acR)
$pc++
\end{DSPOpcodeOperation}
+
+ \begin{DSPOpcodeNote}
+ \item An alternative interpretation is that if \Register{\$acR.m} is odd, then increment \Register{\$acsR} if \Register{\$acR.l} is greater than or equal to \Value{0x8000}; if \Register{\$acR.m} is even, then increment \Register{\$acsR} if \Register{\$acR.l} is greater than or equal to \Value{0x7fff}. Afterwards set \Register{\$acR.l} to 0.
+ \end{DSPOpcodeNote}
\end{DSPOpcode}
\begin{DSPOpcode}{CLRP}