diff options
| -rw-r--r-- | Source/Core/Common/Arm64Emitter.cpp | 2 | ||||
| -rw-r--r-- | Source/Core/Common/Arm64Emitter.h | 4 |
2 files changed, 4 insertions, 2 deletions
diff --git a/Source/Core/Common/Arm64Emitter.cpp b/Source/Core/Common/Arm64Emitter.cpp index a9b810650b..3546638519 100644 --- a/Source/Core/Common/Arm64Emitter.cpp +++ b/Source/Core/Common/Arm64Emitter.cpp @@ -377,7 +377,7 @@ void ARM64XEmitter::EncodeLoadStoreExcInst(u32 instenc, void ARM64XEmitter::EncodeLoadStorePairedInst(u32 op, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, u32 imm) { bool b64Bit = Is64Bit(Rt); - bool b128Bit = Is128Bit(Rt); + bool b128Bit = IsQuad(Rt); bool bVec = IsVector(Rt); if (b128Bit) diff --git a/Source/Core/Common/Arm64Emitter.h b/Source/Core/Common/Arm64Emitter.h index cb3c60119e..0933d2c1b3 100644 --- a/Source/Core/Common/Arm64Emitter.h +++ b/Source/Core/Common/Arm64Emitter.h @@ -76,7 +76,9 @@ enum ARM64Reg }; inline bool Is64Bit(ARM64Reg reg) { return reg & 0x20; } -inline bool Is128Bit(ARM64Reg reg) { return reg & 0xC0; } +inline bool IsSingle(ARM64Reg reg) { return reg & 0x40; } +inline bool IsDouble(ARM64Reg reg) { return reg & 0x80; } +inline bool IsQuad(ARM64Reg reg) { return (reg & 0xC0) == 0xC0; } inline bool IsVector(ARM64Reg reg) { return (reg & 0xC0) != 0; } inline ARM64Reg DecodeReg(ARM64Reg reg) { return (ARM64Reg)(reg & 0x1F); } inline ARM64Reg EncodeRegTo64(ARM64Reg reg) { return (ARM64Reg)(reg | 0x20); } |