4 files changed, 37 insertions, 15 deletions

diff --git a/Source/Core/Core/Src/HW/BBA-TAP/TAP_Unix.cpp b/Source/Core/Core/Src/HW/BBA-TAP/TAP_Unix.cpp
index 6424702019..87a9cfa337 100644
--- a/Source/Core/Core/Src/HW/BBA-TAP/TAP_Unix.cpp
+++ b/Source/Core/Core/Src/HW/BBA-TAP/TAP_Unix.cpp
@@ -68,6 +68,22 @@ bool CEXIETHERNET::activate() {
 	return true;
 	
 }
+bool CEXIETHERNET::CheckRecieved()
+{
+	if(!isActivated())
+		return false;
+	char RBuffer[2048]; // Bigger than MTU, but w/e
+	int Size = recv(fd, RBuffer, 2048, MSG_PEEK);
+	if(Size == -1)
+	{
+		DEBUGPRINT("Recieve check failed with %d\n", errno);
+		return false;
+	}
+	if(Size != 0)
+		DEBUGPRINT("Have waiting Packet of size %d\n", Size);
+	return true;
+}
+
 bool CEXIETHERNET::startRecv() {
 	DEBUGPRINT("Start Receive!\n");
 	exit(0);
@@ -101,6 +117,8 @@ bool CEXIETHERNET::startRecv() {
 }
 bool CEXIETHERNET::sendPacket(u8 *etherpckt, int size) 
 {
+	if(!isActivated())
+		activate();
 	DEBUGPRINT( "Packet: 0x");
 	for(int a = 0; a < size; ++a)
 	{
@@ -110,22 +128,11 @@ bool CEXIETHERNET::sendPacket(u8 *etherpckt, int size)
 	int numBytesWrit = write(fd, etherpckt, size);
 	if(numBytesWrit != size)
 	{
-		DEBUGPRINT("BBA sendPacket %i only got %i bytes sent!\n", size, numBytesWrit);
+		DEBUGPRINT("BBA sendPacket %i only got %i bytes sent!errno: %d\n", size, numBytesWrit, errno);
 		return false;
 	}
 	else
 		DEBUGPRINT("Sent out the correct number of bytes: %d\n", size);
-	//fwrite(etherpckt, size, size, raw_socket);
-	/*DWORD numBytesWrit;
-	OVERLAPPED overlap;
-	ZERO_OBJECT(overlap);
-	//overlap.hEvent = mHRecvEvent;
-	TGLE(WriteFile(mHAdapter, etherpckt, size, &numBytesWrit, &overlap));
-	if(numBytesWrit != size) 
-	{
-		DEGUB("BBA sendPacket %i only got %i bytes sent!\n", size, numBytesWrit);
-		FAIL(UE_BBA_ERROR);
-	}*/
 	recordSendComplete();
 	//exit(0);
 	return true;
diff --git a/Source/Core/Core/Src/HW/EXI_DeviceEthernet.cpp b/Source/Core/Core/Src/HW/EXI_DeviceEthernet.cpp
index 5672603a17..96042abc90 100644
--- a/Source/Core/Core/Src/HW/EXI_DeviceEthernet.cpp
+++ b/Source/Core/Core/Src/HW/EXI_DeviceEthernet.cpp
@@ -80,6 +80,7 @@ CEXIETHERNET::CEXIETHERNET() :
 
 void CEXIETHERNET::SetCS(int cs)
 {
+	DEBUGPRINT("Set CS: %s\n", cs ? "true" : "false");
 	if (!cs)
 	{
 		if (mExpectVariableLengthImmWrite)
@@ -89,8 +90,7 @@ void CEXIETHERNET::SetCS(int cs)
 		}
 		mExpectSpecialImmRead = false;
 		mWriteP = mReadP = INVALID_P;
-		m_uPosition = 0;
-		Expecting = EXPECT_NONE;
+		m_bInterruptSet = false;
 	}
 }
 
@@ -105,6 +105,9 @@ void CEXIETHERNET::Update()
 }
 bool CEXIETHERNET::IsInterruptSet()
 {
+	//bool Temp = m_bInterruptSet;
+	//m_bInterruptSet = false;
+	//return Temp;
 	return m_bInterruptSet;
 }
 
@@ -367,11 +370,22 @@ u32 CEXIETHERNET::ImmRead(u32 _uSize)
 			exit(0);
 		}
 		u32 uResult = 0;
+		switch(mReadP)
+		{
+			case BBA_NWAYS: // Bit of a hack
+				mBbaMem[BBA_NWAYS] = (BBA_NWAYS_LS10 | BBA_NWAYS_LPNWAY | BBA_NWAYS_ANCLPT | BBA_NWAYS_10TXF);
+			break;
+			default:
+			break;
+		}
 		memcpy(&uResult, mBbaMem + mReadP, _uSize);
 		// TODO: We do as well?
 		uResult = Common::swap32(uResult); //Whinecube : we have a byteswap problem...
 		
 		//DEBUGPRINT("Mem spot is 0x%02x uResult is 0x%x\n", mBbaMem[mReadP], uResult);
+		#ifndef _WIN32
+		CheckRecieved();
+		#endif
 		DEBUGPRINT( "\t[INFO]Read from BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mReadP >= CB_OFFSET ? 4 : 2, mReadP, _uSize, (_uSize==1?"":"s"),_uSize*2, getbitsw(uResult, 0, _uSize * 8 - 1));
 		mReadP = mReadP + _uSize;
 		return uResult;
diff --git a/Source/Core/Core/Src/HW/EXI_DeviceEthernet.h b/Source/Core/Core/Src/HW/EXI_DeviceEthernet.h
index 9b7c853004..706a4095c8 100644
--- a/Source/Core/Core/Src/HW/EXI_DeviceEthernet.h
+++ b/Source/Core/Core/Src/HW/EXI_DeviceEthernet.h
@@ -139,6 +139,7 @@ private:
 	
 	//TAP interface
 	bool activate();
+	bool CheckRecieved();
 	bool deactivate();
 	bool isActivated();
 	bool resume();
diff --git a/Source/Core/Core/Src/PowerPC/Jit64/Jit_Branch.cpp b/Source/Core/Core/Src/PowerPC/Jit64/Jit_Branch.cpp
index 93e9557ceb..44b7e61923 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64/Jit_Branch.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64/Jit_Branch.cpp
@@ -63,7 +63,7 @@ using namespace Gen;
 		fpr.Flush(FLUSH_ALL);
 		//Bits SRR1[0, 5-9, 16-23, 25-27, 30-31] are placed into the corresponding bits of the MSR.
 		//MSR[13] is set to 0.
-		const u32 mask = 0x87C0FF73;
+		const u32 mask = 0x87C0FFFF;
 		// MSR = (MSR & ~mask) | (SRR1 & mask);
 		MOV(32, R(EAX), M(&MSR));
 		MOV(32, R(ECX), M(&SRR1));