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AgeCommit message (Expand)Author
2022-09-30docs/DSP: Trivial adjustment to BLOOP{,I} sub-operation orderVincent Pelletier
2022-06-01docs/DSP: Update version and historyPokechu22
2022-06-01docs/DSP: Explain 16-bit and 40-bit modesPokechu22
2022-06-01docs/DSP: Add notes highlighting the difference between 'LS and 'SLPokechu22
2022-05-31docs/DSP: Add missing dollar signs in shift instruction operation sectionsPokechu22
2022-05-29docs/DSP: Fix inconsistency with ADDI and CMPIPokechu22
2022-05-29docs/DSP: Fix typo with arithmetic instructions that take a 16-bit immediatePokechu22
2022-05-29docs/DSP: Document the behavior when main and extended opcodes both write to ...Pokechu22
2022-05-29docs/DSP: Fix typo in 'NOP commentPokechu22
2022-05-29docs/DSP: Clarify LRS notePokechu22
2022-05-27docs/DSP: Rename CMPAR to CMPAXHPokechu22
2022-05-21docs/DSP: Fix "ILLR" typo in Instruction Memory sectionPokechu22
2022-05-14Add tested bootloading transfer sizexperia64
2021-08-22dsp_rom: Add version numbers and hashes to VerifyRoms and readmePokechu22
2021-08-22dsp_rom: Remove illegal use of AX with SRSPokechu22
2021-08-22dsp_rom: add pseudo code and fix small accuracy issuesTillmann Karras
2021-08-22dsp_rom: Fix readme eols and trailing whitespacePokechu22
2021-08-21docs/DSP: Update version and historyPokechu22
2021-08-21docs/DSP: NEG can set overflow and carryPokechu22
2021-08-21docs/DSP: Fix typo with MULCMVZ and MULCMVPokechu22
2021-08-21docs/DSP: Document initialization processPokechu22
2021-08-21docs/DSP: A failed RETcc only inceases PC by 1, not 2Pokechu22
2021-08-21docs/DSP: Add RTIccPokechu22
2021-08-21docs/DSP: Change conditional names to match DolphinPokechu22
2021-08-21docs/DSP: Split SRSH from SRSPokechu22
2021-08-21docs/DSP: Document behavior of LRS/SRS/SI with CRPokechu22
2021-08-21docs/DSP: Document masking/sign extension behavior of registersPokechu22
2021-08-21docs/DSP: Fix registers used by MOVAX and MOVPokechu22
2021-08-21docs/DSP: MADDC operates on acS.m, not acS.lPokechu22
2021-08-21docs/DSP: Add information about flags for every instructionPokechu22
2021-08-21docs/DSP: Document overflow and carry behaviorPokechu22
2021-08-21docs/DSP: Fix MULXAC bytesPokechu22
2021-08-21docs/DSP: Fix 'S formatPokechu22
2021-08-21docs/DSP: Fix 'LS encodingPokechu22
2021-08-21docs/DSP: Fix acD/acR conflation in shift instructionsPokechu22
2021-08-21docs/DSP: Fix operation for LSR/ASRPokechu22
2021-08-21docs/DSP: Note that ADDAXL is unsignedPokechu22
2021-08-21docs/DSP: Fix operation of ADDR and SUBRPokechu22
2021-08-21docs/DSP: Adjust operation for CMPI and CMPISPokechu22
2021-08-21docs/DSP: Document rounding behavior of CLRLPokechu22
2021-08-21docs/DSP: Add 'NOPPokechu22
2021-08-21docs/DSP: Document 'LD and 'LDAXPokechu22
2021-08-21docs/DSP: Document behavior and instructions when the first nybble is 3Pokechu22
2021-08-21docs/DSP: Add most missing instructionsPokechu22
2021-08-21docs/DSP: Adjust bit names in opcode tablePokechu22
2021-08-21docs/DSP: Hyperlink opcode namesPokechu22
2021-08-21docs/DSP: Rename 'SLMN to 'SLNMPokechu22
2021-08-21docs/DSP: Document accelerator hardware registersPokechu22
2021-08-21docs/DSP: Adjust formatting of RegisterBitOverviewPokechu22
2021-08-21docs/DSP: Improve DMA hardware register informationPokechu22
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