most of shieldD revo sdk matching (#2951)

* shieldD revo wpad done

* shieldD revo hio2 done

* shieldD revo aralt, ppcarch, gf done

* shieldD revo exi done

* shieldD revo SI done

* shieldD revo vi done

* shieldD revo mtx done

* shieldD revo GX mostly done

* shieldD revo ai/dsp done

* shieldD revo sc mostly done

* shieldD revo esp/euart/wenc mostly done

* build fixes

27 files changed, 8032 insertions, 76 deletions

diff --git a/include/global.h b/include/global.h
index 63e3defa45..24d22c7522 100644
--- a/include/global.h
+++ b/include/global.h
@@ -70,6 +70,13 @@ extern int __rlwimi(int, int, int, int, int);
 extern void __dcbz(void*, int);
 extern void __sync();
 extern int __abs(int);
+#else
+// to stop clangd errors
+#define __cntlzw
+#define __rlwimi
+#define __dcbz
+#define __sync
+#define __abs
 #endif
 
 #ifndef __MWERKS__
diff --git a/include/revolution/ai.h b/include/revolution/ai.h
index 340da848b2..dd103eb0af 100644
--- a/include/revolution/ai.h
+++ b/include/revolution/ai.h
@@ -25,21 +25,8 @@ u32 AIGetDMABytesLeft(void);
 u32 AIGetDMAStartAddr(void);
 u32 AIGetDMALength(void);
 BOOL AICheckInit(void);
-AISCallback AIRegisterStreamCallback(AISCallback callback);
-u32 AIGetStreamSampleCount(void);
-void AIResetStreamSampleCount(void);
-void AISetStreamTrigger(u32 trigger);
-u32 AIGetStreamTrigger(void);
-void AISetStreamPlayState(u32 state);
-u32 AIGetStreamPlayState(void);
 void AISetDSPSampleRate(u32 rate);
 u32 AIGetDSPSampleRate(void);
-void AISetStreamSampleRate(u32 rate);
-u32 AIGetStreamSampleRate(void);
-void AISetStreamVolLeft(u8 vol);
-u8 AIGetStreamVolLeft(void);
-void AISetStreamVolRight(u8 vol);
-u8 AIGetStreamVolRight(void);
 void AIInit(u8* stack);
 void AIReset(void);
 
diff --git a/include/revolution/aralt.h b/include/revolution/aralt.h
new file mode 100644
index 0000000000..8a699bb857
--- /dev/null
+++ b/include/revolution/aralt.h
@@ -0,0 +1,56 @@
+#ifndef _REVOLUTION_ARALT_H_
+#define _REVOLUTION_ARALT_H_
+
+#include <revolution/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void (*ARQCallback)(u32 pointerToARQRequest);
+
+struct ARQRequest {
+    /* 0x00 */ struct ARQRequest *next;
+    /* 0x04 */ u32 owner;
+    /* 0x08 */ u32 type;
+    /* 0x0C */ u32 priority;
+    /* 0x10 */ u32 source;
+    /* 0x14 */ u32 dest;
+    /* 0x18 */ u32 length;
+    /* 0x1C */ ARQCallback callback;
+};
+
+#define ARQ_DMA_ALIGNMENT 32
+
+#define ARAM_DIR_MRAM_TO_ARAM 0x00
+#define ARAM_DIR_ARAM_TO_MRAM 0x01
+
+#define ARStartDMARead(mmem, aram, len) \
+    ARStartDMA(ARAM_DIR_ARAM_TO_MRAM, mmem, aram, len)
+#define ARStartDMAWrite(mmem, aram, len) \
+    ARStartDMA(ARAM_DIR_MRAM_TO_ARAM, mmem, aram, len)
+
+typedef struct ARQRequest ARQRequest;
+
+#define ARQ_TYPE_MRAM_TO_ARAM ARAM_DIR_MRAM_TO_ARAM
+#define ARQ_TYPE_ARAM_TO_MRAM ARAM_DIR_ARAM_TO_MRAM
+
+#define ARQ_PRIORITY_LOW  0
+#define ARQ_PRIORITY_HIGH 1
+
+// AR
+ARQCallback ARRegisterDMACallback(ARQCallback callback);
+void ARStartDMA(u32 type, u32 mainmem_addr, u32 aram_addr, u32 length);
+u32 ARAlloc(u32 length);
+u32 ARInit(u32* stack_index_addr, u32 num_entries);
+u32 ARGetBaseAddress(void);
+u32 ARGetSize(void);
+
+// ARQ
+void ARQInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/revolution/esp.h b/include/revolution/esp.h
index 802a028630..43fe6d8787 100644
--- a/include/revolution/esp.h
+++ b/include/revolution/esp.h
@@ -1,5 +1,5 @@
-#ifndef ESP_H
-#define ESP_H
+#ifndef _REVOLUTION_ESP_H_
+#define _REVOLUTION_ESP_H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -122,17 +122,17 @@ typedef struct {
 
 s32 ESP_InitLib(void);
 s32 ESP_CloseLib(void);
-s32 ESP_LaunchTitle(u64, ESTicketView*);
-s32 ESP_GetTicketViews(ESTitleId, ESTicketView*, u32*);
-s32 ESP_DiGetTicketView(const void*, ESTicketView*);
-s32 ESP_DiGetTmd(ESTitleMeta*, u32*);
-s32 ESP_GetTmdView(ESTitleId, ESTmdView*, u32*);
-s32 ESP_GetDataDir(ESTitleId, char*);
-s32 ESP_GetTitleId(ESTitleId*);
-s32 ESP_GetConsumption(ESTicketId, ESLpEntry*, u32*);
+s32 ESP_LaunchTitle(u64 titleID, ESTicketView* pTicketView);
+s32 ESP_GetTicketViews(ESTitleId titleId, ESTicketView* ticketViewList, u32* ticketViewCnt);
+s32 ESP_DiGetTicketView(const void* ticket, ESTicketView* ticketView);
+s32 ESP_DiGetTmd(ESTitleMeta* tmd, u32* tmdSize);
+s32 ESP_GetTmdView(ESTitleId titleId, ESTmdView* tmdView, u32* size);
+s32 ESP_GetDataDir(ESTitleId titleId, char* dataDir);
+s32 ESP_GetTitleId(ESTitleId* titleId);
+s32 ESP_GetConsumption(ESTicketId ticketId, ESLpEntry* entries, u32* nEntries);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif // ESP_H
+#endif // _REVOLUTION_ESP_H_
diff --git a/include/revolution/euart.h b/include/revolution/euart.h
new file mode 100644
index 0000000000..a560debc2d
--- /dev/null
+++ b/include/revolution/euart.h
@@ -0,0 +1,61 @@
+#ifndef _REVOLUTION_EUART_H_
+#define _REVOLUTION_EUART_H_
+
+#include <revolution/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef int UARTError;
+
+typedef enum {
+	kBaudHWSet = -1,
+	kBaud300 = 300,
+	kBaud600 = 600,
+	kBaud1200 = 1200,
+	kBaud1800 = 1800,
+	kBaud2000 = 2000,
+	kBaud2400 = 2400,
+	kBaud3600 = 3600,
+	kBaud4800 = 4800,
+	kBaud7200 = 7200,
+	kBaud9600 = 9600,
+	kBaud19200 = 19200,
+	kBaud38400 = 38400,
+	kBaud57600 = 57600,
+	kBaud115200 = 115200,
+	kBaud230400 = 230400
+} UARTBaudRate;
+
+enum {
+	kUARTDataError = -1,
+	kUARTNoError = 0,
+	kUARTUnknownBaudRate,
+	kUARTConfigurationError,
+	kUARTBufferOverflow,
+	kUARTNoData
+};
+
+typedef enum {
+	EUART_ERROR_NONE = 0,
+	EUART_ERROR_UNINITIALIZED,
+	EUART_ERROR_CANNOT_USE,
+	EUART_ERROR_CHANNEL_FULL,
+	EUART_ERROR_NOT_FIND,
+	EUART_ERROR_INTERNAL,
+	EUART_ERROR_INVALID_PARAMETER,
+	EUART_ERROR_INVALID_HANDLE,
+	EUART_ERROR_COM_OPEN,
+	EUART_ERROR_COMM
+} EUARTError;
+
+
+UARTError InitializeUART(UARTBaudRate);
+UARTError WriteUARTN(const void *, unsigned long);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/revolution/exi.h b/include/revolution/exi.h
index 9672a30aa6..b13745dab2 100644
--- a/include/revolution/exi.h
+++ b/include/revolution/exi.h
@@ -74,6 +74,8 @@ typedef struct EXIControl {
     } queue[3];
 } EXIControl;
 
+extern const u32 __EXIFreq;
+
 EXICallback EXISetExiCallback(s32 channel, EXICallback callback);
 
 void EXIInit(void);
@@ -96,6 +98,12 @@ int EXISelectSD(s32 chan, u32 dev, u32 freq);
 s32 EXIGetType(s32 chan, u32 dev, u32* type);
 char* EXIGetTypeString(u32 type);
 
+s32 EXIGetConsoleType(void);
+void EXIWait(void);
+BOOL EXIWriteReg(s32 chan, u32 dev, u32 exiCmd, void* reg, s32 size);
+BOOL EXIReadRam(s32 chan, u32 dev, u32 exiCmd, void* buffer, s32 size, EXICallback callback);
+BOOL EXIWriteRam(s32 chan, u32 dev, u32 exiCmd, void* buffer, s32 size, EXICallback callback);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/revolution/hio2.h b/include/revolution/hio2.h
new file mode 100644
index 0000000000..3758415931
--- /dev/null
+++ b/include/revolution/hio2.h
@@ -0,0 +1,44 @@
+#ifndef _REVOLUTION_HIO2_H_
+#define _REVOLUTION_HIO2_H_
+
+#include <revolution/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    HIO2_DEVICE_INVALID = -1,
+    HIO2_DEVICE_UNK_0 = 0,
+    HIO2_DEVICE_UNK_1 = 1,
+    HIO2_DEVICE_UNK_2 = 2,
+} HIO2DeviceType;
+
+typedef BOOL (*HIO2EnumCallback)(HIO2DeviceType);
+typedef void (*HIO2UnkCallback)(s32);
+typedef void (*HIO2DisconnectCallback)(s32);
+
+typedef struct HIO2Control {
+    /* 0x00 */ HIO2DeviceType type;
+    /* 0x04 */ s32 chan;
+    /* 0x08 */ u32 _0x8;
+    /* 0x0C */ HIO2UnkCallback exiCallback;
+    /* 0x10 */ HIO2UnkCallback _0x10;
+    /* 0x14 */ HIO2UnkCallback _0x14;
+    /* 0x18 */ HIO2DisconnectCallback disconnectCb;
+} HIO2Control; // size 0x1C
+
+
+BOOL HIO2Init(void);
+BOOL HIO2EnumDevices(HIO2EnumCallback callback);
+s32 HIO2Open(HIO2DeviceType type, HIO2UnkCallback exiCb, HIO2DisconnectCallback disconnectCb);
+BOOL HIO2Close(s32 handle);
+BOOL HIO2Read(s32 handle, u32 addr, void* buffer, s32 size);
+BOOL HIO2Write(s32 handle, u32 addr, void* buffer, s32 size);
+void HIO2Exit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/revolution/hw_regs.h b/include/revolution/hw_regs.h
index 1bf8658f9f..b1f8a2c4e5 100644
--- a/include/revolution/hw_regs.h
+++ b/include/revolution/hw_regs.h
@@ -9,7 +9,7 @@ volatile u32 __PIRegs[12]     AT_ADDRESS(0xCC003000);
 volatile u16 __MEMRegs[64]    AT_ADDRESS(0xCC004000);
 volatile u16 __DSPRegs[]      AT_ADDRESS(0xCC005000);
 volatile u32 __DIRegs[]       AT_ADDRESS(0xCD006000);
-volatile u32 __SIRegs[0x100]  AT_ADDRESS(0xCC006400);
+volatile u32 __SIRegs[0x100]  AT_ADDRESS(0xCD006400);
 volatile u32 __EXIRegs[0x40]  AT_ADDRESS(0xCD006800);
 volatile u32 __AIRegs[8]      AT_ADDRESS(0xCD006C00);
 volatile u32 __IPCRegs[4]     AT_ADDRESS(0xCD000000);
@@ -19,7 +19,7 @@ volatile u32 __IPCRegs[4]     AT_ADDRESS(0xCD000000);
 #define __MEMRegs        ((volatile u16 *)0xCC004000)
 #define __DSPRegs        ((volatile u16 *)0xCC005000)
 #define __DIRegs         ((volatile u32 *)0xCD006000)
-#define __SIRegs         ((volatile u32 *)0xCC006400)
+#define __SIRegs         ((volatile u32 *)0xCD006400)
 #define __EXIRegs        ((volatile u32 *)0xCD006800)
 #define __AIRegs         ((volatile u32 *)0xCD006C00)
 #define __IPCRegs        ((volatile u32 *)0xCD000000)
diff --git a/include/revolution/private/GXFDLShortcut.h b/include/revolution/private/GXFDLShortcut.h
new file mode 100644
index 0000000000..a717d18fb6
--- /dev/null
+++ b/include/revolution/private/GXFDLShortcut.h
@@ -0,0 +1,263 @@
+#ifndef GXFDLSHORTCUT_H
+#define GXFDLSHORTCUT_H
+
+#if __MWERKS__
+#define FAST_GPFLAGSET(line, regOrg, newFlag, regName) \
+do {                                                                                \
+    ASSERTMSGLINE(line, ((u32)(newFlag) & ~((1 << (regName ## _SIZE)) - 1)) == 0, "GX Internal: Register field out of range"); \
+    (regOrg) = (u32) __rlwimi((int) (regOrg),                                       \
+                              (int) (newFlag),                                      \
+                              (regName ## _SHIFT),                                  \
+                              (32-(regName ## _SHIFT)-(regName ## _SIZE)),          \
+                              (31-(regName ## _SHIFT)));                            \
+} while (0)
+#else
+#define FAST_GPFLAGSET(line, regOrg, newFlag, regName)
+#endif
+
+#define CP_VCD_REG_HI_TEXALL_MASK   ((1UL<<CP_VCD_REG_HI_TOTAL_SIZE)-1)
+#define CP_VCD_REG_HI_TEXALL_SHIFT  CP_VCD_REG_HI_TEX0_SHIFT
+#define CP_VCD_REG_LO_COLALL_MASK   (CP_VCD_REG_LO_COL0_MASK|CP_VCD_REG_LO_COL1_MASK)
+#define CP_VCD_REG_LO_COLALL_SHIFT  CP_VCD_REG_LO_COL0_SHIFT
+
+#define TEV_REGISTERL_R8_SIZE   TEV_KREGISTERL_R_SIZE
+#define TEV_REGISTERL_R8_SHIFT  TEV_KREGISTERL_R_SHIFT
+#define TEV_REGISTERL_R8_MASK   TEV_KREGISTERL_R_MASK
+#define SC_TEV_REGISTERL_SET_R8(line, tev_registerl, r8) \
+    FAST_GPFLAGSET(line, tev_registerl, r8, TEV_REGISTERL_R8)
+
+#define TEV_REGISTERL_A8_SIZE   TEV_KREGISTERL_A_SIZE
+#define TEV_REGISTERL_A8_SHIFT  TEV_KREGISTERL_A_SHIFT
+#define TEV_REGISTERL_A8_MASK   TEV_KREGISTERL_A_MASK
+#define SC_TEV_REGISTERL_SET_A8(line, tev_registerl, a8) \
+    FAST_GPFLAGSET(line, tev_registerl, a8, TEV_REGISTERL_A8)
+
+#define TEV_REGISTERH_B8_SIZE   TEV_KREGISTERH_B_SIZE
+#define TEV_REGISTERH_B8_SHIFT  TEV_KREGISTERH_B_SHIFT
+#define TEV_REGISTERH_B8_MASK   TEV_KREGISTERH_B_MASK
+#define SC_TEV_REGISTERH_SET_B8(line, tev_registerh, b8) \
+    FAST_GPFLAGSET(line, tev_registerh, b8, TEV_REGISTERH_B8)
+
+#define TEV_REGISTERH_G8_SIZE   TEV_KREGISTERH_G_SIZE
+#define TEV_REGISTERH_G8_SHIFT  TEV_KREGISTERH_G_SHIFT
+#define TEV_REGISTERH_G8_MASK   TEV_KREGISTERH_G_MASK
+#define SC_TEV_REGISTERH_SET_G8(line, tev_registerh, g8) \
+    FAST_GPFLAGSET(line, tev_registerh, g8, TEV_REGISTERH_G8)
+
+#define TEV_REGISTERL_R8_SIZE   TEV_KREGISTERL_R_SIZE
+#define TEV_REGISTERL_R8_SHIFT  TEV_KREGISTERL_R_SHIFT
+#define TEV_REGISTERL_R8_MASK   TEV_KREGISTERL_R_MASK
+#define SC_TEV_REGISTERL_SET_R8(line, tev_registerl, r8) \
+    FAST_GPFLAGSET(line, tev_registerl, r8, TEV_REGISTERL_R8)
+
+#define TEV_REGISTERL_A8_SIZE   TEV_KREGISTERL_A_SIZE
+#define TEV_REGISTERL_A8_SHIFT  TEV_KREGISTERL_A_SHIFT
+#define TEV_REGISTERL_A8_MASK   TEV_KREGISTERL_A_MASK
+#define SC_TEV_REGISTERL_SET_A8(line, tev_registerl, a8) \
+    FAST_GPFLAGSET(line, tev_registerl, a8, TEV_REGISTERL_A8)
+
+#define TEV_REGISTERH_B8_SIZE   TEV_KREGISTERH_B_SIZE
+#define TEV_REGISTERH_B8_SHIFT  TEV_KREGISTERH_B_SHIFT
+#define TEV_REGISTERH_B8_MASK   TEV_KREGISTERH_B_MASK
+#define SC_TEV_REGISTERH_SET_B8(line, tev_registerh, b8) \
+    FAST_GPFLAGSET(line, tev_registerh, b8, TEV_REGISTERH_B8)
+
+#define TEV_REGISTERH_G8_SIZE   TEV_KREGISTERH_G_SIZE
+#define TEV_REGISTERH_G8_SHIFT  TEV_KREGISTERH_G_SHIFT
+#define TEV_REGISTERH_G8_MASK   TEV_KREGISTERH_G_MASK
+#define SC_TEV_REGISTERH_SET_G8(line, tev_registerh, g8) \
+    FAST_GPFLAGSET(line, tev_registerh, g8, TEV_REGISTERH_G8)
+
+#define XF_AMBIENT0_F_RGBA_SIZE \
+    ((XF_AMBIENT0_F_ALPHA_SIZE)+(XF_AMBIENT0_F_BLUE_SIZE)+ \
+     (XF_AMBIENT0_F_GREEN_SIZE)+(XF_AMBIENT0_F_RED_SIZE))
+#define XF_AMBIENT0_F_RGBA_SHIFT \
+    XF_AMBIENT0_F_ALPHA_SHIFT
+#define XF_AMBIENT0_F_RGBA_MASK \
+    ((XF_AMBIENT0_F_ALPHA_MASK)|(XF_AMBIENT0_F_BLUE_MASK)| \
+     (XF_AMBIENT0_F_GREEN_MASK)|(XF_AMBIENT0_F_RED_MASK))
+#define SC_XF_AMBIENT0_F_SET_RGBA(xf_ambient0_f, rgba) { \
+    xf_ambient0_f = (((unsigned long)(xf_ambient0_f)) & ~XF_AMBIENT0_F_RGBA_MASK) | (((unsigned long)(rgba)) << XF_AMBIENT0_F_RGBA_SHIFT);\
+}
+
+#define XF_AMBIENT0_F_ALPHA_SIZE	8
+#define XF_AMBIENT0_F_ALPHA_SHIFT	0
+#define XF_AMBIENT0_F_ALPHA_MASK	0x000000ff
+#define XF_AMBIENT0_F_GET_ALPHA(xf_ambient0_f) \
+	((((unsigned long)(xf_ambient0_f)) & XF_AMBIENT0_F_ALPHA_MASK) >> XF_AMBIENT0_F_ALPHA_SHIFT)
+#define XF_AMBIENT0_F_SET_ALPHA(xf_ambient0_f, alpha) { \
+	xf_ambient0_f = (((unsigned long)(xf_ambient0_f)) & ~XF_AMBIENT0_F_ALPHA_MASK) | (((unsigned long)(alpha)) << XF_AMBIENT0_F_ALPHA_SHIFT);\
+}
+#define XF_AMBIENT0_F_BLUE_SIZE	8
+#define XF_AMBIENT0_F_BLUE_SHIFT	8
+#define XF_AMBIENT0_F_BLUE_MASK	0x0000ff00
+#define XF_AMBIENT0_F_GET_BLUE(xf_ambient0_f) \
+	((((unsigned long)(xf_ambient0_f)) & XF_AMBIENT0_F_BLUE_MASK) >> XF_AMBIENT0_F_BLUE_SHIFT)
+#define XF_AMBIENT0_F_SET_BLUE(xf_ambient0_f, blue) { \
+	xf_ambient0_f = (((unsigned long)(xf_ambient0_f)) & ~XF_AMBIENT0_F_BLUE_MASK) | (((unsigned long)(blue)) << XF_AMBIENT0_F_BLUE_SHIFT);\
+}
+#define XF_AMBIENT0_F_GREEN_SIZE	8
+#define XF_AMBIENT0_F_GREEN_SHIFT	16
+#define XF_AMBIENT0_F_GREEN_MASK	0x00ff0000
+#define XF_AMBIENT0_F_GET_GREEN(xf_ambient0_f) \
+	((((unsigned long)(xf_ambient0_f)) & XF_AMBIENT0_F_GREEN_MASK) >> XF_AMBIENT0_F_GREEN_SHIFT)
+#define XF_AMBIENT0_F_SET_GREEN(xf_ambient0_f, green) { \
+	xf_ambient0_f = (((unsigned long)(xf_ambient0_f)) & ~XF_AMBIENT0_F_GREEN_MASK) | (((unsigned long)(green)) << XF_AMBIENT0_F_GREEN_SHIFT);\
+}
+#define XF_AMBIENT0_F_RED_SIZE	8
+#define XF_AMBIENT0_F_RED_SHIFT	24
+#define XF_AMBIENT0_F_RED_MASK	0xff000000
+#define XF_AMBIENT0_F_GET_RED(xf_ambient0_f) \
+	((((unsigned long)(xf_ambient0_f)) & XF_AMBIENT0_F_RED_MASK) >> XF_AMBIENT0_F_RED_SHIFT)
+#define XF_AMBIENT0_F_SET_RED(xf_ambient0_f, red) { \
+	xf_ambient0_f = (((unsigned long)(xf_ambient0_f)) & ~XF_AMBIENT0_F_RED_MASK) | (((unsigned long)(red)) << XF_AMBIENT0_F_RED_SHIFT);\
+}
+
+#define XF_AMBIENT0_F_RGB_SIZE \
+    ((XF_AMBIENT0_F_BLUE_SIZE)+(XF_AMBIENT0_F_GREEN_SIZE)+(XF_AMBIENT0_F_RED_SIZE))
+#define XF_AMBIENT0_F_RGB_SHIFT \
+    XF_AMBIENT0_F_BLUE_SHIFT
+#define XF_AMBIENT0_F_RGB_MASK \
+    ((XF_AMBIENT0_F_BLUE_MASK)|(XF_AMBIENT0_F_GREEN_MASK)|(XF_AMBIENT0_F_RED_MASK))
+
+#define SC_XF_AMBIENT0_F_SET_RGB(line, xf_ambient0_f, rgb) \
+    FAST_GPFLAGSET(line, xf_ambient0_f, rgb, XF_AMBIENT0_F_RGB)
+
+#define XF_AMBIENT1_F_RGBA_SIZE \
+    ((XF_AMBIENT1_F_ALPHA_SIZE)+(XF_AMBIENT1_F_BLUE_SIZE)+ \
+     (XF_AMBIENT1_F_GREEN_SIZE)+(XF_AMBIENT1_F_RED_SIZE))
+#define XF_AMBIENT1_F_RGBA_SHIFT \
+    XF_AMBIENT1_F_ALPHA_SHIFT
+#define XF_AMBIENT1_F_RGBA_MASK \
+    ((XF_AMBIENT1_F_ALPHA_MASK)|(XF_AMBIENT1_F_BLUE_MASK)| \
+     (XF_AMBIENT1_F_GREEN_MASK)|(XF_AMBIENT1_F_RED_MASK))
+#define SC_XF_AMBIENT1_F_SET_RGBA(xf_ambient1_f, rgba) { \
+    xf_ambient1_f = (((unsigned long)(xf_ambient1_f)) & ~XF_AMBIENT1_F_RGBA_MASK) | (((unsigned long)(rgba)) << XF_AMBIENT1_F_RGBA_SHIFT);\
+}
+
+#define XF_AMBIENT1_F_ALPHA_SIZE	8
+#define XF_AMBIENT1_F_ALPHA_SHIFT	0
+#define XF_AMBIENT1_F_ALPHA_MASK	0x000000ff
+#define XF_AMBIENT1_F_GET_ALPHA(xf_ambient1_f) \
+	((((unsigned long)(xf_ambient1_f)) & XF_AMBIENT1_F_ALPHA_MASK) >> XF_AMBIENT1_F_ALPHA_SHIFT)
+#define XF_AMBIENT1_F_SET_ALPHA(xf_ambient1_f, alpha) { \
+	xf_ambient1_f = (((unsigned long)(xf_ambient1_f)) & ~XF_AMBIENT1_F_ALPHA_MASK) | (((unsigned long)(alpha)) << XF_AMBIENT1_F_ALPHA_SHIFT);\
+}
+#define XF_AMBIENT1_F_BLUE_SIZE	8
+#define XF_AMBIENT1_F_BLUE_SHIFT	8
+#define XF_AMBIENT1_F_BLUE_MASK	0x0000ff00
+#define XF_AMBIENT1_F_GET_BLUE(xf_ambient1_f) \
+	((((unsigned long)(xf_ambient1_f)) & XF_AMBIENT1_F_BLUE_MASK) >> XF_AMBIENT1_F_BLUE_SHIFT)
+#define XF_AMBIENT1_F_SET_BLUE(xf_ambient1_f, blue) { \
+	xf_ambient1_f = (((unsigned long)(xf_ambient1_f)) & ~XF_AMBIENT1_F_BLUE_MASK) | (((unsigned long)(blue)) << XF_AMBIENT1_F_BLUE_SHIFT);\
+}
+#define XF_AMBIENT1_F_GREEN_SIZE	8
+#define XF_AMBIENT1_F_GREEN_SHIFT	16
+#define XF_AMBIENT1_F_GREEN_MASK	0x00ff0000
+#define XF_AMBIENT1_F_GET_GREEN(xf_ambient1_f) \
+	((((unsigned long)(xf_ambient1_f)) & XF_AMBIENT1_F_GREEN_MASK) >> XF_AMBIENT1_F_GREEN_SHIFT)
+#define XF_AMBIENT1_F_SET_GREEN(xf_ambient1_f, green) { \
+	xf_ambient1_f = (((unsigned long)(xf_ambient1_f)) & ~XF_AMBIENT1_F_GREEN_MASK) | (((unsigned long)(green)) << XF_AMBIENT1_F_GREEN_SHIFT);\
+}
+#define XF_AMBIENT1_F_RED_SIZE	8
+#define XF_AMBIENT1_F_RED_SHIFT	24
+#define XF_AMBIENT1_F_RED_MASK	0xff000000
+#define XF_AMBIENT1_F_GET_RED(xf_ambient1_f) \
+	((((unsigned long)(xf_ambient1_f)) & XF_AMBIENT1_F_RED_MASK) >> XF_AMBIENT1_F_RED_SHIFT)
+#define XF_AMBIENT1_F_SET_RED(xf_ambient1_f, red) { \
+	xf_ambient1_f = (((unsigned long)(xf_ambient1_f)) & ~XF_AMBIENT1_F_RED_MASK) | (((unsigned long)(red)) << XF_AMBIENT1_F_RED_SHIFT);\
+}
+
+#define XF_AMBIENT1_F_RGB_SIZE \
+    ((XF_AMBIENT1_F_BLUE_SIZE)+(XF_AMBIENT1_F_GREEN_SIZE)+(XF_AMBIENT1_F_RED_SIZE))
+#define XF_AMBIENT1_F_RGB_SHIFT \
+    XF_AMBIENT1_F_BLUE_SHIFT
+#define XF_AMBIENT1_F_RGB_MASK \
+    ((XF_AMBIENT1_F_BLUE_MASK)|(XF_AMBIENT1_F_GREEN_MASK)|(XF_AMBIENT1_F_RED_MASK))
+#define SC_XF_AMBIENT1_F_SET_RGB(line, xf_ambient1_f, rgb) \
+    FAST_GPFLAGSET(line, xf_ambient1_f, rgb, XF_AMBIENT1_F_RGB)
+
+#define XF_MATERIAL0_F_RGBA_SIZE \
+    ((XF_MATERIAL0_F_ALPHA_SIZE)+(XF_MATERIAL0_F_BLUE_SIZE)+ \
+     (XF_MATERIAL0_F_GREEN_SIZE)+(XF_MATERIAL0_F_RED_SIZE))
+#define XF_MATERIAL0_F_RGBA_SHIFT \
+    XF_MATERIAL0_F_ALPHA_SHIFT
+#define XF_MATERIAL0_F_RGBA_MASK \
+    ((XF_MATERIAL0_F_ALPHA_MASK)|(XF_MATERIAL0_F_BLUE_MASK)| \
+     (XF_MATERIAL0_F_GREEN_MASK)|(XF_MATERIAL0_F_RED_MASK))
+#define SC_XF_MATERIAL0_F_SET_RGBA(xf_material0_f, rgba) { \
+    xf_material0_f = (((unsigned long)(xf_material0_f)) & ~XF_MATERIAL0_F_RGBA_MASK) | (((unsigned long)(rgba)) << XF_MATERIAL0_F_RGBA_SHIFT);\
+}
+
+#define XF_MATERIAL0_F_RGBA_SIZE \
+    ((XF_MATERIAL0_F_ALPHA_SIZE)+(XF_MATERIAL0_F_BLUE_SIZE)+ \
+     (XF_MATERIAL0_F_GREEN_SIZE)+(XF_MATERIAL0_F_RED_SIZE))
+#define XF_MATERIAL0_F_RGBA_SHIFT \
+    XF_MATERIAL0_F_ALPHA_SHIFT
+#define XF_MATERIAL0_F_RGBA_MASK \
+    ((XF_MATERIAL0_F_ALPHA_MASK)|(XF_MATERIAL0_F_BLUE_MASK)| \
+     (XF_MATERIAL0_F_GREEN_MASK)|(XF_MATERIAL0_F_RED_MASK))
+
+#define XF_MATERIAL0_F_RGB_SIZE \
+    ((XF_MATERIAL0_F_BLUE_SIZE)+(XF_MATERIAL0_F_GREEN_SIZE)+(XF_MATERIAL0_F_RED_SIZE))
+#define XF_MATERIAL0_F_RGB_SHIFT \
+    XF_MATERIAL0_F_BLUE_SHIFT
+#define XF_MATERIAL0_F_RGB_MASK \
+    ((XF_MATERIAL0_F_BLUE_MASK)|(XF_MATERIAL0_F_GREEN_MASK)|(XF_MATERIAL0_F_RED_MASK))
+#define SC_XF_MATERIAL0_F_SET_RGB(line, xf_material0_f, rgb) \
+    FAST_GPFLAGSET(line, xf_material0_f, rgb, XF_MATERIAL0_F_RGB)
+
+#define XF_MATERIAL0_F_RGB_SIZE \
+    ((XF_MATERIAL0_F_BLUE_SIZE)+(XF_MATERIAL0_F_GREEN_SIZE)+(XF_MATERIAL0_F_RED_SIZE))
+#define XF_MATERIAL0_F_RGB_SHIFT \
+    XF_MATERIAL0_F_BLUE_SHIFT
+#define XF_MATERIAL0_F_RGB_MASK \
+    ((XF_MATERIAL0_F_BLUE_MASK)|(XF_MATERIAL0_F_GREEN_MASK)|(XF_MATERIAL0_F_RED_MASK))
+#define SC_XF_MATERIAL0_F_SET_RGB(line, xf_material0_f, rgb) \
+    FAST_GPFLAGSET(line, xf_material0_f, rgb, XF_MATERIAL0_F_RGB)
+
+#define XF_MATERIAL1_F_RGBA_SIZE \
+    ((XF_MATERIAL1_F_ALPHA_SIZE)+(XF_MATERIAL1_F_BLUE_SIZE)+ \
+     (XF_MATERIAL1_F_GREEN_SIZE)+(XF_MATERIAL1_F_RED_SIZE))
+#define XF_MATERIAL1_F_RGBA_SHIFT \
+    XF_MATERIAL1_F_ALPHA_SHIFT
+#define XF_MATERIAL1_F_RGBA_MASK \
+    ((XF_MATERIAL1_F_ALPHA_MASK)|(XF_MATERIAL1_F_BLUE_MASK)| \
+     (XF_MATERIAL1_F_GREEN_MASK)|(XF_MATERIAL1_F_RED_MASK))
+#define SC_XF_MATERIAL1_F_SET_RGBA(xf_material1_f, rgba) { \
+    xf_material1_f = (((unsigned long)(xf_material1_f)) & ~XF_MATERIAL1_F_RGBA_MASK) | (((unsigned long)(rgba)) << XF_MATERIAL1_F_RGBA_SHIFT);\
+}
+
+
+#define XF_MATERIAL1_F_RGB_SIZE \
+    ((XF_MATERIAL1_F_BLUE_SIZE)+(XF_MATERIAL1_F_GREEN_SIZE)+(XF_MATERIAL1_F_RED_SIZE))
+#define XF_MATERIAL1_F_RGB_SHIFT \
+    XF_MATERIAL1_F_BLUE_SHIFT
+#define XF_MATERIAL1_F_RGB_MASK \
+    ((XF_MATERIAL1_F_BLUE_MASK)|(XF_MATERIAL1_F_GREEN_MASK)|(XF_MATERIAL1_F_RED_MASK))
+#define SC_XF_MATERIAL1_F_SET_RGB(line, xf_material1_f, rgb) \
+    FAST_GPFLAGSET(line, xf_material1_f, rgb, XF_MATERIAL1_F_RGB)
+
+#define XF_COLOR0CNTRL_F_LIGHT0123_SIZE \
+    ((XF_COLOR0CNTRL_F_LIGHT0_SIZE)+(XF_COLOR0CNTRL_F_LIGHT1_SIZE)+ \
+     (XF_COLOR0CNTRL_F_LIGHT2_SIZE)+(XF_COLOR0CNTRL_F_LIGHT3_SIZE))
+#define XF_COLOR0CNTRL_F_LIGHT0123_SHIFT \
+    XF_COLOR0CNTRL_F_LIGHT0_SHIFT
+#define XF_COLOR0CNTRL_F_LIGHT0123_MASK \
+    ((XF_COLOR0CNTRL_F_LIGHT0_MASK)|(XF_COLOR0CNTRL_F_LIGHT1_MASK)| \
+     (XF_COLOR0CNTRL_F_LIGHT2_MASK)|(XF_COLOR0CNTRL_F_LIGHT3_MASK))
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHT0123(line, xf_color0cntrl_f, light0123) \
+    FAST_GPFLAGSET(line, xf_color0cntrl_f, light0123, XF_COLOR0CNTRL_F_LIGHT0123)
+
+#define XF_COLOR0CNTRL_F_LIGHT4567_SIZE \
+    ((XF_COLOR0CNTRL_F_LIGHT4_SIZE)+(XF_COLOR0CNTRL_F_LIGHT5_SIZE)+ \
+     (XF_COLOR0CNTRL_F_LIGHT6_SIZE)+(XF_COLOR0CNTRL_F_LIGHT7_SIZE))
+#define XF_COLOR0CNTRL_F_LIGHT4567_SHIFT \
+    XF_COLOR0CNTRL_F_LIGHT4_SHIFT
+#define XF_COLOR0CNTRL_F_LIGHT4567_MASK \
+    ((XF_COLOR0CNTRL_F_LIGHT4_MASK)|(XF_COLOR0CNTRL_F_LIGHT5_MASK)| \
+     (XF_COLOR0CNTRL_F_LIGHT6_MASK)|(XF_COLOR0CNTRL_F_LIGHT7_MASK))
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHT4567(line, xf_color0cntrl_f, light4567) \
+    FAST_GPFLAGSET(line, xf_color0cntrl_f, light4567, XF_COLOR0CNTRL_F_LIGHT4567)
+
+#endif // GXFDLSHORTCUT_H
diff --git a/include/revolution/private/GXRegs.h b/include/revolution/private/GXRegs.h
new file mode 100644
index 0000000000..ab6ca00c4d
--- /dev/null
+++ b/include/revolution/private/GXRegs.h
@@ -0,0 +1,186 @@
+#ifndef GXREGS_H
+#define GXREGS_H
+
+#include <revolution/gx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <revolution/private/bp_reg.h>
+#include <revolution/private/cp_reg.h>
+#include <revolution/private/gen_reg.h>
+#include <revolution/private/pe_reg.h>
+#include <revolution/private/pi_reg.h>
+#include <revolution/private/ras_reg.h>
+#include <revolution/private/su_reg.h>
+#include <revolution/private/tev_reg.h>
+#include <revolution/private/tx_reg.h>
+#include <revolution/private/xf_mem.h>
+
+extern volatile void* __piReg;
+extern volatile void* __cpReg;
+extern volatile void* __peReg;
+extern volatile void* __memReg;
+
+#define MEM_PE_REQCOUNTH_IDX 0x27
+#define MEM_PE_REQCOUNTL_IDX 0x28
+
+/* GX fifo write helpers */
+
+#define GX_WRITE_U8(ub)     \
+    GXWGFifo.u8 = (u8)(ub)
+
+#define GX_WRITE_U16(us)   \
+   GXWGFifo.u16 = (u16)(us)
+
+#define GX_WRITE_U32(ui)   \
+   GXWGFifo.u32 = (u32)(ui)
+
+#define GX_WRITE_F32(f)     \
+   GXWGFifo.f32 = (f32)(f);
+
+
+#define GX_PI_REG_WRITE_U32(a, d) *(vu32*)((vu8*)__piReg + (a)) = (u32)(d)
+
+#define GX_PI_REG_READ_U32(a) *(vu32*)((vu8*)__piReg + (a))
+
+#define GX_CP_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__cpReg + (a)) = (u16)(d)
+
+#define GX_CP_REG_READ_U16(a) *(vu16*)((vu16*)__cpReg + (a))
+
+#define GX_CP_REG_WRITE_U32(a, d) *(vu32*)((vu16*)__cpReg + (a)) = (u32)(d)
+
+#define GX_CP_REG_READ_U32(a) *(vu32*)((vu16*)__cpReg + (a))
+
+#define GX_MEM_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__memReg + (a)) = (u16)(d)
+
+#define GX_MEM_REG_READ_U16(a) *(vu16*)((vu16*)__memReg + (a))
+
+#define GX_PE_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__peReg + (a)) = (u16)(d)
+
+#define GX_PE_REG_READ_U16(a) *(vu16*)((vu16*)__peReg + (a))
+
+#define GX_CP_IDLE_REG_READ_U16(a) GX_CP_REG_READ_U16(a)
+
+#define GX_PI_REG_WRITE_U32(a, d) *(vu32*)((vu8*)__piReg + (a)) = (u32)(d)
+
+#define GX_PI_REG_READ_U32(a) *(vu32*)((vu8*)__piReg + (a))
+
+#define GX_CP_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__cpReg + (a)) = (u16)(d)
+
+#define GX_CP_REG_READ_U16(a) *(vu16*)((vu16*)__cpReg + (a))
+
+#define GX_CP_REG_WRITE_U32(a, d) *(vu32*)((vu16*)__cpReg + (a)) = (u32)(d)
+
+#define GX_CP_REG_READ_U32(a) *(vu32*)((vu16*)__cpReg + (a))
+
+#define GX_MEM_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__memReg + (a)) = (u16)(d)
+
+#define GX_MEM_REG_READ_U16(a) *(vu16*)((vu16*)__memReg + (a))
+
+#define GX_PE_REG_WRITE_U16(a, d) *(vu16*)((vu16*)__peReg + (a)) = (u16)(d)
+
+#define GX_PE_REG_READ_U16(a) *(vu16*)((vu16*)__peReg + (a))
+
+#define GX_CP_IDLE_REG_READ_U16(a) GX_CP_REG_READ_U16(a)
+
+#define GX_WRITE_CP_STRM_REG(addr, vtxfmt, data)                                                                                                     \
+    {                                                                                                                                                \
+        GX_WRITE_U8(CP_OPCODE(0, 1));                                                                                                                \
+        GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr)));                                                                                                \
+        GX_WRITE_U32((data));                                                                                                                        \
+    }
+
+// needed to match some places
+#define GX_WRITE_CP_STRM_REG_alt(addr, vtxfmt, data, rAddr)                                                                                                     \
+    {                                                                                                                                                \
+        s32 regAddr; \
+        GX_WRITE_U8(CP_OPCODE(0, 1));                                                                                                                \
+        GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr)));                                                                                                \
+        GX_WRITE_U32((data));                                                                                                                        \
+        regAddr = rAddr; \
+    }
+
+// needed to match some places
+#if DEBUG
+#define GX_WRITE_CP_STRM_REG_alt2(addr, vtxfmt, data, rAddr)                                                                                                     \
+    {                                                                                                                                                \
+        s32 regAddr; \
+        GX_WRITE_U8(CP_OPCODE(0, 1));                                                                                                                \
+        GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr)));                                                                                                \
+        GX_WRITE_U32((data));                                                                                                                        \
+        regAddr = rAddr; \
+        if (regAddr >= 0 && regAddr < 4) { \
+            __GXData->indexBase[regAddr] = data; \
+        } \
+    }
+#else
+#define GX_WRITE_CP_STRM_REG_alt2(addr, vtxfmt, data, rAddr) GX_WRITE_CP_STRM_REG(addr, vtxfmt, data)
+#endif
+
+// needed to match some places
+#if DEBUG
+#define GX_WRITE_CP_STRM_REG_alt3(addr, vtxfmt, data, rAddr)                                                                                                     \
+    {                                                                                                                                                \
+        s32 regAddr; \
+        GX_WRITE_U8(CP_OPCODE(0, 1));                                                                                                                \
+        GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr)));                                                                                                \
+        GX_WRITE_U32((data));                                                                                                                        \
+        regAddr = rAddr; \
+        if (regAddr >= 0 && regAddr < 4) { \
+            __GXData->indexStride[regAddr] = data; \
+        } \
+    }
+#else
+#define GX_WRITE_CP_STRM_REG_alt3(addr, vtxfmt, data, rAddr) GX_WRITE_CP_STRM_REG(addr, vtxfmt, data)
+#endif
+
+#define GX_WRITE_XF_REG(addr, data, cnt)                                                                                                             \
+    {                                                                                                                                                \
+        GX_WRITE_U8(CP_OPCODE(0, 0x2));                                                                                                              \
+        GX_WRITE_U32(CP_XF_LOADREGS((addr), (cnt)));                                                                                                 \
+        GX_WRITE_U32((data));                                                                                                                        \
+        VERIF_XF_REG(addr, data);                                                                                                                   \
+    }
+
+#define GX_WRITE_XF_MEM_U32(addr, data) GX_WRITE_U32(data)
+#define GX_WRITE_XF_MEM_F32(addr, data) GX_WRITE_F32(data)
+
+#define GX_WRITE_RA_REG(reg)                                                                                                                         \
+    {                                                                                                                                                \
+        GX_WRITE_U8(CP_OPCODE(1, 0xC));                                                                                                              \
+        GX_WRITE_U32((reg));                                                                                                                         \
+        VERIF_RAS_REG(reg); \
+    }
+
+#ifdef __MWERKS__
+#define GX_DEFINE_GX_READ_COUNTER(unit)                                                                                                              \
+    inline u32 __GXRead##unit##CounterU32(u32 regAddrL, u32 regAddrH) {                                                                              \
+        u32 ctrH0, ctrH1, ctrL;                                                                                                                      \
+        ctrH0 = GX_##unit##_REG_READ_U16(regAddrH);                                                                                                  \
+        do {                                                                                                                                         \
+            ctrH1 = ctrH0;                                                                                                                           \
+            ctrL = GX_##unit##_REG_READ_U16(regAddrL);                                                                                               \
+            ctrH0 = GX_##unit##_REG_READ_U16(regAddrH);                                                                                              \
+        } while (ctrH0 != ctrH1);                                                                                                                    \
+        return ((ctrH0 << 16) | ctrL);                                                                                                               \
+    }
+#else
+#define GX_DEFINE_GX_READ_COUNTER(unit)
+#endif
+
+#ifdef __MWERKS__
+#define FAST_FLAG_SET(regOrg, newFlag, shift, size)                                                                                                  \
+    do {                                                                                                                                             \
+        (regOrg) = (u32)__rlwimi((int)(regOrg), (int)(newFlag), (shift), (32 - (shift) - (size)), (31 - (shift)));                                   \
+    } while (0);
+#else
+#define FAST_FLAG_SET(regOrg, newFlag, shift, size)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // GXREGS_H
diff --git a/include/revolution/private/bp_reg.h b/include/revolution/private/bp_reg.h
new file mode 100644
index 0000000000..1ac478453d
--- /dev/null
+++ b/include/revolution/private/bp_reg.h
@@ -0,0 +1,229 @@
+#ifndef BP_REG_H
+#define BP_REG_H
+
+#include <revolution/private/GXFDLShortcut.h>
+
+#define BP_IMASK_RID_SIZE	8
+#define BP_IMASK_RID_SHIFT	24
+#define BP_IMASK_RID_MASK	0xff000000
+#define BP_IMASK_GET_RID(bp_imask) \
+	((((unsigned long)(bp_imask)) & BP_IMASK_RID_MASK) >> BP_IMASK_RID_SHIFT)
+
+#define BP_CMD_BT_SIZE	2
+#define BP_CMD_BT_SHIFT	0
+#define BP_CMD_BT_MASK	0x00000003
+#define BP_CMD_GET_BT(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_BT_MASK) >> BP_CMD_BT_SHIFT)
+
+#define BP_CMD_FMT_SIZE	2
+#define BP_CMD_FMT_SHIFT	2
+#define BP_CMD_FMT_MASK	0x0000000c
+#define BP_CMD_GET_FMT(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_FMT_MASK) >> BP_CMD_FMT_SHIFT)
+
+#define BP_CMD_BIAS_SIZE	3
+#define BP_CMD_BIAS_SHIFT	4
+#define BP_CMD_BIAS_MASK	0x00000070
+#define BP_CMD_GET_BIAS(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_BIAS_MASK) >> BP_CMD_BIAS_SHIFT)
+
+#define BP_CMD_BS_SIZE	2
+#define BP_CMD_BS_SHIFT	7
+#define BP_CMD_BS_MASK	0x00000180
+#define BP_CMD_GET_BS(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_BS_MASK) >> BP_CMD_BS_SHIFT)
+
+#define BP_CMD_M_SIZE	4
+#define BP_CMD_M_SHIFT	9
+#define BP_CMD_M_MASK	0x00001e00
+#define BP_CMD_GET_M(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_M_MASK) >> BP_CMD_M_SHIFT)
+
+#define BP_CMD_SW_SIZE	3
+#define BP_CMD_SW_SHIFT	13
+#define BP_CMD_SW_MASK	0x0000e000
+#define BP_CMD_GET_SW(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_SW_MASK) >> BP_CMD_SW_SHIFT)
+
+#define BP_CMD_TW_SIZE	3
+#define BP_CMD_TW_SHIFT	16
+#define BP_CMD_TW_MASK	0x00070000
+#define BP_CMD_GET_TW(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_TW_MASK) >> BP_CMD_TW_SHIFT)
+
+#define BP_CMD_LB_SIZE	1
+#define BP_CMD_LB_SHIFT	19
+#define BP_CMD_LB_MASK	0x00080000
+#define BP_CMD_GET_LB(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_LB_MASK) >> BP_CMD_LB_SHIFT)
+
+#define BP_CMD_FB_SIZE	1
+#define BP_CMD_FB_SHIFT	20
+#define BP_CMD_FB_MASK	0x00100000
+#define BP_CMD_GET_FB(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_FB_MASK) >> BP_CMD_FB_SHIFT)
+
+#define BP_CMD_PAD0_SIZE	3
+#define BP_CMD_PAD0_SHIFT	21
+#define BP_CMD_PAD0_MASK	0x00e00000
+#define BP_CMD_GET_PAD0(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_PAD0_MASK) >> BP_CMD_PAD0_SHIFT)
+
+#define BP_CMD_RID_SIZE	8
+#define BP_CMD_RID_SHIFT	24
+#define BP_CMD_RID_MASK	0xff000000
+#define BP_CMD_GET_RID(bp_cmd) \
+	((((unsigned long)(bp_cmd)) & BP_CMD_RID_MASK) >> BP_CMD_RID_SHIFT)
+
+#define BP_MTXA_MA_SIZE	11
+#define BP_MTXA_MA_SHIFT	0
+#define BP_MTXA_MA_MASK	0x000007ff
+#define BP_MTXA_GET_MA(bp_mtxa) \
+	((((unsigned long)(bp_mtxa)) & BP_MTXA_MA_MASK) >> BP_MTXA_MA_SHIFT)
+
+#define BP_MTXA_MB_SIZE	11
+#define BP_MTXA_MB_SHIFT	11
+#define BP_MTXA_MB_MASK	0x003ff800
+#define BP_MTXA_GET_MB(bp_mtxa) \
+	((((unsigned long)(bp_mtxa)) & BP_MTXA_MB_MASK) >> BP_MTXA_MB_SHIFT)
+
+#define BP_MTXA_S_SIZE	2
+#define BP_MTXA_S_SHIFT	22
+#define BP_MTXA_S_MASK	0x00c00000
+#define BP_MTXA_GET_S(bp_mtxa) \
+	((((unsigned long)(bp_mtxa)) & BP_MTXA_S_MASK) >> BP_MTXA_S_SHIFT)
+
+#define BP_MTXA_RID_SIZE	8
+#define BP_MTXA_RID_SHIFT	24
+#define BP_MTXA_RID_MASK	0xff000000
+#define BP_MTXA_GET_RID(bp_mtxa) \
+	((((unsigned long)(bp_mtxa)) & BP_MTXA_RID_MASK) >> BP_MTXA_RID_SHIFT)
+
+#define BP_MTXB_MC_SIZE	11
+#define BP_MTXB_MC_SHIFT	0
+#define BP_MTXB_MC_MASK	0x000007ff
+#define BP_MTXB_GET_MC(bp_mtxb) \
+	((((unsigned long)(bp_mtxb)) & BP_MTXB_MC_MASK) >> BP_MTXB_MC_SHIFT)
+
+#define BP_MTXB_MD_SIZE	11
+#define BP_MTXB_MD_SHIFT	11
+#define BP_MTXB_MD_MASK	0x003ff800
+#define BP_MTXB_GET_MD(bp_mtxb) \
+	((((unsigned long)(bp_mtxb)) & BP_MTXB_MD_MASK) >> BP_MTXB_MD_SHIFT)
+
+#define BP_MTXB_S_SIZE	2
+#define BP_MTXB_S_SHIFT	22
+#define BP_MTXB_S_MASK	0x00c00000
+#define BP_MTXB_GET_S(bp_mtxb) \
+	((((unsigned long)(bp_mtxb)) & BP_MTXB_S_MASK) >> BP_MTXB_S_SHIFT)
+
+#define BP_MTXB_RID_SIZE	8
+#define BP_MTXB_RID_SHIFT	24
+#define BP_MTXB_RID_MASK	0xff000000
+#define BP_MTXB_GET_RID(bp_mtxb) \
+	((((unsigned long)(bp_mtxb)) & BP_MTXB_RID_MASK) >> BP_MTXB_RID_SHIFT)
+
+#define BP_MTXC_ME_SIZE	11
+#define BP_MTXC_ME_SHIFT	0
+#define BP_MTXC_ME_MASK	0x000007ff
+#define BP_MTXC_GET_ME(bp_mtxc) \
+	((((unsigned long)(bp_mtxc)) & BP_MTXC_ME_MASK) >> BP_MTXC_ME_SHIFT)
+
+#define BP_MTXC_MF_SIZE	11
+#define BP_MTXC_MF_SHIFT	11
+#define BP_MTXC_MF_MASK	0x003ff800
+#define BP_MTXC_GET_MF(bp_mtxc) \
+	((((unsigned long)(bp_mtxc)) & BP_MTXC_MF_MASK) >> BP_MTXC_MF_SHIFT)
+
+#define BP_MTXC_S_SIZE	2
+#define BP_MTXC_S_SHIFT	22
+#define BP_MTXC_S_MASK	0x00c00000
+#define BP_MTXC_GET_S(bp_mtxc) \
+	((((unsigned long)(bp_mtxc)) & BP_MTXC_S_MASK) >> BP_MTXC_S_SHIFT)
+
+#define BP_MTXC_RID_SIZE	8
+#define BP_MTXC_RID_SHIFT	24
+#define BP_MTXC_RID_MASK	0xff000000
+#define BP_MTXC_GET_RID(bp_mtxc) \
+	((((unsigned long)(bp_mtxc)) & BP_MTXC_RID_MASK) >> BP_MTXC_RID_SHIFT)
+
+
+#define SC_BP_MTXA_SET_MA(line, bp_mtxa,ma) \
+	FAST_GPFLAGSET(line, bp_mtxa,ma,BP_MTXA_MA)
+
+#define SC_BP_MTXA_SET_MB(line, bp_mtxa,mb) \
+	FAST_GPFLAGSET(line, bp_mtxa,mb,BP_MTXA_MB)
+
+#define SC_BP_MTXA_SET_S(line, bp_mtxa,s) \
+	FAST_GPFLAGSET(line, bp_mtxa,s,BP_MTXA_S)
+
+#define SC_BP_MTXA_SET_RID(line, bp_mtxa,rid) \
+	FAST_GPFLAGSET(line, bp_mtxa,rid,BP_MTXA_RID)
+
+#define SC_BP_MTXB_SET_MC(line, bp_mtxb,mc) \
+	FAST_GPFLAGSET(line, bp_mtxb,mc,BP_MTXB_MC)
+
+#define SC_BP_MTXB_SET_MD(line, bp_mtxb,md) \
+	FAST_GPFLAGSET(line, bp_mtxb,md,BP_MTXB_MD)
+
+#define SC_BP_MTXB_SET_S(line, bp_mtxb,s) \
+	FAST_GPFLAGSET(line, bp_mtxb,s,BP_MTXB_S)
+
+#define SC_BP_MTXB_SET_RID(line, bp_mtxb,rid) \
+	FAST_GPFLAGSET(line, bp_mtxb,rid,BP_MTXB_RID)
+
+#define SC_BP_MTXC_SET_ME(line, bp_mtxc,me) \
+	FAST_GPFLAGSET(line, bp_mtxc,me,BP_MTXC_ME)
+
+#define SC_BP_MTXC_SET_MF(line, bp_mtxc,mf) \
+	FAST_GPFLAGSET(line, bp_mtxc,mf,BP_MTXC_MF)
+
+#define SC_BP_MTXC_SET_S(line, bp_mtxc,s) \
+	FAST_GPFLAGSET(line, bp_mtxc,s,BP_MTXC_S)
+
+#define SC_BP_MTXC_SET_RID(line, bp_mtxc,rid) \
+	FAST_GPFLAGSET(line, bp_mtxc,rid,BP_MTXC_RID)
+
+#define SC_BP_CMD_SET_BT(line, bp_cmd,bt) \
+	FAST_GPFLAGSET(line, bp_cmd,bt,BP_CMD_BT)
+
+#define SC_BP_CMD_SET_FMT(line, bp_cmd,fmt) \
+	FAST_GPFLAGSET(line, bp_cmd,fmt,BP_CMD_FMT)
+
+#define SC_BP_CMD_SET_BIAS(line, bp_cmd,bias) \
+	FAST_GPFLAGSET(line, bp_cmd,bias,BP_CMD_BIAS)
+
+#define SC_BP_CMD_SET_BS(line, bp_cmd,bs) \
+	FAST_GPFLAGSET(line, bp_cmd,bs,BP_CMD_BS)
+
+#define SC_BP_CMD_SET_M(line, bp_cmd,m) \
+	FAST_GPFLAGSET(line, bp_cmd,m,BP_CMD_M)
+
+#define SC_BP_CMD_SET_SW(line, bp_cmd,sw) \
+	FAST_GPFLAGSET(line, bp_cmd,sw,BP_CMD_SW)
+
+#define SC_BP_CMD_SET_TW(line, bp_cmd,tw) \
+	FAST_GPFLAGSET(line, bp_cmd,tw,BP_CMD_TW)
+
+#define SC_BP_CMD_SET_LB(line, bp_cmd,lb) \
+	FAST_GPFLAGSET(line, bp_cmd,lb,BP_CMD_LB)
+
+#define SC_BP_CMD_SET_FB(line, bp_cmd,fb) \
+	FAST_GPFLAGSET(line, bp_cmd,fb,BP_CMD_FB)
+
+#define SC_BP_CMD_SET_PAD0(line, bp_cmd,pad0) \
+	FAST_GPFLAGSET(line, bp_cmd,pad0,BP_CMD_PAD0)
+
+#define SC_BP_CMD_SET_RID(line, bp_cmd,rid) \
+	FAST_GPFLAGSET(line, bp_cmd,rid,BP_CMD_RID)
+
+#define SC_BP_IMASK_SET_IMASK(line, bp_imask,imask) \
+	FAST_GPFLAGSET(line, bp_imask,imask,BP_IMASK_IMASK)
+
+#define SC_BP_IMASK_SET_PAD0(line, bp_imask,pad0) \
+	FAST_GPFLAGSET(line, bp_imask,pad0,BP_IMASK_PAD0)
+
+#define SC_BP_IMASK_SET_RID(line, bp_imask,rid) \
+	FAST_GPFLAGSET(line, bp_imask,rid,BP_IMASK_RID)
+
+#endif // BP_REG_H
diff --git a/include/revolution/private/cp_reg.h b/include/revolution/private/cp_reg.h
new file mode 100644
index 0000000000..2cfda75e75
--- /dev/null
+++ b/include/revolution/private/cp_reg.h
@@ -0,0 +1,2043 @@
+#ifndef __FDL_CP_REG_H__
+#define __FDL_CP_REG_H__
+
+#include <revolution/private/GXFDLShortcut.h>
+
+#define FDL_ASSERT(c) 
+
+#define CP_CMD_NOP  0x00
+#define CP_CMD_QUADS    0x10
+#define CP_CMD_QUAD_STRIP   0x11
+#define CP_CMD_TRIANGLES    0x12
+#define CP_CMD_TRIANGLE_STRIP   0x13
+#define CP_CMD_TRIANGLE_FAN 0x14
+#define CP_CMD_LINES    0x15
+#define CP_CMD_LINE_STRIP   0x16
+#define CP_CMD_POINTS   0x17
+#define CP_CMD_LOADREGS 0x01
+#define CP_CMD_XF_LOADREGS  0x02
+#define CP_CMD_XF_IDXLDREG_A    0x04
+#define CP_CMD_XF_IDXLDREG_B    0x05
+#define CP_CMD_XF_IDXLDREG_C    0x06
+#define CP_CMD_XF_IDXLDREG_D    0x07
+#define CP_CMD_CALL_OBJECT  0x08
+#define CP_CMD_VCACHE_INVALIDATE    0x09
+#define CP_CMD_SU_BYPCMD0   0x0c
+#define CP_CMD_SU_BYPCMD1   0x0d
+
+#define CP_COUNTER0L	0x20
+#define CP_COUNTER0H	0x21
+#define CP_COUNTER1L	0x22
+#define CP_COUNTER1H	0x23
+#define CP_COUNTER2L	0x24
+#define CP_COUNTER2H	0x25
+#define CP_COUNTER3L	0x26
+#define CP_COUNTER3H	0x27
+#define CP_VC_CHKCNTL	0x28
+#define CP_VC_CHKCNTH	0x29
+
+#define CP_OPCODE_INDEX_SIZE    3
+#define CP_OPCODE_INDEX_SHIFT   0
+#define CP_OPCODE_INDEX_MASK    0x00000007
+#define CP_OPCODE_GET_INDEX(cp_opcode) \
+    ((((unsigned long)(cp_opcode)) & CP_OPCODE_INDEX_MASK) >> CP_OPCODE_INDEX_SHIFT)
+#define CP_OPCODE_SET_INDEX(cp_opcode, index) { \
+    FDL_ASSERT(!((index) & ~((1 << CP_OPCODE_INDEX_SIZE)-1))); \
+    cp_opcode = (((unsigned long)(cp_opcode)) & ~CP_OPCODE_INDEX_MASK) | (((unsigned long)(index)) << CP_OPCODE_INDEX_SHIFT);\
+}
+#define CP_OPCODE_CMD_SIZE  5
+#define CP_OPCODE_CMD_SHIFT 3
+#define CP_OPCODE_CMD_MASK  0x000000f8
+#define CP_OPCODE_GET_CMD(cp_opcode) \
+    ((((unsigned long)(cp_opcode)) & CP_OPCODE_CMD_MASK) >> CP_OPCODE_CMD_SHIFT)
+#define CP_OPCODE_SET_CMD(cp_opcode, cmd) { \
+    FDL_ASSERT(!((cmd) & ~((1 << CP_OPCODE_CMD_SIZE)-1))); \
+    cp_opcode = (((unsigned long)(cp_opcode)) & ~CP_OPCODE_CMD_MASK) | (((unsigned long)(cmd)) << CP_OPCODE_CMD_SHIFT);\
+}
+#define CP_OPCODE_TOTAL_SIZE    8
+#define CP_OPCODE(index, cmd) \
+    ((((unsigned long)(index)) << CP_OPCODE_INDEX_SHIFT) | \
+    (((unsigned long)(cmd)) << CP_OPCODE_CMD_SHIFT))
+
+#define CP_VC_STAT_RESET    0x00
+#define CP_STAT_ENABLE  0x01
+#define CP_STAT_SEL 0x02
+#define CP_MATINDEX_A   0x03
+#define CP_MATINDEX_B   0x04
+#define CP_VCD_LO   0x05
+#define CP_VCD_HI   0x06
+#define CP_VAT_A    0x07
+#define CP_VAT_B    0x08
+#define CP_VAT_C    0x09
+#define CP_ARRAY_BASE   0x0a
+#define CP_ARRAY_STRIDE 0x0b
+
+#define CP_STREAM_REG_INDEX_SIZE    4
+#define CP_STREAM_REG_INDEX_SHIFT   0
+#define CP_STREAM_REG_INDEX_MASK    0x0000000f
+#define CP_STREAM_REG_GET_INDEX(cp_stream_reg) \
+    ((((unsigned long)(cp_stream_reg)) & CP_STREAM_REG_INDEX_MASK) >> CP_STREAM_REG_INDEX_SHIFT)
+#define CP_STREAM_REG_SET_INDEX(cp_stream_reg, index) { \
+    FDL_ASSERT(!((index) & ~((1 << CP_STREAM_REG_INDEX_SIZE)-1))); \
+    cp_stream_reg = (((unsigned long)(cp_stream_reg)) & ~CP_STREAM_REG_INDEX_MASK) | (((unsigned long)(index)) << CP_STREAM_REG_INDEX_SHIFT);\
+}
+#define CP_STREAM_REG_ADDR_SIZE 4
+#define CP_STREAM_REG_ADDR_SHIFT    4
+#define CP_STREAM_REG_ADDR_MASK 0x000000f0
+#define CP_STREAM_REG_GET_ADDR(cp_stream_reg) \
+    ((((unsigned long)(cp_stream_reg)) & CP_STREAM_REG_ADDR_MASK) >> CP_STREAM_REG_ADDR_SHIFT)
+#define CP_STREAM_REG_SET_ADDR(cp_stream_reg, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_STREAM_REG_ADDR_SIZE)-1))); \
+    cp_stream_reg = (((unsigned long)(cp_stream_reg)) & ~CP_STREAM_REG_ADDR_MASK) | (((unsigned long)(addr)) << CP_STREAM_REG_ADDR_SHIFT);\
+}
+#define CP_STREAM_REG_TOTAL_SIZE    8
+#define CP_STREAM_REG(index, addr) \
+    ((((unsigned long)(index)) << CP_STREAM_REG_INDEX_SHIFT) | \
+    (((unsigned long)(addr)) << CP_STREAM_REG_ADDR_SHIFT))
+
+#define CP_STATUS   0x00
+#define CP_ENABLE   0x01
+#define CP_CLR  0x02
+#define CP_MEMPERF_SEL  0x03
+#define CP_STM_LOW  0x05
+#define CP_FIFO_BASEL   0x10
+#define CP_FIFO_BASEH   0x11
+#define CP_FIFO_TOPL    0x12
+#define CP_FIFO_TOPH    0x13
+#define CP_FIFO_HICNTL  0x14
+#define CP_FIFO_HICNTH  0x15
+#define CP_FIFO_LOCNTL  0x16
+#define CP_FIFO_LOCNTH  0x17
+#define CP_FIFO_COUNTL  0x18
+#define CP_FIFO_COUNTH  0x19
+#define CP_FIFO_WPTRL   0x1a
+#define CP_FIFO_WPTRH   0x1b
+#define CP_FIFO_RPTRL   0x1c
+#define CP_FIFO_RPTRH   0x1d
+#define CP_FIFO_BRKL    0x1e
+#define CP_FIFO_BRKH    0x1f
+#define CP_COUNTER0L    0x20
+#define CP_COUNTER0H    0x21
+#define CP_COUNTER1L    0x22
+#define CP_COUNTER1H    0x23
+#define CP_COUNTER2L    0x24
+#define CP_COUNTER2H    0x25
+#define CP_COUNTER3L    0x26
+#define CP_COUNTER3H    0x27
+#define CP_VC_CHKCNTL   0x28
+#define CP_VC_CHKCNTH   0x29
+#define CP_VC_MISSL 0x2a
+#define CP_VC_MISSH 0x2b
+#define CP_VC_STALLL    0x2c
+#define CP_VC_STALLH    0x2d
+#define CP_FRCLK_CNTL   0x2e
+#define CP_FRCLK_CNTH   0x2f
+#define CP_XF_ADDR  0x30
+#define CP_XF_DATAL 0x31
+#define CP_XF_DATAH 0x32
+#define CP_NUM_REGS 0x33
+
+/*
+*  cp_reg_status struct
+*/
+#define CP_REG_STATUS_OVFL_SIZE 1
+#define CP_REG_STATUS_OVFL_SHIFT    0
+#define CP_REG_STATUS_OVFL_MASK 0x00000001
+#define CP_REG_STATUS_GET_OVFL(cp_reg_status) \
+    ((((unsigned long)(cp_reg_status)) & CP_REG_STATUS_OVFL_MASK) >> CP_REG_STATUS_OVFL_SHIFT)
+#define CP_REG_STATUS_SET_OVFL(cp_reg_status, ovfl) { \
+    FDL_ASSERT(!((ovfl) & ~((1 << CP_REG_STATUS_OVFL_SIZE)-1))); \
+    cp_reg_status = (((unsigned long)(cp_reg_status)) & ~CP_REG_STATUS_OVFL_MASK) | (((unsigned long)(ovfl)) << CP_REG_STATUS_OVFL_SHIFT);\
+}
+#define CP_REG_STATUS_UNFL_SIZE 1
+#define CP_REG_STATUS_UNFL_SHIFT    1
+#define CP_REG_STATUS_UNFL_MASK 0x00000002
+#define CP_REG_STATUS_GET_UNFL(cp_reg_status) \
+    ((((unsigned long)(cp_reg_status)) & CP_REG_STATUS_UNFL_MASK) >> CP_REG_STATUS_UNFL_SHIFT)
+#define CP_REG_STATUS_SET_UNFL(cp_reg_status, unfl) { \
+    FDL_ASSERT(!((unfl) & ~((1 << CP_REG_STATUS_UNFL_SIZE)-1))); \
+    cp_reg_status = (((unsigned long)(cp_reg_status)) & ~CP_REG_STATUS_UNFL_MASK) | (((unsigned long)(unfl)) << CP_REG_STATUS_UNFL_SHIFT);\
+}
+#define CP_REG_STATUS_FIFO_RDIDLE_SIZE  1
+#define CP_REG_STATUS_FIFO_RDIDLE_SHIFT 2
+#define CP_REG_STATUS_FIFO_RDIDLE_MASK  0x00000004
+#define CP_REG_STATUS_GET_FIFO_RDIDLE(cp_reg_status) \
+    ((((unsigned long)(cp_reg_status)) & CP_REG_STATUS_FIFO_RDIDLE_MASK) >> CP_REG_STATUS_FIFO_RDIDLE_SHIFT)
+#define CP_REG_STATUS_SET_FIFO_RDIDLE(cp_reg_status, fifo_rdidle) { \
+    FDL_ASSERT(!((fifo_rdidle) & ~((1 << CP_REG_STATUS_FIFO_RDIDLE_SIZE)-1))); \
+    cp_reg_status = (((unsigned long)(cp_reg_status)) & ~CP_REG_STATUS_FIFO_RDIDLE_MASK) | (((unsigned long)(fifo_rdidle)) << CP_REG_STATUS_FIFO_RDIDLE_SHIFT);\
+}
+#define CP_REG_STATUS_CPIDLE_SIZE   1
+#define CP_REG_STATUS_CPIDLE_SHIFT  3
+#define CP_REG_STATUS_CPIDLE_MASK   0x00000008
+#define CP_REG_STATUS_GET_CPIDLE(cp_reg_status) \
+    ((((unsigned long)(cp_reg_status)) & CP_REG_STATUS_CPIDLE_MASK) >> CP_REG_STATUS_CPIDLE_SHIFT)
+#define CP_REG_STATUS_SET_CPIDLE(cp_reg_status, cpidle) { \
+    FDL_ASSERT(!((cpidle) & ~((1 << CP_REG_STATUS_CPIDLE_SIZE)-1))); \
+    cp_reg_status = (((unsigned long)(cp_reg_status)) & ~CP_REG_STATUS_CPIDLE_MASK) | (((unsigned long)(cpidle)) << CP_REG_STATUS_CPIDLE_SHIFT);\
+}
+#define CP_REG_STATUS_FIFOBRK_SIZE  1
+#define CP_REG_STATUS_FIFOBRK_SHIFT 4
+#define CP_REG_STATUS_FIFOBRK_MASK  0x00000010
+#define CP_REG_STATUS_GET_FIFOBRK(cp_reg_status) \
+    ((((unsigned long)(cp_reg_status)) & CP_REG_STATUS_FIFOBRK_MASK) >> CP_REG_STATUS_FIFOBRK_SHIFT)
+#define CP_REG_STATUS_SET_FIFOBRK(cp_reg_status, fifobrk) { \
+    FDL_ASSERT(!((fifobrk) & ~((1 << CP_REG_STATUS_FIFOBRK_SIZE)-1))); \
+    cp_reg_status = (((unsigned long)(cp_reg_status)) & ~CP_REG_STATUS_FIFOBRK_MASK) | (((unsigned long)(fifobrk)) << CP_REG_STATUS_FIFOBRK_SHIFT);\
+}
+#define CP_REG_STATUS_TOTAL_SIZE    5
+#define CP_REG_STATUS(ovfl, unfl, fifo_rdidle, cpidle, fifobrk) \
+    ((((unsigned long)(ovfl)) << CP_REG_STATUS_OVFL_SHIFT) | \
+    (((unsigned long)(unfl)) << CP_REG_STATUS_UNFL_SHIFT) | \
+    (((unsigned long)(fifo_rdidle)) << CP_REG_STATUS_FIFO_RDIDLE_SHIFT) | \
+    (((unsigned long)(cpidle)) << CP_REG_STATUS_CPIDLE_SHIFT) | \
+    (((unsigned long)(fifobrk)) << CP_REG_STATUS_FIFOBRK_SHIFT))
+
+/*
+*  cp_reg_enable struct
+*/
+#define CP_REG_ENABLE_FIFORD_SIZE   1
+#define CP_REG_ENABLE_FIFORD_SHIFT  0
+#define CP_REG_ENABLE_FIFORD_MASK   0x00000001
+#define CP_REG_ENABLE_GET_FIFORD(cp_reg_enable) \
+    ((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_FIFORD_MASK) >> CP_REG_ENABLE_FIFORD_SHIFT)
+#define CP_REG_ENABLE_SET_FIFORD(cp_reg_enable, fiford) { \
+    FDL_ASSERT(!((fiford) & ~((1 << CP_REG_ENABLE_FIFORD_SIZE)-1))); \
+    cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_FIFORD_MASK) | (((unsigned long)(fiford)) << CP_REG_ENABLE_FIFORD_SHIFT);\
+}
+#define CP_REG_ENABLE_FIFOBRK_SIZE  1
+#define CP_REG_ENABLE_FIFOBRK_SHIFT 1
+#define CP_REG_ENABLE_FIFOBRK_MASK  0x00000002
+#define CP_REG_ENABLE_GET_FIFOBRK(cp_reg_enable) \
+    ((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_FIFOBRK_MASK) >> CP_REG_ENABLE_FIFOBRK_SHIFT)
+#define CP_REG_ENABLE_SET_FIFOBRK(cp_reg_enable, fifobrk) { \
+    FDL_ASSERT(!((fifobrk) & ~((1 << CP_REG_ENABLE_FIFOBRK_SIZE)-1))); \
+    cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_FIFOBRK_MASK) | (((unsigned long)(fifobrk)) << CP_REG_ENABLE_FIFOBRK_SHIFT);\
+}
+#define CP_REG_ENABLE_OVFLINT_SIZE  1
+#define CP_REG_ENABLE_OVFLINT_SHIFT 2
+#define CP_REG_ENABLE_OVFLINT_MASK  0x00000004
+#define CP_REG_ENABLE_GET_OVFLINT(cp_reg_enable) \
+    ((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_OVFLINT_MASK) >> CP_REG_ENABLE_OVFLINT_SHIFT)
+#define CP_REG_ENABLE_SET_OVFLINT(cp_reg_enable, ovflint) { \
+    FDL_ASSERT(!((ovflint) & ~((1 << CP_REG_ENABLE_OVFLINT_SIZE)-1))); \
+    cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_OVFLINT_MASK) | (((unsigned long)(ovflint)) << CP_REG_ENABLE_OVFLINT_SHIFT);\
+}
+#define CP_REG_ENABLE_UNFLINT_SIZE  1
+#define CP_REG_ENABLE_UNFLINT_SHIFT 3
+#define CP_REG_ENABLE_UNFLINT_MASK  0x00000008
+#define CP_REG_ENABLE_GET_UNFLINT(cp_reg_enable) \
+    ((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_UNFLINT_MASK) >> CP_REG_ENABLE_UNFLINT_SHIFT)
+#define CP_REG_ENABLE_SET_UNFLINT(cp_reg_enable, unflint) { \
+    FDL_ASSERT(!((unflint) & ~((1 << CP_REG_ENABLE_UNFLINT_SIZE)-1))); \
+    cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_UNFLINT_MASK) | (((unsigned long)(unflint)) << CP_REG_ENABLE_UNFLINT_SHIFT);\
+}
+#define CP_REG_ENABLE_WRPTRINC_SIZE 1
+#define CP_REG_ENABLE_WRPTRINC_SHIFT    4
+#define CP_REG_ENABLE_WRPTRINC_MASK 0x00000010
+#define CP_REG_ENABLE_GET_WRPTRINC(cp_reg_enable) \
+    ((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_WRPTRINC_MASK) >> CP_REG_ENABLE_WRPTRINC_SHIFT)
+#define CP_REG_ENABLE_SET_WRPTRINC(cp_reg_enable, wrptrinc) { \
+    FDL_ASSERT(!((wrptrinc) & ~((1 << CP_REG_ENABLE_WRPTRINC_SIZE)-1))); \
+    cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_WRPTRINC_MASK) | (((unsigned long)(wrptrinc)) << CP_REG_ENABLE_WRPTRINC_SHIFT);\
+}
+#define CP_REG_ENABLE_FIFOBRKINT_SIZE   1
+#define CP_REG_ENABLE_FIFOBRKINT_SHIFT  5
+#define CP_REG_ENABLE_FIFOBRKINT_MASK   0x00000020
+#define CP_REG_ENABLE_GET_FIFOBRKINT(cp_reg_enable) \
+    ((((unsigned long)(cp_reg_enable)) & CP_REG_ENABLE_FIFOBRKINT_MASK) >> CP_REG_ENABLE_FIFOBRKINT_SHIFT)
+#define CP_REG_ENABLE_SET_FIFOBRKINT(cp_reg_enable, fifobrkint) { \
+    FDL_ASSERT(!((fifobrkint) & ~((1 << CP_REG_ENABLE_FIFOBRKINT_SIZE)-1))); \
+    cp_reg_enable = (((unsigned long)(cp_reg_enable)) & ~CP_REG_ENABLE_FIFOBRKINT_MASK) | (((unsigned long)(fifobrkint)) << CP_REG_ENABLE_FIFOBRKINT_SHIFT);\
+}
+#define CP_REG_ENABLE_TOTAL_SIZE    6
+#define CP_REG_ENABLE(fiford, fifobrk, ovflint, unflint, wrptrinc, fifobrkint) \
+    ((((unsigned long)(fiford)) << CP_REG_ENABLE_FIFORD_SHIFT) | \
+    (((unsigned long)(fifobrk)) << CP_REG_ENABLE_FIFOBRK_SHIFT) | \
+    (((unsigned long)(ovflint)) << CP_REG_ENABLE_OVFLINT_SHIFT) | \
+    (((unsigned long)(unflint)) << CP_REG_ENABLE_UNFLINT_SHIFT) | \
+    (((unsigned long)(wrptrinc)) << CP_REG_ENABLE_WRPTRINC_SHIFT) | \
+    (((unsigned long)(fifobrkint)) << CP_REG_ENABLE_FIFOBRKINT_SHIFT))
+
+/*
+*  cp_reg_clr struct
+*/
+#define CP_REG_CLR_OVFLINT_SIZE 1
+#define CP_REG_CLR_OVFLINT_SHIFT    0
+#define CP_REG_CLR_OVFLINT_MASK 0x00000001
+#define CP_REG_CLR_GET_OVFLINT(cp_reg_clr) \
+    ((((unsigned long)(cp_reg_clr)) & CP_REG_CLR_OVFLINT_MASK) >> CP_REG_CLR_OVFLINT_SHIFT)
+#define CP_REG_CLR_SET_OVFLINT(cp_reg_clr, ovflint) { \
+    FDL_ASSERT(!((ovflint) & ~((1 << CP_REG_CLR_OVFLINT_SIZE)-1))); \
+    cp_reg_clr = (((unsigned long)(cp_reg_clr)) & ~CP_REG_CLR_OVFLINT_MASK) | (((unsigned long)(ovflint)) << CP_REG_CLR_OVFLINT_SHIFT);\
+}
+#define CP_REG_CLR_UNFLINT_SIZE 1
+#define CP_REG_CLR_UNFLINT_SHIFT    1
+#define CP_REG_CLR_UNFLINT_MASK 0x00000002
+#define CP_REG_CLR_GET_UNFLINT(cp_reg_clr) \
+    ((((unsigned long)(cp_reg_clr)) & CP_REG_CLR_UNFLINT_MASK) >> CP_REG_CLR_UNFLINT_SHIFT)
+#define CP_REG_CLR_SET_UNFLINT(cp_reg_clr, unflint) { \
+    FDL_ASSERT(!((unflint) & ~((1 << CP_REG_CLR_UNFLINT_SIZE)-1))); \
+    cp_reg_clr = (((unsigned long)(cp_reg_clr)) & ~CP_REG_CLR_UNFLINT_MASK) | (((unsigned long)(unflint)) << CP_REG_CLR_UNFLINT_SHIFT);\
+}
+#define CP_REG_CLR_PERFCNT_SIZE 1
+#define CP_REG_CLR_PERFCNT_SHIFT    2
+#define CP_REG_CLR_PERFCNT_MASK 0x00000004
+#define CP_REG_CLR_GET_PERFCNT(cp_reg_clr) \
+    ((((unsigned long)(cp_reg_clr)) & CP_REG_CLR_PERFCNT_MASK) >> CP_REG_CLR_PERFCNT_SHIFT)
+#define CP_REG_CLR_SET_PERFCNT(cp_reg_clr, perfcnt) { \
+    FDL_ASSERT(!((perfcnt) & ~((1 << CP_REG_CLR_PERFCNT_SIZE)-1))); \
+    cp_reg_clr = (((unsigned long)(cp_reg_clr)) & ~CP_REG_CLR_PERFCNT_MASK) | (((unsigned long)(perfcnt)) << CP_REG_CLR_PERFCNT_SHIFT);\
+}
+#define CP_REG_CLR_TOTAL_SIZE   3
+#define CP_REG_CLR(ovflint, unflint, perfcnt) \
+    ((((unsigned long)(ovflint)) << CP_REG_CLR_OVFLINT_SHIFT) | \
+    (((unsigned long)(unflint)) << CP_REG_CLR_UNFLINT_SHIFT) | \
+    (((unsigned long)(perfcnt)) << CP_REG_CLR_PERFCNT_SHIFT))
+
+/*
+*  cp_reg_memperfsel struct
+*/
+#define CP_REG_MEMPERFSEL_PERFSEL_SIZE  3
+#define CP_REG_MEMPERFSEL_PERFSEL_SHIFT 0
+#define CP_REG_MEMPERFSEL_PERFSEL_MASK  0x00000007
+#define CP_REG_MEMPERFSEL_GET_PERFSEL(cp_reg_memperfsel) \
+    ((((unsigned long)(cp_reg_memperfsel)) & CP_REG_MEMPERFSEL_PERFSEL_MASK) >> CP_REG_MEMPERFSEL_PERFSEL_SHIFT)
+#define CP_REG_MEMPERFSEL_SET_PERFSEL(cp_reg_memperfsel, perfsel) { \
+    FDL_ASSERT(!((perfsel) & ~((1 << CP_REG_MEMPERFSEL_PERFSEL_SIZE)-1))); \
+    cp_reg_memperfsel = (((unsigned long)(cp_reg_memperfsel)) & ~CP_REG_MEMPERFSEL_PERFSEL_MASK) | (((unsigned long)(perfsel)) << CP_REG_MEMPERFSEL_PERFSEL_SHIFT);\
+}
+#define CP_REG_MEMPERFSEL_TOTAL_SIZE    3
+#define CP_REG_MEMPERFSEL(perfsel) \
+    ((((unsigned long)(perfsel)) << CP_REG_MEMPERFSEL_PERFSEL_SHIFT))
+
+/*
+*  cp_reg_fifo_basel struct
+*/
+#define CP_REG_FIFO_BASEL_PAD0_SIZE 5
+#define CP_REG_FIFO_BASEL_PAD0_SHIFT    0
+#define CP_REG_FIFO_BASEL_PAD0_MASK 0x0000001f
+#define CP_REG_FIFO_BASEL_GET_PAD0(cp_reg_fifo_basel) \
+    ((((unsigned long)(cp_reg_fifo_basel)) & CP_REG_FIFO_BASEL_PAD0_MASK) >> CP_REG_FIFO_BASEL_PAD0_SHIFT)
+#define CP_REG_FIFO_BASEL_SET_PAD0(cp_reg_fifo_basel, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_BASEL_PAD0_SIZE)-1))); \
+    cp_reg_fifo_basel = (((unsigned long)(cp_reg_fifo_basel)) & ~CP_REG_FIFO_BASEL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_BASEL_PAD0_SHIFT);\
+}
+#define CP_REG_FIFO_BASEL_ADDR_SIZE 11
+#define CP_REG_FIFO_BASEL_ADDR_SHIFT    5
+#define CP_REG_FIFO_BASEL_ADDR_MASK 0x0000ffe0
+#define CP_REG_FIFO_BASEL_GET_ADDR(cp_reg_fifo_basel) \
+    ((((unsigned long)(cp_reg_fifo_basel)) & CP_REG_FIFO_BASEL_ADDR_MASK) >> CP_REG_FIFO_BASEL_ADDR_SHIFT)
+#define CP_REG_FIFO_BASEL_SET_ADDR(cp_reg_fifo_basel, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_BASEL_ADDR_SIZE)-1))); \
+    cp_reg_fifo_basel = (((unsigned long)(cp_reg_fifo_basel)) & ~CP_REG_FIFO_BASEL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_BASEL_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_BASEL_TOTAL_SIZE    16
+#define CP_REG_FIFO_BASEL(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_BASEL_ADDR_SHIFT))
+
+/*
+*  cp_reg_fifo_baseh struct
+*/
+#define CP_REG_FIFO_BASEH_ADDR_SIZE 13
+#define CP_REG_FIFO_BASEH_ADDR_SHIFT    0
+#define CP_REG_FIFO_BASEH_ADDR_MASK 0x00001fff
+#define CP_REG_FIFO_BASEH_GET_ADDR(cp_reg_fifo_baseh) \
+    ((((unsigned long)(cp_reg_fifo_baseh)) & CP_REG_FIFO_BASEH_ADDR_MASK) >> CP_REG_FIFO_BASEH_ADDR_SHIFT)
+#define CP_REG_FIFO_BASEH_SET_ADDR(cp_reg_fifo_baseh, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_BASEH_ADDR_SIZE)-1))); \
+    cp_reg_fifo_baseh = (((unsigned long)(cp_reg_fifo_baseh)) & ~CP_REG_FIFO_BASEH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_BASEH_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_BASEH_TOTAL_SIZE    13
+#define CP_REG_FIFO_BASEH(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_BASEH_ADDR_SHIFT))
+
+/*
+*  cp_reg_fifo_topl struct
+*/
+#define CP_REG_FIFO_TOPL_PAD0_SIZE  5
+#define CP_REG_FIFO_TOPL_PAD0_SHIFT 0
+#define CP_REG_FIFO_TOPL_PAD0_MASK  0x0000001f
+#define CP_REG_FIFO_TOPL_GET_PAD0(cp_reg_fifo_topl) \
+    ((((unsigned long)(cp_reg_fifo_topl)) & CP_REG_FIFO_TOPL_PAD0_MASK) >> CP_REG_FIFO_TOPL_PAD0_SHIFT)
+#define CP_REG_FIFO_TOPL_SET_PAD0(cp_reg_fifo_topl, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_TOPL_PAD0_SIZE)-1))); \
+    cp_reg_fifo_topl = (((unsigned long)(cp_reg_fifo_topl)) & ~CP_REG_FIFO_TOPL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_TOPL_PAD0_SHIFT);\
+}
+#define CP_REG_FIFO_TOPL_ADDR_SIZE  11
+#define CP_REG_FIFO_TOPL_ADDR_SHIFT 5
+#define CP_REG_FIFO_TOPL_ADDR_MASK  0x0000ffe0
+#define CP_REG_FIFO_TOPL_GET_ADDR(cp_reg_fifo_topl) \
+    ((((unsigned long)(cp_reg_fifo_topl)) & CP_REG_FIFO_TOPL_ADDR_MASK) >> CP_REG_FIFO_TOPL_ADDR_SHIFT)
+#define CP_REG_FIFO_TOPL_SET_ADDR(cp_reg_fifo_topl, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_TOPL_ADDR_SIZE)-1))); \
+    cp_reg_fifo_topl = (((unsigned long)(cp_reg_fifo_topl)) & ~CP_REG_FIFO_TOPL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_TOPL_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_TOPL_TOTAL_SIZE 16
+#define CP_REG_FIFO_TOPL(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_TOPL_ADDR_SHIFT))
+
+/*
+*  cp_reg_fifo_toph struct
+*/
+#define CP_REG_FIFO_TOPH_ADDR_SIZE  13
+#define CP_REG_FIFO_TOPH_ADDR_SHIFT 0
+#define CP_REG_FIFO_TOPH_ADDR_MASK  0x00001fff
+#define CP_REG_FIFO_TOPH_GET_ADDR(cp_reg_fifo_toph) \
+    ((((unsigned long)(cp_reg_fifo_toph)) & CP_REG_FIFO_TOPH_ADDR_MASK) >> CP_REG_FIFO_TOPH_ADDR_SHIFT)
+#define CP_REG_FIFO_TOPH_SET_ADDR(cp_reg_fifo_toph, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_TOPH_ADDR_SIZE)-1))); \
+    cp_reg_fifo_toph = (((unsigned long)(cp_reg_fifo_toph)) & ~CP_REG_FIFO_TOPH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_TOPH_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_TOPH_TOTAL_SIZE 13
+#define CP_REG_FIFO_TOPH(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_TOPH_ADDR_SHIFT))
+
+/*
+*  cp_reg_fifo_hicntl struct
+*/
+#define CP_REG_FIFO_HICNTL_PAD0_SIZE    5
+#define CP_REG_FIFO_HICNTL_PAD0_SHIFT   0
+#define CP_REG_FIFO_HICNTL_PAD0_MASK    0x0000001f
+#define CP_REG_FIFO_HICNTL_GET_PAD0(cp_reg_fifo_hicntl) \
+    ((((unsigned long)(cp_reg_fifo_hicntl)) & CP_REG_FIFO_HICNTL_PAD0_MASK) >> CP_REG_FIFO_HICNTL_PAD0_SHIFT)
+#define CP_REG_FIFO_HICNTL_SET_PAD0(cp_reg_fifo_hicntl, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_HICNTL_PAD0_SIZE)-1))); \
+    cp_reg_fifo_hicntl = (((unsigned long)(cp_reg_fifo_hicntl)) & ~CP_REG_FIFO_HICNTL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_HICNTL_PAD0_SHIFT);\
+}
+#define CP_REG_FIFO_HICNTL_ADDR_SIZE    11
+#define CP_REG_FIFO_HICNTL_ADDR_SHIFT   5
+#define CP_REG_FIFO_HICNTL_ADDR_MASK    0x0000ffe0
+#define CP_REG_FIFO_HICNTL_GET_ADDR(cp_reg_fifo_hicntl) \
+    ((((unsigned long)(cp_reg_fifo_hicntl)) & CP_REG_FIFO_HICNTL_ADDR_MASK) >> CP_REG_FIFO_HICNTL_ADDR_SHIFT)
+#define CP_REG_FIFO_HICNTL_SET_ADDR(cp_reg_fifo_hicntl, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_HICNTL_ADDR_SIZE)-1))); \
+    cp_reg_fifo_hicntl = (((unsigned long)(cp_reg_fifo_hicntl)) & ~CP_REG_FIFO_HICNTL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_HICNTL_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_HICNTL_TOTAL_SIZE   16
+#define CP_REG_FIFO_HICNTL(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_HICNTL_ADDR_SHIFT))
+
+/*
+*  cp_reg_fifo_hicnth struct
+*/
+#define CP_REG_FIFO_HICNTH_ADDR_SIZE    13
+#define CP_REG_FIFO_HICNTH_ADDR_SHIFT   0
+#define CP_REG_FIFO_HICNTH_ADDR_MASK    0x00001fff
+#define CP_REG_FIFO_HICNTH_GET_ADDR(cp_reg_fifo_hicnth) \
+    ((((unsigned long)(cp_reg_fifo_hicnth)) & CP_REG_FIFO_HICNTH_ADDR_MASK) >> CP_REG_FIFO_HICNTH_ADDR_SHIFT)
+#define CP_REG_FIFO_HICNTH_SET_ADDR(cp_reg_fifo_hicnth, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_HICNTH_ADDR_SIZE)-1))); \
+    cp_reg_fifo_hicnth = (((unsigned long)(cp_reg_fifo_hicnth)) & ~CP_REG_FIFO_HICNTH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_HICNTH_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_HICNTH_TOTAL_SIZE   13
+#define CP_REG_FIFO_HICNTH(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_HICNTH_ADDR_SHIFT))
+
+#define CP_REG_FIFO_LOCNTL_PAD0_SIZE    5
+#define CP_REG_FIFO_LOCNTL_PAD0_SHIFT   0
+#define CP_REG_FIFO_LOCNTL_PAD0_MASK    0x0000001f
+#define CP_REG_FIFO_LOCNTL_GET_PAD0(cp_reg_fifo_locntl) \
+    ((((unsigned long)(cp_reg_fifo_locntl)) & CP_REG_FIFO_LOCNTL_PAD0_MASK) >> CP_REG_FIFO_LOCNTL_PAD0_SHIFT)
+#define CP_REG_FIFO_LOCNTL_SET_PAD0(cp_reg_fifo_locntl, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_LOCNTL_PAD0_SIZE)-1))); \
+    cp_reg_fifo_locntl = (((unsigned long)(cp_reg_fifo_locntl)) & ~CP_REG_FIFO_LOCNTL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_LOCNTL_PAD0_SHIFT);\
+}
+#define CP_REG_FIFO_LOCNTL_ADDR_SIZE    11
+#define CP_REG_FIFO_LOCNTL_ADDR_SHIFT   5
+#define CP_REG_FIFO_LOCNTL_ADDR_MASK    0x0000ffe0
+#define CP_REG_FIFO_LOCNTL_GET_ADDR(cp_reg_fifo_locntl) \
+    ((((unsigned long)(cp_reg_fifo_locntl)) & CP_REG_FIFO_LOCNTL_ADDR_MASK) >> CP_REG_FIFO_LOCNTL_ADDR_SHIFT)
+#define CP_REG_FIFO_LOCNTL_SET_ADDR(cp_reg_fifo_locntl, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_LOCNTL_ADDR_SIZE)-1))); \
+    cp_reg_fifo_locntl = (((unsigned long)(cp_reg_fifo_locntl)) & ~CP_REG_FIFO_LOCNTL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_LOCNTL_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_LOCNTL_TOTAL_SIZE   16
+#define CP_REG_FIFO_LOCNTL(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_LOCNTL_ADDR_SHIFT))
+
+#define CP_REG_FIFO_LOCNTH_ADDR_SIZE    13
+#define CP_REG_FIFO_LOCNTH_ADDR_SHIFT   0
+#define CP_REG_FIFO_LOCNTH_ADDR_MASK    0x00001fff
+#define CP_REG_FIFO_LOCNTH_GET_ADDR(cp_reg_fifo_locnth) \
+    ((((unsigned long)(cp_reg_fifo_locnth)) & CP_REG_FIFO_LOCNTH_ADDR_MASK) >> CP_REG_FIFO_LOCNTH_ADDR_SHIFT)
+#define CP_REG_FIFO_LOCNTH_SET_ADDR(cp_reg_fifo_locnth, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_LOCNTH_ADDR_SIZE)-1))); \
+    cp_reg_fifo_locnth = (((unsigned long)(cp_reg_fifo_locnth)) & ~CP_REG_FIFO_LOCNTH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_LOCNTH_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_LOCNTH_TOTAL_SIZE   13
+#define CP_REG_FIFO_LOCNTH(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_LOCNTH_ADDR_SHIFT))
+
+#define CP_REG_FIFO_COUNTL_PAD0_SIZE    5
+#define CP_REG_FIFO_COUNTL_PAD0_SHIFT   0
+#define CP_REG_FIFO_COUNTL_PAD0_MASK    0x0000001f
+#define CP_REG_FIFO_COUNTL_GET_PAD0(cp_reg_fifo_countl) \
+    ((((unsigned long)(cp_reg_fifo_countl)) & CP_REG_FIFO_COUNTL_PAD0_MASK) >> CP_REG_FIFO_COUNTL_PAD0_SHIFT)
+#define CP_REG_FIFO_COUNTL_SET_PAD0(cp_reg_fifo_countl, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_COUNTL_PAD0_SIZE)-1))); \
+    cp_reg_fifo_countl = (((unsigned long)(cp_reg_fifo_countl)) & ~CP_REG_FIFO_COUNTL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_COUNTL_PAD0_SHIFT);\
+}
+#define CP_REG_FIFO_COUNTL_ADDR_SIZE    11
+#define CP_REG_FIFO_COUNTL_ADDR_SHIFT   5
+#define CP_REG_FIFO_COUNTL_ADDR_MASK    0x0000ffe0
+#define CP_REG_FIFO_COUNTL_GET_ADDR(cp_reg_fifo_countl) \
+    ((((unsigned long)(cp_reg_fifo_countl)) & CP_REG_FIFO_COUNTL_ADDR_MASK) >> CP_REG_FIFO_COUNTL_ADDR_SHIFT)
+#define CP_REG_FIFO_COUNTL_SET_ADDR(cp_reg_fifo_countl, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_COUNTL_ADDR_SIZE)-1))); \
+    cp_reg_fifo_countl = (((unsigned long)(cp_reg_fifo_countl)) & ~CP_REG_FIFO_COUNTL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_COUNTL_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_COUNTL_TOTAL_SIZE   16
+#define CP_REG_FIFO_COUNTL(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_COUNTL_ADDR_SHIFT))
+
+#define CP_REG_FIFO_COUNTH_ADDR_SIZE    13
+#define CP_REG_FIFO_COUNTH_ADDR_SHIFT   0
+#define CP_REG_FIFO_COUNTH_ADDR_MASK    0x00001fff
+#define CP_REG_FIFO_COUNTH_GET_ADDR(cp_reg_fifo_counth) \
+    ((((unsigned long)(cp_reg_fifo_counth)) & CP_REG_FIFO_COUNTH_ADDR_MASK) >> CP_REG_FIFO_COUNTH_ADDR_SHIFT)
+#define CP_REG_FIFO_COUNTH_SET_ADDR(cp_reg_fifo_counth, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_COUNTH_ADDR_SIZE)-1))); \
+    cp_reg_fifo_counth = (((unsigned long)(cp_reg_fifo_counth)) & ~CP_REG_FIFO_COUNTH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_COUNTH_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_COUNTH_TOTAL_SIZE   13
+#define CP_REG_FIFO_COUNTH(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_COUNTH_ADDR_SHIFT))
+
+#define CP_REG_FIFO_WPTRL_PAD0_SIZE 5
+#define CP_REG_FIFO_WPTRL_PAD0_SHIFT    0
+#define CP_REG_FIFO_WPTRL_PAD0_MASK 0x0000001f
+#define CP_REG_FIFO_WPTRL_GET_PAD0(cp_reg_fifo_wptrl) \
+    ((((unsigned long)(cp_reg_fifo_wptrl)) & CP_REG_FIFO_WPTRL_PAD0_MASK) >> CP_REG_FIFO_WPTRL_PAD0_SHIFT)
+#define CP_REG_FIFO_WPTRL_SET_PAD0(cp_reg_fifo_wptrl, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_WPTRL_PAD0_SIZE)-1))); \
+    cp_reg_fifo_wptrl = (((unsigned long)(cp_reg_fifo_wptrl)) & ~CP_REG_FIFO_WPTRL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_WPTRL_PAD0_SHIFT);\
+}
+#define CP_REG_FIFO_WPTRL_ADDR_SIZE 11
+#define CP_REG_FIFO_WPTRL_ADDR_SHIFT    5
+#define CP_REG_FIFO_WPTRL_ADDR_MASK 0x0000ffe0
+#define CP_REG_FIFO_WPTRL_GET_ADDR(cp_reg_fifo_wptrl) \
+    ((((unsigned long)(cp_reg_fifo_wptrl)) & CP_REG_FIFO_WPTRL_ADDR_MASK) >> CP_REG_FIFO_WPTRL_ADDR_SHIFT)
+#define CP_REG_FIFO_WPTRL_SET_ADDR(cp_reg_fifo_wptrl, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_WPTRL_ADDR_SIZE)-1))); \
+    cp_reg_fifo_wptrl = (((unsigned long)(cp_reg_fifo_wptrl)) & ~CP_REG_FIFO_WPTRL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_WPTRL_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_WPTRL_TOTAL_SIZE    16
+#define CP_REG_FIFO_WPTRL(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_WPTRL_ADDR_SHIFT))
+
+#define CP_REG_FIFO_WPTRH_ADDR_SIZE 13
+#define CP_REG_FIFO_WPTRH_ADDR_SHIFT    0
+#define CP_REG_FIFO_WPTRH_ADDR_MASK 0x00001fff
+#define CP_REG_FIFO_WPTRH_GET_ADDR(cp_reg_fifo_wptrh) \
+    ((((unsigned long)(cp_reg_fifo_wptrh)) & CP_REG_FIFO_WPTRH_ADDR_MASK) >> CP_REG_FIFO_WPTRH_ADDR_SHIFT)
+#define CP_REG_FIFO_WPTRH_SET_ADDR(cp_reg_fifo_wptrh, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_WPTRH_ADDR_SIZE)-1))); \
+    cp_reg_fifo_wptrh = (((unsigned long)(cp_reg_fifo_wptrh)) & ~CP_REG_FIFO_WPTRH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_WPTRH_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_WPTRH_TOTAL_SIZE    13
+#define CP_REG_FIFO_WPTRH(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_WPTRH_ADDR_SHIFT))
+
+#define CP_REG_FIFO_RPTRL_PAD0_SIZE 5
+#define CP_REG_FIFO_RPTRL_PAD0_SHIFT    0
+#define CP_REG_FIFO_RPTRL_PAD0_MASK 0x0000001f
+#define CP_REG_FIFO_RPTRL_GET_PAD0(cp_reg_fifo_rptrl) \
+    ((((unsigned long)(cp_reg_fifo_rptrl)) & CP_REG_FIFO_RPTRL_PAD0_MASK) >> CP_REG_FIFO_RPTRL_PAD0_SHIFT)
+#define CP_REG_FIFO_RPTRL_SET_PAD0(cp_reg_fifo_rptrl, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_RPTRL_PAD0_SIZE)-1))); \
+    cp_reg_fifo_rptrl = (((unsigned long)(cp_reg_fifo_rptrl)) & ~CP_REG_FIFO_RPTRL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_RPTRL_PAD0_SHIFT);\
+}
+#define CP_REG_FIFO_RPTRL_ADDR_SIZE 11
+#define CP_REG_FIFO_RPTRL_ADDR_SHIFT    5
+#define CP_REG_FIFO_RPTRL_ADDR_MASK 0x0000ffe0
+#define CP_REG_FIFO_RPTRL_GET_ADDR(cp_reg_fifo_rptrl) \
+    ((((unsigned long)(cp_reg_fifo_rptrl)) & CP_REG_FIFO_RPTRL_ADDR_MASK) >> CP_REG_FIFO_RPTRL_ADDR_SHIFT)
+#define CP_REG_FIFO_RPTRL_SET_ADDR(cp_reg_fifo_rptrl, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_RPTRL_ADDR_SIZE)-1))); \
+    cp_reg_fifo_rptrl = (((unsigned long)(cp_reg_fifo_rptrl)) & ~CP_REG_FIFO_RPTRL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_RPTRL_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_RPTRL_TOTAL_SIZE    16
+#define CP_REG_FIFO_RPTRL(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_RPTRL_ADDR_SHIFT))
+
+#define CP_REG_FIFO_RPTRH_ADDR_SIZE 13
+#define CP_REG_FIFO_RPTRH_ADDR_SHIFT    0
+#define CP_REG_FIFO_RPTRH_ADDR_MASK 0x00001fff
+#define CP_REG_FIFO_RPTRH_GET_ADDR(cp_reg_fifo_rptrh) \
+    ((((unsigned long)(cp_reg_fifo_rptrh)) & CP_REG_FIFO_RPTRH_ADDR_MASK) >> CP_REG_FIFO_RPTRH_ADDR_SHIFT)
+#define CP_REG_FIFO_RPTRH_SET_ADDR(cp_reg_fifo_rptrh, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_RPTRH_ADDR_SIZE)-1))); \
+    cp_reg_fifo_rptrh = (((unsigned long)(cp_reg_fifo_rptrh)) & ~CP_REG_FIFO_RPTRH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_RPTRH_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_RPTRH_TOTAL_SIZE    13
+#define CP_REG_FIFO_RPTRH(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_RPTRH_ADDR_SHIFT))
+
+#define CP_REG_FIFO_BRKL_PAD0_SIZE  5
+#define CP_REG_FIFO_BRKL_PAD0_SHIFT 0
+#define CP_REG_FIFO_BRKL_PAD0_MASK  0x0000001f
+#define CP_REG_FIFO_BRKL_GET_PAD0(cp_reg_fifo_brkl) \
+    ((((unsigned long)(cp_reg_fifo_brkl)) & CP_REG_FIFO_BRKL_PAD0_MASK) >> CP_REG_FIFO_BRKL_PAD0_SHIFT)
+#define CP_REG_FIFO_BRKL_SET_PAD0(cp_reg_fifo_brkl, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_REG_FIFO_BRKL_PAD0_SIZE)-1))); \
+    cp_reg_fifo_brkl = (((unsigned long)(cp_reg_fifo_brkl)) & ~CP_REG_FIFO_BRKL_PAD0_MASK) | (((unsigned long)(pad0)) << CP_REG_FIFO_BRKL_PAD0_SHIFT);\
+}
+#define CP_REG_FIFO_BRKL_ADDR_SIZE  11
+#define CP_REG_FIFO_BRKL_ADDR_SHIFT 5
+#define CP_REG_FIFO_BRKL_ADDR_MASK  0x0000ffe0
+#define CP_REG_FIFO_BRKL_GET_ADDR(cp_reg_fifo_brkl) \
+    ((((unsigned long)(cp_reg_fifo_brkl)) & CP_REG_FIFO_BRKL_ADDR_MASK) >> CP_REG_FIFO_BRKL_ADDR_SHIFT)
+#define CP_REG_FIFO_BRKL_SET_ADDR(cp_reg_fifo_brkl, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_BRKL_ADDR_SIZE)-1))); \
+    cp_reg_fifo_brkl = (((unsigned long)(cp_reg_fifo_brkl)) & ~CP_REG_FIFO_BRKL_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_BRKL_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_BRKL_TOTAL_SIZE 16
+#define CP_REG_FIFO_BRKL(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_BRKL_ADDR_SHIFT))
+
+/*
+*  cp_reg_fifo_brkh struct
+*/
+#define CP_REG_FIFO_BRKH_ADDR_SIZE  13
+#define CP_REG_FIFO_BRKH_ADDR_SHIFT 0
+#define CP_REG_FIFO_BRKH_ADDR_MASK  0x00001fff
+#define CP_REG_FIFO_BRKH_GET_ADDR(cp_reg_fifo_brkh) \
+    ((((unsigned long)(cp_reg_fifo_brkh)) & CP_REG_FIFO_BRKH_ADDR_MASK) >> CP_REG_FIFO_BRKH_ADDR_SHIFT)
+#define CP_REG_FIFO_BRKH_SET_ADDR(cp_reg_fifo_brkh, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_REG_FIFO_BRKH_ADDR_SIZE)-1))); \
+    cp_reg_fifo_brkh = (((unsigned long)(cp_reg_fifo_brkh)) & ~CP_REG_FIFO_BRKH_ADDR_MASK) | (((unsigned long)(addr)) << CP_REG_FIFO_BRKH_ADDR_SHIFT);\
+}
+#define CP_REG_FIFO_BRKH_TOTAL_SIZE 13
+#define CP_REG_FIFO_BRKH(addr) \
+    ((((unsigned long)(addr)) << CP_REG_FIFO_BRKH_ADDR_SHIFT))
+
+/*
+*  memperf_sel enum
+*/
+#define MEMPERF_ZERO    0x00000000
+#define MEMPERF_ONE 0x00000001
+#define DFIFO_REQ_CNT   0x00000002
+#define OBJCALL_REQ_CNT 0x00000003
+#define VCMISS_REQ_CNT  0x00000004
+#define ALL_MEMREQ_CNT  0x00000005
+#define MEMPERF_SEL_UNUSED_6    0x00000006
+#define MEMPERF_SEL_UNUSED_7    0x00000007
+
+/*
+*  vtx_attr_name value
+*/
+#define VTX_ATTR_POSMATIDX  0x00
+#define VTX_ATTR_TEX0MATIDX 0x01
+#define VTX_ATTR_TEX1MATIDX 0x02
+#define VTX_ATTR_TEX2MATIDX 0x03
+#define VTX_ATTR_TEX3MATIDX 0x04
+#define VTX_ATTR_TEX4MATIDX 0x05
+#define VTX_ATTR_TEX5MATIDX 0x06
+#define VTX_ATTR_TEX6MATIDX 0x07
+#define VTX_ATTR_TEX7MATIDX 0x08
+#define VTX_ATTR_POS    0x09
+#define VTX_ATTR_NRM    0x0a
+#define VTX_ATTR_COL0   0x0b
+#define VTX_ATTR_COL1   0x0c
+#define VTX_ATTR_TEX0   0x0d
+#define VTX_ATTR_TEX1   0x0e
+#define VTX_ATTR_TEX2   0x0f
+#define VTX_ATTR_TEX3   0x10
+#define VTX_ATTR_TEX4   0x11
+#define VTX_ATTR_TEX5   0x12
+#define VTX_ATTR_TEX6   0x13
+#define VTX_ATTR_TEX7   0x14
+#define VTX_ATTR_POSARRAY   0x15
+#define VTX_ATTR_NRMARRAY   0x16
+#define VTX_ATTR_TEXARRAY   0x17
+#define VTX_ATTR_LIGHTARRAY 0x18
+#define VTX_NUM_ATTR    0x19
+
+/*
+*  vtx_attr_type value
+*/
+#define ATTR_NONE   0x0
+#define ATTR_DIRECT 0x1
+#define ATTR_INDEX8 0x2
+#define ATTR_INDEX16    0x3
+
+/*
+*  attr_comp_fmt value
+*/
+#define ATTR_COMP_UBYTE 0x0
+#define ATTR_COMP_BYTE  0x1
+#define ATTR_COMP_USHORT    0x2
+#define ATTR_COMP_SHORT 0x3
+#define ATTR_COMP_FLOAT 0x4
+
+/*
+*  attr_clr_fmt value
+*/
+#define ATTR_CLR_565    0x0
+#define ATTR_CLR_888    0x1
+#define ATTR_CLR_888X   0x2
+#define ATTR_CLR_4444   0x3
+#define ATTR_CLR_6666   0x4
+#define ATTR_CLR_8888   0x5
+
+/*
+*  cp_vcd_reg_lo struct
+*/
+#define CP_VCD_REG_LO_PMIDX_SIZE    1
+#define CP_VCD_REG_LO_PMIDX_SHIFT   0
+#define CP_VCD_REG_LO_PMIDX_MASK    0x00000001
+#define CP_VCD_REG_LO_GET_PMIDX(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_PMIDX_MASK) >> CP_VCD_REG_LO_PMIDX_SHIFT)
+#define CP_VCD_REG_LO_SET_PMIDX(cp_vcd_reg_lo, pmidx) { \
+    FDL_ASSERT(!((pmidx) & ~((1 << CP_VCD_REG_LO_PMIDX_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_PMIDX_MASK) | (((unsigned long)(pmidx)) << CP_VCD_REG_LO_PMIDX_SHIFT);\
+}
+#define CP_VCD_REG_LO_T0MIDX_SIZE   1
+#define CP_VCD_REG_LO_T0MIDX_SHIFT  1
+#define CP_VCD_REG_LO_T0MIDX_MASK   0x00000002
+#define CP_VCD_REG_LO_GET_T0MIDX(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T0MIDX_MASK) >> CP_VCD_REG_LO_T0MIDX_SHIFT)
+#define CP_VCD_REG_LO_SET_T0MIDX(cp_vcd_reg_lo, t0midx) { \
+    FDL_ASSERT(!((t0midx) & ~((1 << CP_VCD_REG_LO_T0MIDX_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T0MIDX_MASK) | (((unsigned long)(t0midx)) << CP_VCD_REG_LO_T0MIDX_SHIFT);\
+}
+#define CP_VCD_REG_LO_T1MIDX_SIZE   1
+#define CP_VCD_REG_LO_T1MIDX_SHIFT  2
+#define CP_VCD_REG_LO_T1MIDX_MASK   0x00000004
+#define CP_VCD_REG_LO_GET_T1MIDX(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T1MIDX_MASK) >> CP_VCD_REG_LO_T1MIDX_SHIFT)
+#define CP_VCD_REG_LO_SET_T1MIDX(cp_vcd_reg_lo, t1midx) { \
+    FDL_ASSERT(!((t1midx) & ~((1 << CP_VCD_REG_LO_T1MIDX_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T1MIDX_MASK) | (((unsigned long)(t1midx)) << CP_VCD_REG_LO_T1MIDX_SHIFT);\
+}
+#define CP_VCD_REG_LO_T2MIDX_SIZE   1
+#define CP_VCD_REG_LO_T2MIDX_SHIFT  3
+#define CP_VCD_REG_LO_T2MIDX_MASK   0x00000008
+#define CP_VCD_REG_LO_GET_T2MIDX(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T2MIDX_MASK) >> CP_VCD_REG_LO_T2MIDX_SHIFT)
+#define CP_VCD_REG_LO_SET_T2MIDX(cp_vcd_reg_lo, t2midx) { \
+    FDL_ASSERT(!((t2midx) & ~((1 << CP_VCD_REG_LO_T2MIDX_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T2MIDX_MASK) | (((unsigned long)(t2midx)) << CP_VCD_REG_LO_T2MIDX_SHIFT);\
+}
+#define CP_VCD_REG_LO_T3MIDX_SIZE   1
+#define CP_VCD_REG_LO_T3MIDX_SHIFT  4
+#define CP_VCD_REG_LO_T3MIDX_MASK   0x00000010
+#define CP_VCD_REG_LO_GET_T3MIDX(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T3MIDX_MASK) >> CP_VCD_REG_LO_T3MIDX_SHIFT)
+#define CP_VCD_REG_LO_SET_T3MIDX(cp_vcd_reg_lo, t3midx) { \
+    FDL_ASSERT(!((t3midx) & ~((1 << CP_VCD_REG_LO_T3MIDX_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T3MIDX_MASK) | (((unsigned long)(t3midx)) << CP_VCD_REG_LO_T3MIDX_SHIFT);\
+}
+#define CP_VCD_REG_LO_T4MIDX_SIZE   1
+#define CP_VCD_REG_LO_T4MIDX_SHIFT  5
+#define CP_VCD_REG_LO_T4MIDX_MASK   0x00000020
+#define CP_VCD_REG_LO_GET_T4MIDX(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T4MIDX_MASK) >> CP_VCD_REG_LO_T4MIDX_SHIFT)
+#define CP_VCD_REG_LO_SET_T4MIDX(cp_vcd_reg_lo, t4midx) { \
+    FDL_ASSERT(!((t4midx) & ~((1 << CP_VCD_REG_LO_T4MIDX_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T4MIDX_MASK) | (((unsigned long)(t4midx)) << CP_VCD_REG_LO_T4MIDX_SHIFT);\
+}
+#define CP_VCD_REG_LO_T5MIDX_SIZE   1
+#define CP_VCD_REG_LO_T5MIDX_SHIFT  6
+#define CP_VCD_REG_LO_T5MIDX_MASK   0x00000040
+#define CP_VCD_REG_LO_GET_T5MIDX(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T5MIDX_MASK) >> CP_VCD_REG_LO_T5MIDX_SHIFT)
+#define CP_VCD_REG_LO_SET_T5MIDX(cp_vcd_reg_lo, t5midx) { \
+    FDL_ASSERT(!((t5midx) & ~((1 << CP_VCD_REG_LO_T5MIDX_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T5MIDX_MASK) | (((unsigned long)(t5midx)) << CP_VCD_REG_LO_T5MIDX_SHIFT);\
+}
+#define CP_VCD_REG_LO_T6MIDX_SIZE   1
+#define CP_VCD_REG_LO_T6MIDX_SHIFT  7
+#define CP_VCD_REG_LO_T6MIDX_MASK   0x00000080
+#define CP_VCD_REG_LO_GET_T6MIDX(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T6MIDX_MASK) >> CP_VCD_REG_LO_T6MIDX_SHIFT)
+#define CP_VCD_REG_LO_SET_T6MIDX(cp_vcd_reg_lo, t6midx) { \
+    FDL_ASSERT(!((t6midx) & ~((1 << CP_VCD_REG_LO_T6MIDX_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T6MIDX_MASK) | (((unsigned long)(t6midx)) << CP_VCD_REG_LO_T6MIDX_SHIFT);\
+}
+#define CP_VCD_REG_LO_T7MIDX_SIZE   1
+#define CP_VCD_REG_LO_T7MIDX_SHIFT  8
+#define CP_VCD_REG_LO_T7MIDX_MASK   0x00000100
+#define CP_VCD_REG_LO_GET_T7MIDX(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_T7MIDX_MASK) >> CP_VCD_REG_LO_T7MIDX_SHIFT)
+#define CP_VCD_REG_LO_SET_T7MIDX(cp_vcd_reg_lo, t7midx) { \
+    FDL_ASSERT(!((t7midx) & ~((1 << CP_VCD_REG_LO_T7MIDX_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_T7MIDX_MASK) | (((unsigned long)(t7midx)) << CP_VCD_REG_LO_T7MIDX_SHIFT);\
+}
+#define CP_VCD_REG_LO_POS_SIZE  2
+#define CP_VCD_REG_LO_POS_SHIFT 9
+#define CP_VCD_REG_LO_POS_MASK  0x00000600
+#define CP_VCD_REG_LO_GET_POS(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_POS_MASK) >> CP_VCD_REG_LO_POS_SHIFT)
+#define CP_VCD_REG_LO_SET_POS(cp_vcd_reg_lo, pos) { \
+    FDL_ASSERT(!((pos) & ~((1 << CP_VCD_REG_LO_POS_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_POS_MASK) | (((unsigned long)(pos)) << CP_VCD_REG_LO_POS_SHIFT);\
+}
+#define CP_VCD_REG_LO_NRM_SIZE  2
+#define CP_VCD_REG_LO_NRM_SHIFT 11
+#define CP_VCD_REG_LO_NRM_MASK  0x00001800
+#define CP_VCD_REG_LO_GET_NRM(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_NRM_MASK) >> CP_VCD_REG_LO_NRM_SHIFT)
+#define CP_VCD_REG_LO_SET_NRM(cp_vcd_reg_lo, nrm) { \
+    FDL_ASSERT(!((nrm) & ~((1 << CP_VCD_REG_LO_NRM_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_NRM_MASK) | (((unsigned long)(nrm)) << CP_VCD_REG_LO_NRM_SHIFT);\
+}
+#define CP_VCD_REG_LO_COL0_SIZE 2
+#define CP_VCD_REG_LO_COL0_SHIFT    13
+#define CP_VCD_REG_LO_COL0_MASK 0x00006000
+#define CP_VCD_REG_LO_GET_COL0(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_COL0_MASK) >> CP_VCD_REG_LO_COL0_SHIFT)
+#define CP_VCD_REG_LO_SET_COL0(cp_vcd_reg_lo, col0) { \
+    FDL_ASSERT(!((col0) & ~((1 << CP_VCD_REG_LO_COL0_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_COL0_MASK) | (((unsigned long)(col0)) << CP_VCD_REG_LO_COL0_SHIFT);\
+}
+#define CP_VCD_REG_LO_COL1_SIZE 2
+#define CP_VCD_REG_LO_COL1_SHIFT    15
+#define CP_VCD_REG_LO_COL1_MASK 0x00018000
+#define CP_VCD_REG_LO_GET_COL1(cp_vcd_reg_lo) \
+    ((((unsigned long)(cp_vcd_reg_lo)) & CP_VCD_REG_LO_COL1_MASK) >> CP_VCD_REG_LO_COL1_SHIFT)
+#define CP_VCD_REG_LO_SET_COL1(cp_vcd_reg_lo, col1) { \
+    FDL_ASSERT(!((col1) & ~((1 << CP_VCD_REG_LO_COL1_SIZE)-1))); \
+    cp_vcd_reg_lo = (((unsigned long)(cp_vcd_reg_lo)) & ~CP_VCD_REG_LO_COL1_MASK) | (((unsigned long)(col1)) << CP_VCD_REG_LO_COL1_SHIFT);\
+}
+#define CP_VCD_REG_LO_TOTAL_SIZE    17
+#define CP_VCD_REG_LO(pmidx, t0midx, t1midx, t2midx, t3midx, t4midx, t5midx, t6midx, t7midx, pos, nrm, col0, col1) \
+    ((((unsigned long)(pmidx)) << CP_VCD_REG_LO_PMIDX_SHIFT) | \
+    (((unsigned long)(t0midx)) << CP_VCD_REG_LO_T0MIDX_SHIFT) | \
+    (((unsigned long)(t1midx)) << CP_VCD_REG_LO_T1MIDX_SHIFT) | \
+    (((unsigned long)(t2midx)) << CP_VCD_REG_LO_T2MIDX_SHIFT) | \
+    (((unsigned long)(t3midx)) << CP_VCD_REG_LO_T3MIDX_SHIFT) | \
+    (((unsigned long)(t4midx)) << CP_VCD_REG_LO_T4MIDX_SHIFT) | \
+    (((unsigned long)(t5midx)) << CP_VCD_REG_LO_T5MIDX_SHIFT) | \
+    (((unsigned long)(t6midx)) << CP_VCD_REG_LO_T6MIDX_SHIFT) | \
+    (((unsigned long)(t7midx)) << CP_VCD_REG_LO_T7MIDX_SHIFT) | \
+    (((unsigned long)(pos)) << CP_VCD_REG_LO_POS_SHIFT) | \
+    (((unsigned long)(nrm)) << CP_VCD_REG_LO_NRM_SHIFT) | \
+    (((unsigned long)(col0)) << CP_VCD_REG_LO_COL0_SHIFT) | \
+    (((unsigned long)(col1)) << CP_VCD_REG_LO_COL1_SHIFT))
+
+/*
+*  cp_vcd_reg_hi struct
+*/
+#define CP_VCD_REG_HI_TEX0_SIZE 2
+#define CP_VCD_REG_HI_TEX0_SHIFT    0
+#define CP_VCD_REG_HI_TEX0_MASK 0x00000003
+#define CP_VCD_REG_HI_GET_TEX0(cp_vcd_reg_hi) \
+    ((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX0_MASK) >> CP_VCD_REG_HI_TEX0_SHIFT)
+#define CP_VCD_REG_HI_SET_TEX0(cp_vcd_reg_hi, tex0) { \
+    FDL_ASSERT(!((tex0) & ~((1 << CP_VCD_REG_HI_TEX0_SIZE)-1))); \
+    cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX0_MASK) | (((unsigned long)(tex0)) << CP_VCD_REG_HI_TEX0_SHIFT);\
+}
+#define CP_VCD_REG_HI_TEX1_SIZE 2
+#define CP_VCD_REG_HI_TEX1_SHIFT    2
+#define CP_VCD_REG_HI_TEX1_MASK 0x0000000c
+#define CP_VCD_REG_HI_GET_TEX1(cp_vcd_reg_hi) \
+    ((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX1_MASK) >> CP_VCD_REG_HI_TEX1_SHIFT)
+#define CP_VCD_REG_HI_SET_TEX1(cp_vcd_reg_hi, tex1) { \
+    FDL_ASSERT(!((tex1) & ~((1 << CP_VCD_REG_HI_TEX1_SIZE)-1))); \
+    cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX1_MASK) | (((unsigned long)(tex1)) << CP_VCD_REG_HI_TEX1_SHIFT);\
+}
+#define CP_VCD_REG_HI_TEX2_SIZE 2
+#define CP_VCD_REG_HI_TEX2_SHIFT    4
+#define CP_VCD_REG_HI_TEX2_MASK 0x00000030
+#define CP_VCD_REG_HI_GET_TEX2(cp_vcd_reg_hi) \
+    ((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX2_MASK) >> CP_VCD_REG_HI_TEX2_SHIFT)
+#define CP_VCD_REG_HI_SET_TEX2(cp_vcd_reg_hi, tex2) { \
+    FDL_ASSERT(!((tex2) & ~((1 << CP_VCD_REG_HI_TEX2_SIZE)-1))); \
+    cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX2_MASK) | (((unsigned long)(tex2)) << CP_VCD_REG_HI_TEX2_SHIFT);\
+}
+#define CP_VCD_REG_HI_TEX3_SIZE 2
+#define CP_VCD_REG_HI_TEX3_SHIFT    6
+#define CP_VCD_REG_HI_TEX3_MASK 0x000000c0
+#define CP_VCD_REG_HI_GET_TEX3(cp_vcd_reg_hi) \
+    ((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX3_MASK) >> CP_VCD_REG_HI_TEX3_SHIFT)
+#define CP_VCD_REG_HI_SET_TEX3(cp_vcd_reg_hi, tex3) { \
+    FDL_ASSERT(!((tex3) & ~((1 << CP_VCD_REG_HI_TEX3_SIZE)-1))); \
+    cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX3_MASK) | (((unsigned long)(tex3)) << CP_VCD_REG_HI_TEX3_SHIFT);\
+}
+#define CP_VCD_REG_HI_TEX4_SIZE 2
+#define CP_VCD_REG_HI_TEX4_SHIFT    8
+#define CP_VCD_REG_HI_TEX4_MASK 0x00000300
+#define CP_VCD_REG_HI_GET_TEX4(cp_vcd_reg_hi) \
+    ((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX4_MASK) >> CP_VCD_REG_HI_TEX4_SHIFT)
+#define CP_VCD_REG_HI_SET_TEX4(cp_vcd_reg_hi, tex4) { \
+    FDL_ASSERT(!((tex4) & ~((1 << CP_VCD_REG_HI_TEX4_SIZE)-1))); \
+    cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX4_MASK) | (((unsigned long)(tex4)) << CP_VCD_REG_HI_TEX4_SHIFT);\
+}
+#define CP_VCD_REG_HI_TEX5_SIZE 2
+#define CP_VCD_REG_HI_TEX5_SHIFT    10
+#define CP_VCD_REG_HI_TEX5_MASK 0x00000c00
+#define CP_VCD_REG_HI_GET_TEX5(cp_vcd_reg_hi) \
+    ((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX5_MASK) >> CP_VCD_REG_HI_TEX5_SHIFT)
+#define CP_VCD_REG_HI_SET_TEX5(cp_vcd_reg_hi, tex5) { \
+    FDL_ASSERT(!((tex5) & ~((1 << CP_VCD_REG_HI_TEX5_SIZE)-1))); \
+    cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX5_MASK) | (((unsigned long)(tex5)) << CP_VCD_REG_HI_TEX5_SHIFT);\
+}
+#define CP_VCD_REG_HI_TEX6_SIZE 2
+#define CP_VCD_REG_HI_TEX6_SHIFT    12
+#define CP_VCD_REG_HI_TEX6_MASK 0x00003000
+#define CP_VCD_REG_HI_GET_TEX6(cp_vcd_reg_hi) \
+    ((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX6_MASK) >> CP_VCD_REG_HI_TEX6_SHIFT)
+#define CP_VCD_REG_HI_SET_TEX6(cp_vcd_reg_hi, tex6) { \
+    FDL_ASSERT(!((tex6) & ~((1 << CP_VCD_REG_HI_TEX6_SIZE)-1))); \
+    cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX6_MASK) | (((unsigned long)(tex6)) << CP_VCD_REG_HI_TEX6_SHIFT);\
+}
+#define CP_VCD_REG_HI_TEX7_SIZE 2
+#define CP_VCD_REG_HI_TEX7_SHIFT    14
+#define CP_VCD_REG_HI_TEX7_MASK 0x0000c000
+#define CP_VCD_REG_HI_GET_TEX7(cp_vcd_reg_hi) \
+    ((((unsigned long)(cp_vcd_reg_hi)) & CP_VCD_REG_HI_TEX7_MASK) >> CP_VCD_REG_HI_TEX7_SHIFT)
+#define CP_VCD_REG_HI_SET_TEX7(cp_vcd_reg_hi, tex7) { \
+    FDL_ASSERT(!((tex7) & ~((1 << CP_VCD_REG_HI_TEX7_SIZE)-1))); \
+    cp_vcd_reg_hi = (((unsigned long)(cp_vcd_reg_hi)) & ~CP_VCD_REG_HI_TEX7_MASK) | (((unsigned long)(tex7)) << CP_VCD_REG_HI_TEX7_SHIFT);\
+}
+#define CP_VCD_REG_HI_TOTAL_SIZE    16
+#define CP_VCD_REG_HI(tex0, tex1, tex2, tex3, tex4, tex5, tex6, tex7) \
+    ((((unsigned long)(tex0)) << CP_VCD_REG_HI_TEX0_SHIFT) | \
+    (((unsigned long)(tex1)) << CP_VCD_REG_HI_TEX1_SHIFT) | \
+    (((unsigned long)(tex2)) << CP_VCD_REG_HI_TEX2_SHIFT) | \
+    (((unsigned long)(tex3)) << CP_VCD_REG_HI_TEX3_SHIFT) | \
+    (((unsigned long)(tex4)) << CP_VCD_REG_HI_TEX4_SHIFT) | \
+    (((unsigned long)(tex5)) << CP_VCD_REG_HI_TEX5_SHIFT) | \
+    (((unsigned long)(tex6)) << CP_VCD_REG_HI_TEX6_SHIFT) | \
+    (((unsigned long)(tex7)) << CP_VCD_REG_HI_TEX7_SHIFT))
+
+/*
+*  cp_vat_table value
+*/
+#define CP_NUM_VATS 0x08
+
+/*
+*  cp_vat_reg_a struct
+*/
+#define CP_VAT_REG_A_POSCNT_SIZE    1
+#define CP_VAT_REG_A_POSCNT_SHIFT   0
+#define CP_VAT_REG_A_POSCNT_MASK    0x00000001
+#define CP_VAT_REG_A_GET_POSCNT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_POSCNT_MASK) >> CP_VAT_REG_A_POSCNT_SHIFT)
+#define CP_VAT_REG_A_SET_POSCNT(cp_vat_reg_a, posCnt) { \
+    FDL_ASSERT(!((posCnt) & ~((1 << CP_VAT_REG_A_POSCNT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_POSCNT_MASK) | (((unsigned long)(posCnt)) << CP_VAT_REG_A_POSCNT_SHIFT);\
+}
+#define CP_VAT_REG_A_POSFMT_SIZE    3
+#define CP_VAT_REG_A_POSFMT_SHIFT   1
+#define CP_VAT_REG_A_POSFMT_MASK    0x0000000e
+#define CP_VAT_REG_A_GET_POSFMT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_POSFMT_MASK) >> CP_VAT_REG_A_POSFMT_SHIFT)
+#define CP_VAT_REG_A_SET_POSFMT(cp_vat_reg_a, posFmt) { \
+    FDL_ASSERT(!((posFmt) & ~((1 << CP_VAT_REG_A_POSFMT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_POSFMT_MASK) | (((unsigned long)(posFmt)) << CP_VAT_REG_A_POSFMT_SHIFT);\
+}
+#define CP_VAT_REG_A_POSSHFT_SIZE   5
+#define CP_VAT_REG_A_POSSHFT_SHIFT  4
+#define CP_VAT_REG_A_POSSHFT_MASK   0x000001f0
+#define CP_VAT_REG_A_GET_POSSHFT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_POSSHFT_MASK) >> CP_VAT_REG_A_POSSHFT_SHIFT)
+#define CP_VAT_REG_A_SET_POSSHFT(cp_vat_reg_a, posShft) { \
+    FDL_ASSERT(!((posShft) & ~((1 << CP_VAT_REG_A_POSSHFT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_POSSHFT_MASK) | (((unsigned long)(posShft)) << CP_VAT_REG_A_POSSHFT_SHIFT);\
+}
+#define CP_VAT_REG_A_NRMCNT_SIZE    1
+#define CP_VAT_REG_A_NRMCNT_SHIFT   9
+#define CP_VAT_REG_A_NRMCNT_MASK    0x00000200
+#define CP_VAT_REG_A_GET_NRMCNT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_NRMCNT_MASK) >> CP_VAT_REG_A_NRMCNT_SHIFT)
+#define CP_VAT_REG_A_SET_NRMCNT(cp_vat_reg_a, nrmCnt) { \
+    FDL_ASSERT(!((nrmCnt) & ~((1 << CP_VAT_REG_A_NRMCNT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_NRMCNT_MASK) | (((unsigned long)(nrmCnt)) << CP_VAT_REG_A_NRMCNT_SHIFT);\
+}
+#define CP_VAT_REG_A_NRMFMT_SIZE    3
+#define CP_VAT_REG_A_NRMFMT_SHIFT   10
+#define CP_VAT_REG_A_NRMFMT_MASK    0x00001c00
+#define CP_VAT_REG_A_GET_NRMFMT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_NRMFMT_MASK) >> CP_VAT_REG_A_NRMFMT_SHIFT)
+#define CP_VAT_REG_A_SET_NRMFMT(cp_vat_reg_a, nrmFmt) { \
+    FDL_ASSERT(!((nrmFmt) & ~((1 << CP_VAT_REG_A_NRMFMT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_NRMFMT_MASK) | (((unsigned long)(nrmFmt)) << CP_VAT_REG_A_NRMFMT_SHIFT);\
+}
+#define CP_VAT_REG_A_COL0CNT_SIZE   1
+#define CP_VAT_REG_A_COL0CNT_SHIFT  13
+#define CP_VAT_REG_A_COL0CNT_MASK   0x00002000
+#define CP_VAT_REG_A_GET_COL0CNT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_COL0CNT_MASK) >> CP_VAT_REG_A_COL0CNT_SHIFT)
+#define CP_VAT_REG_A_SET_COL0CNT(cp_vat_reg_a, Col0Cnt) { \
+    FDL_ASSERT(!((Col0Cnt) & ~((1 << CP_VAT_REG_A_COL0CNT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_COL0CNT_MASK) | (((unsigned long)(Col0Cnt)) << CP_VAT_REG_A_COL0CNT_SHIFT);\
+}
+#define CP_VAT_REG_A_COL0FMT_SIZE   3
+#define CP_VAT_REG_A_COL0FMT_SHIFT  14
+#define CP_VAT_REG_A_COL0FMT_MASK   0x0001c000
+#define CP_VAT_REG_A_GET_COL0FMT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_COL0FMT_MASK) >> CP_VAT_REG_A_COL0FMT_SHIFT)
+#define CP_VAT_REG_A_SET_COL0FMT(cp_vat_reg_a, Col0Fmt) { \
+    FDL_ASSERT(!((Col0Fmt) & ~((1 << CP_VAT_REG_A_COL0FMT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_COL0FMT_MASK) | (((unsigned long)(Col0Fmt)) << CP_VAT_REG_A_COL0FMT_SHIFT);\
+}
+#define CP_VAT_REG_A_COL1CNT_SIZE   1
+#define CP_VAT_REG_A_COL1CNT_SHIFT  17
+#define CP_VAT_REG_A_COL1CNT_MASK   0x00020000
+#define CP_VAT_REG_A_GET_COL1CNT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_COL1CNT_MASK) >> CP_VAT_REG_A_COL1CNT_SHIFT)
+#define CP_VAT_REG_A_SET_COL1CNT(cp_vat_reg_a, Col1Cnt) { \
+    FDL_ASSERT(!((Col1Cnt) & ~((1 << CP_VAT_REG_A_COL1CNT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_COL1CNT_MASK) | (((unsigned long)(Col1Cnt)) << CP_VAT_REG_A_COL1CNT_SHIFT);\
+}
+#define CP_VAT_REG_A_COL1FMT_SIZE   3
+#define CP_VAT_REG_A_COL1FMT_SHIFT  18
+#define CP_VAT_REG_A_COL1FMT_MASK   0x001c0000
+#define CP_VAT_REG_A_GET_COL1FMT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_COL1FMT_MASK) >> CP_VAT_REG_A_COL1FMT_SHIFT)
+#define CP_VAT_REG_A_SET_COL1FMT(cp_vat_reg_a, Col1Fmt) { \
+    FDL_ASSERT(!((Col1Fmt) & ~((1 << CP_VAT_REG_A_COL1FMT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_COL1FMT_MASK) | (((unsigned long)(Col1Fmt)) << CP_VAT_REG_A_COL1FMT_SHIFT);\
+}
+#define CP_VAT_REG_A_TEX0CNT_SIZE   1
+#define CP_VAT_REG_A_TEX0CNT_SHIFT  21
+#define CP_VAT_REG_A_TEX0CNT_MASK   0x00200000
+#define CP_VAT_REG_A_GET_TEX0CNT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_TEX0CNT_MASK) >> CP_VAT_REG_A_TEX0CNT_SHIFT)
+#define CP_VAT_REG_A_SET_TEX0CNT(cp_vat_reg_a, tex0Cnt) { \
+    FDL_ASSERT(!((tex0Cnt) & ~((1 << CP_VAT_REG_A_TEX0CNT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_TEX0CNT_MASK) | (((unsigned long)(tex0Cnt)) << CP_VAT_REG_A_TEX0CNT_SHIFT);\
+}
+#define CP_VAT_REG_A_TEX0FMT_SIZE   3
+#define CP_VAT_REG_A_TEX0FMT_SHIFT  22
+#define CP_VAT_REG_A_TEX0FMT_MASK   0x01c00000
+#define CP_VAT_REG_A_GET_TEX0FMT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_TEX0FMT_MASK) >> CP_VAT_REG_A_TEX0FMT_SHIFT)
+#define CP_VAT_REG_A_SET_TEX0FMT(cp_vat_reg_a, tex0Fmt) { \
+    FDL_ASSERT(!((tex0Fmt) & ~((1 << CP_VAT_REG_A_TEX0FMT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_TEX0FMT_MASK) | (((unsigned long)(tex0Fmt)) << CP_VAT_REG_A_TEX0FMT_SHIFT);\
+}
+#define CP_VAT_REG_A_TEX0SHFT_SIZE  5
+#define CP_VAT_REG_A_TEX0SHFT_SHIFT 25
+#define CP_VAT_REG_A_TEX0SHFT_MASK  0x3e000000
+#define CP_VAT_REG_A_GET_TEX0SHFT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_TEX0SHFT_MASK) >> CP_VAT_REG_A_TEX0SHFT_SHIFT)
+#define CP_VAT_REG_A_SET_TEX0SHFT(cp_vat_reg_a, tex0Shft) { \
+    FDL_ASSERT(!((tex0Shft) & ~((1 << CP_VAT_REG_A_TEX0SHFT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_TEX0SHFT_MASK) | (((unsigned long)(tex0Shft)) << CP_VAT_REG_A_TEX0SHFT_SHIFT);\
+}
+#define CP_VAT_REG_A_BYTEDEQUANT_SIZE   1
+#define CP_VAT_REG_A_BYTEDEQUANT_SHIFT  30
+#define CP_VAT_REG_A_BYTEDEQUANT_MASK   0x40000000
+#define CP_VAT_REG_A_GET_BYTEDEQUANT(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_BYTEDEQUANT_MASK) >> CP_VAT_REG_A_BYTEDEQUANT_SHIFT)
+#define CP_VAT_REG_A_SET_BYTEDEQUANT(cp_vat_reg_a, byteDequant) { \
+    FDL_ASSERT(!((byteDequant) & ~((1 << CP_VAT_REG_A_BYTEDEQUANT_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_BYTEDEQUANT_MASK) | (((unsigned long)(byteDequant)) << CP_VAT_REG_A_BYTEDEQUANT_SHIFT);\
+}
+#define CP_VAT_REG_A_NORMALINDEX3_SIZE  1
+#define CP_VAT_REG_A_NORMALINDEX3_SHIFT 31
+#define CP_VAT_REG_A_NORMALINDEX3_MASK  0x80000000
+#define CP_VAT_REG_A_GET_NORMALINDEX3(cp_vat_reg_a) \
+    ((((unsigned long)(cp_vat_reg_a)) & CP_VAT_REG_A_NORMALINDEX3_MASK) >> CP_VAT_REG_A_NORMALINDEX3_SHIFT)
+#define CP_VAT_REG_A_SET_NORMALINDEX3(cp_vat_reg_a, normalIndex3) { \
+    FDL_ASSERT(!((normalIndex3) & ~((1 << CP_VAT_REG_A_NORMALINDEX3_SIZE)-1))); \
+    cp_vat_reg_a = (((unsigned long)(cp_vat_reg_a)) & ~CP_VAT_REG_A_NORMALINDEX3_MASK) | (((unsigned long)(normalIndex3)) << CP_VAT_REG_A_NORMALINDEX3_SHIFT);\
+}
+#define CP_VAT_REG_A_TOTAL_SIZE 32
+#define CP_VAT_REG_A(posCnt, posFmt, posShft, nrmCnt, nrmFmt, Col0Cnt, Col0Fmt, Col1Cnt, Col1Fmt, tex0Cnt, tex0Fmt, tex0Shft, byteDequant, normalIndex3) \
+    ((((unsigned long)(posCnt)) << CP_VAT_REG_A_POSCNT_SHIFT) | \
+    (((unsigned long)(posFmt)) << CP_VAT_REG_A_POSFMT_SHIFT) | \
+    (((unsigned long)(posShft)) << CP_VAT_REG_A_POSSHFT_SHIFT) | \
+    (((unsigned long)(nrmCnt)) << CP_VAT_REG_A_NRMCNT_SHIFT) | \
+    (((unsigned long)(nrmFmt)) << CP_VAT_REG_A_NRMFMT_SHIFT) | \
+    (((unsigned long)(Col0Cnt)) << CP_VAT_REG_A_COL0CNT_SHIFT) | \
+    (((unsigned long)(Col0Fmt)) << CP_VAT_REG_A_COL0FMT_SHIFT) | \
+    (((unsigned long)(Col1Cnt)) << CP_VAT_REG_A_COL1CNT_SHIFT) | \
+    (((unsigned long)(Col1Fmt)) << CP_VAT_REG_A_COL1FMT_SHIFT) | \
+    (((unsigned long)(tex0Cnt)) << CP_VAT_REG_A_TEX0CNT_SHIFT) | \
+    (((unsigned long)(tex0Fmt)) << CP_VAT_REG_A_TEX0FMT_SHIFT) | \
+    (((unsigned long)(tex0Shft)) << CP_VAT_REG_A_TEX0SHFT_SHIFT) | \
+    (((unsigned long)(byteDequant)) << CP_VAT_REG_A_BYTEDEQUANT_SHIFT) | \
+    (((unsigned long)(normalIndex3)) << CP_VAT_REG_A_NORMALINDEX3_SHIFT))
+
+/*
+*  cp_vat_reg_b struct
+*/
+#define CP_VAT_REG_B_TEX1CNT_SIZE   1
+#define CP_VAT_REG_B_TEX1CNT_SHIFT  0
+#define CP_VAT_REG_B_TEX1CNT_MASK   0x00000001
+#define CP_VAT_REG_B_GET_TEX1CNT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX1CNT_MASK) >> CP_VAT_REG_B_TEX1CNT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX1CNT(cp_vat_reg_b, tex1Cnt) { \
+    FDL_ASSERT(!((tex1Cnt) & ~((1 << CP_VAT_REG_B_TEX1CNT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX1CNT_MASK) | (((unsigned long)(tex1Cnt)) << CP_VAT_REG_B_TEX1CNT_SHIFT);\
+}
+#define CP_VAT_REG_B_TEX1FMT_SIZE   3
+#define CP_VAT_REG_B_TEX1FMT_SHIFT  1
+#define CP_VAT_REG_B_TEX1FMT_MASK   0x0000000e
+#define CP_VAT_REG_B_GET_TEX1FMT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX1FMT_MASK) >> CP_VAT_REG_B_TEX1FMT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX1FMT(cp_vat_reg_b, tex1Fmt) { \
+    FDL_ASSERT(!((tex1Fmt) & ~((1 << CP_VAT_REG_B_TEX1FMT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX1FMT_MASK) | (((unsigned long)(tex1Fmt)) << CP_VAT_REG_B_TEX1FMT_SHIFT);\
+}
+#define CP_VAT_REG_B_TEX1SHFT_SIZE  5
+#define CP_VAT_REG_B_TEX1SHFT_SHIFT 4
+#define CP_VAT_REG_B_TEX1SHFT_MASK  0x000001f0
+#define CP_VAT_REG_B_GET_TEX1SHFT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX1SHFT_MASK) >> CP_VAT_REG_B_TEX1SHFT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX1SHFT(cp_vat_reg_b, tex1Shft) { \
+    FDL_ASSERT(!((tex1Shft) & ~((1 << CP_VAT_REG_B_TEX1SHFT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX1SHFT_MASK) | (((unsigned long)(tex1Shft)) << CP_VAT_REG_B_TEX1SHFT_SHIFT);\
+}
+#define CP_VAT_REG_B_TEX2CNT_SIZE   1
+#define CP_VAT_REG_B_TEX2CNT_SHIFT  9
+#define CP_VAT_REG_B_TEX2CNT_MASK   0x00000200
+#define CP_VAT_REG_B_GET_TEX2CNT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX2CNT_MASK) >> CP_VAT_REG_B_TEX2CNT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX2CNT(cp_vat_reg_b, tex2Cnt) { \
+    FDL_ASSERT(!((tex2Cnt) & ~((1 << CP_VAT_REG_B_TEX2CNT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX2CNT_MASK) | (((unsigned long)(tex2Cnt)) << CP_VAT_REG_B_TEX2CNT_SHIFT);\
+}
+#define CP_VAT_REG_B_TEX2FMT_SIZE   3
+#define CP_VAT_REG_B_TEX2FMT_SHIFT  10
+#define CP_VAT_REG_B_TEX2FMT_MASK   0x00001c00
+#define CP_VAT_REG_B_GET_TEX2FMT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX2FMT_MASK) >> CP_VAT_REG_B_TEX2FMT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX2FMT(cp_vat_reg_b, tex2Fmt) { \
+    FDL_ASSERT(!((tex2Fmt) & ~((1 << CP_VAT_REG_B_TEX2FMT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX2FMT_MASK) | (((unsigned long)(tex2Fmt)) << CP_VAT_REG_B_TEX2FMT_SHIFT);\
+}
+#define CP_VAT_REG_B_TEX2SHFT_SIZE  5
+#define CP_VAT_REG_B_TEX2SHFT_SHIFT 13
+#define CP_VAT_REG_B_TEX2SHFT_MASK  0x0003e000
+#define CP_VAT_REG_B_GET_TEX2SHFT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX2SHFT_MASK) >> CP_VAT_REG_B_TEX2SHFT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX2SHFT(cp_vat_reg_b, tex2Shft) { \
+    FDL_ASSERT(!((tex2Shft) & ~((1 << CP_VAT_REG_B_TEX2SHFT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX2SHFT_MASK) | (((unsigned long)(tex2Shft)) << CP_VAT_REG_B_TEX2SHFT_SHIFT);\
+}
+#define CP_VAT_REG_B_TEX3CNT_SIZE   1
+#define CP_VAT_REG_B_TEX3CNT_SHIFT  18
+#define CP_VAT_REG_B_TEX3CNT_MASK   0x00040000
+#define CP_VAT_REG_B_GET_TEX3CNT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX3CNT_MASK) >> CP_VAT_REG_B_TEX3CNT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX3CNT(cp_vat_reg_b, tex3Cnt) { \
+    FDL_ASSERT(!((tex3Cnt) & ~((1 << CP_VAT_REG_B_TEX3CNT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX3CNT_MASK) | (((unsigned long)(tex3Cnt)) << CP_VAT_REG_B_TEX3CNT_SHIFT);\
+}
+#define CP_VAT_REG_B_TEX3FMT_SIZE   3
+#define CP_VAT_REG_B_TEX3FMT_SHIFT  19
+#define CP_VAT_REG_B_TEX3FMT_MASK   0x00380000
+#define CP_VAT_REG_B_GET_TEX3FMT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX3FMT_MASK) >> CP_VAT_REG_B_TEX3FMT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX3FMT(cp_vat_reg_b, tex3Fmt) { \
+    FDL_ASSERT(!((tex3Fmt) & ~((1 << CP_VAT_REG_B_TEX3FMT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX3FMT_MASK) | (((unsigned long)(tex3Fmt)) << CP_VAT_REG_B_TEX3FMT_SHIFT);\
+}
+#define CP_VAT_REG_B_TEX3SHFT_SIZE  5
+#define CP_VAT_REG_B_TEX3SHFT_SHIFT 22
+#define CP_VAT_REG_B_TEX3SHFT_MASK  0x07c00000
+#define CP_VAT_REG_B_GET_TEX3SHFT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX3SHFT_MASK) >> CP_VAT_REG_B_TEX3SHFT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX3SHFT(cp_vat_reg_b, tex3Shft) { \
+    FDL_ASSERT(!((tex3Shft) & ~((1 << CP_VAT_REG_B_TEX3SHFT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX3SHFT_MASK) | (((unsigned long)(tex3Shft)) << CP_VAT_REG_B_TEX3SHFT_SHIFT);\
+}
+#define CP_VAT_REG_B_TEX4CNT_SIZE   1
+#define CP_VAT_REG_B_TEX4CNT_SHIFT  27
+#define CP_VAT_REG_B_TEX4CNT_MASK   0x08000000
+#define CP_VAT_REG_B_GET_TEX4CNT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX4CNT_MASK) >> CP_VAT_REG_B_TEX4CNT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX4CNT(cp_vat_reg_b, tex4Cnt) { \
+    FDL_ASSERT(!((tex4Cnt) & ~((1 << CP_VAT_REG_B_TEX4CNT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX4CNT_MASK) | (((unsigned long)(tex4Cnt)) << CP_VAT_REG_B_TEX4CNT_SHIFT);\
+}
+#define CP_VAT_REG_B_TEX4FMT_SIZE   3
+#define CP_VAT_REG_B_TEX4FMT_SHIFT  28
+#define CP_VAT_REG_B_TEX4FMT_MASK   0x70000000
+#define CP_VAT_REG_B_GET_TEX4FMT(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_TEX4FMT_MASK) >> CP_VAT_REG_B_TEX4FMT_SHIFT)
+#define CP_VAT_REG_B_SET_TEX4FMT(cp_vat_reg_b, tex4Fmt) { \
+    FDL_ASSERT(!((tex4Fmt) & ~((1 << CP_VAT_REG_B_TEX4FMT_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_TEX4FMT_MASK) | (((unsigned long)(tex4Fmt)) << CP_VAT_REG_B_TEX4FMT_SHIFT);\
+}
+#define CP_VAT_REG_B_VCACHE_ENHANCE_SIZE    1
+#define CP_VAT_REG_B_VCACHE_ENHANCE_SHIFT   31
+#define CP_VAT_REG_B_VCACHE_ENHANCE_MASK    0x80000000
+#define CP_VAT_REG_B_GET_VCACHE_ENHANCE(cp_vat_reg_b) \
+    ((((unsigned long)(cp_vat_reg_b)) & CP_VAT_REG_B_VCACHE_ENHANCE_MASK) >> CP_VAT_REG_B_VCACHE_ENHANCE_SHIFT)
+#define CP_VAT_REG_B_SET_VCACHE_ENHANCE(cp_vat_reg_b, vcache_enhance) { \
+    FDL_ASSERT(!((vcache_enhance) & ~((1 << CP_VAT_REG_B_VCACHE_ENHANCE_SIZE)-1))); \
+    cp_vat_reg_b = (((unsigned long)(cp_vat_reg_b)) & ~CP_VAT_REG_B_VCACHE_ENHANCE_MASK) | (((unsigned long)(vcache_enhance)) << CP_VAT_REG_B_VCACHE_ENHANCE_SHIFT);\
+}
+#define CP_VAT_REG_B_TOTAL_SIZE 32
+#define CP_VAT_REG_B(tex1Cnt, tex1Fmt, tex1Shft, tex2Cnt, tex2Fmt, tex2Shft, tex3Cnt, tex3Fmt, tex3Shft, tex4Cnt, tex4Fmt, vcache_enhance) \
+    ((((unsigned long)(tex1Cnt)) << CP_VAT_REG_B_TEX1CNT_SHIFT) | \
+    (((unsigned long)(tex1Fmt)) << CP_VAT_REG_B_TEX1FMT_SHIFT) | \
+    (((unsigned long)(tex1Shft)) << CP_VAT_REG_B_TEX1SHFT_SHIFT) | \
+    (((unsigned long)(tex2Cnt)) << CP_VAT_REG_B_TEX2CNT_SHIFT) | \
+    (((unsigned long)(tex2Fmt)) << CP_VAT_REG_B_TEX2FMT_SHIFT) | \
+    (((unsigned long)(tex2Shft)) << CP_VAT_REG_B_TEX2SHFT_SHIFT) | \
+    (((unsigned long)(tex3Cnt)) << CP_VAT_REG_B_TEX3CNT_SHIFT) | \
+    (((unsigned long)(tex3Fmt)) << CP_VAT_REG_B_TEX3FMT_SHIFT) | \
+    (((unsigned long)(tex3Shft)) << CP_VAT_REG_B_TEX3SHFT_SHIFT) | \
+    (((unsigned long)(tex4Cnt)) << CP_VAT_REG_B_TEX4CNT_SHIFT) | \
+    (((unsigned long)(tex4Fmt)) << CP_VAT_REG_B_TEX4FMT_SHIFT) | \
+    (((unsigned long)(vcache_enhance)) << CP_VAT_REG_B_VCACHE_ENHANCE_SHIFT))
+
+/*
+*  cp_vat_reg_c struct
+*/
+#define CP_VAT_REG_C_TEX4SHFT_SIZE  5
+#define CP_VAT_REG_C_TEX4SHFT_SHIFT 0
+#define CP_VAT_REG_C_TEX4SHFT_MASK  0x0000001f
+#define CP_VAT_REG_C_GET_TEX4SHFT(cp_vat_reg_c) \
+    ((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX4SHFT_MASK) >> CP_VAT_REG_C_TEX4SHFT_SHIFT)
+#define CP_VAT_REG_C_SET_TEX4SHFT(cp_vat_reg_c, tex4Shft) { \
+    FDL_ASSERT(!((tex4Shft) & ~((1 << CP_VAT_REG_C_TEX4SHFT_SIZE)-1))); \
+    cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX4SHFT_MASK) | (((unsigned long)(tex4Shft)) << CP_VAT_REG_C_TEX4SHFT_SHIFT);\
+}
+#define CP_VAT_REG_C_TEX5CNT_SIZE   1
+#define CP_VAT_REG_C_TEX5CNT_SHIFT  5
+#define CP_VAT_REG_C_TEX5CNT_MASK   0x00000020
+#define CP_VAT_REG_C_GET_TEX5CNT(cp_vat_reg_c) \
+    ((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX5CNT_MASK) >> CP_VAT_REG_C_TEX5CNT_SHIFT)
+#define CP_VAT_REG_C_SET_TEX5CNT(cp_vat_reg_c, tex5Cnt) { \
+    FDL_ASSERT(!((tex5Cnt) & ~((1 << CP_VAT_REG_C_TEX5CNT_SIZE)-1))); \
+    cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX5CNT_MASK) | (((unsigned long)(tex5Cnt)) << CP_VAT_REG_C_TEX5CNT_SHIFT);\
+}
+#define CP_VAT_REG_C_TEX5FMT_SIZE   3
+#define CP_VAT_REG_C_TEX5FMT_SHIFT  6
+#define CP_VAT_REG_C_TEX5FMT_MASK   0x000001c0
+#define CP_VAT_REG_C_GET_TEX5FMT(cp_vat_reg_c) \
+    ((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX5FMT_MASK) >> CP_VAT_REG_C_TEX5FMT_SHIFT)
+#define CP_VAT_REG_C_SET_TEX5FMT(cp_vat_reg_c, tex5Fmt) { \
+    FDL_ASSERT(!((tex5Fmt) & ~((1 << CP_VAT_REG_C_TEX5FMT_SIZE)-1))); \
+    cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX5FMT_MASK) | (((unsigned long)(tex5Fmt)) << CP_VAT_REG_C_TEX5FMT_SHIFT);\
+}
+#define CP_VAT_REG_C_TEX5SHFT_SIZE  5
+#define CP_VAT_REG_C_TEX5SHFT_SHIFT 9
+#define CP_VAT_REG_C_TEX5SHFT_MASK  0x00003e00
+#define CP_VAT_REG_C_GET_TEX5SHFT(cp_vat_reg_c) \
+    ((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX5SHFT_MASK) >> CP_VAT_REG_C_TEX5SHFT_SHIFT)
+#define CP_VAT_REG_C_SET_TEX5SHFT(cp_vat_reg_c, tex5Shft) { \
+    FDL_ASSERT(!((tex5Shft) & ~((1 << CP_VAT_REG_C_TEX5SHFT_SIZE)-1))); \
+    cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX5SHFT_MASK) | (((unsigned long)(tex5Shft)) << CP_VAT_REG_C_TEX5SHFT_SHIFT);\
+}
+#define CP_VAT_REG_C_TEX6CNT_SIZE   1
+#define CP_VAT_REG_C_TEX6CNT_SHIFT  14
+#define CP_VAT_REG_C_TEX6CNT_MASK   0x00004000
+#define CP_VAT_REG_C_GET_TEX6CNT(cp_vat_reg_c) \
+    ((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX6CNT_MASK) >> CP_VAT_REG_C_TEX6CNT_SHIFT)
+#define CP_VAT_REG_C_SET_TEX6CNT(cp_vat_reg_c, tex6Cnt) { \
+    FDL_ASSERT(!((tex6Cnt) & ~((1 << CP_VAT_REG_C_TEX6CNT_SIZE)-1))); \
+    cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX6CNT_MASK) | (((unsigned long)(tex6Cnt)) << CP_VAT_REG_C_TEX6CNT_SHIFT);\
+}
+#define CP_VAT_REG_C_TEX6FMT_SIZE   3
+#define CP_VAT_REG_C_TEX6FMT_SHIFT  15
+#define CP_VAT_REG_C_TEX6FMT_MASK   0x00038000
+#define CP_VAT_REG_C_GET_TEX6FMT(cp_vat_reg_c) \
+    ((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX6FMT_MASK) >> CP_VAT_REG_C_TEX6FMT_SHIFT)
+#define CP_VAT_REG_C_SET_TEX6FMT(cp_vat_reg_c, tex6Fmt) { \
+    FDL_ASSERT(!((tex6Fmt) & ~((1 << CP_VAT_REG_C_TEX6FMT_SIZE)-1))); \
+    cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX6FMT_MASK) | (((unsigned long)(tex6Fmt)) << CP_VAT_REG_C_TEX6FMT_SHIFT);\
+}
+#define CP_VAT_REG_C_TEX6SHFT_SIZE  5
+#define CP_VAT_REG_C_TEX6SHFT_SHIFT 18
+#define CP_VAT_REG_C_TEX6SHFT_MASK  0x007c0000
+#define CP_VAT_REG_C_GET_TEX6SHFT(cp_vat_reg_c) \
+    ((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX6SHFT_MASK) >> CP_VAT_REG_C_TEX6SHFT_SHIFT)
+#define CP_VAT_REG_C_SET_TEX6SHFT(cp_vat_reg_c, tex6Shft) { \
+    FDL_ASSERT(!((tex6Shft) & ~((1 << CP_VAT_REG_C_TEX6SHFT_SIZE)-1))); \
+    cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX6SHFT_MASK) | (((unsigned long)(tex6Shft)) << CP_VAT_REG_C_TEX6SHFT_SHIFT);\
+}
+#define CP_VAT_REG_C_TEX7CNT_SIZE   1
+#define CP_VAT_REG_C_TEX7CNT_SHIFT  23
+#define CP_VAT_REG_C_TEX7CNT_MASK   0x00800000
+#define CP_VAT_REG_C_GET_TEX7CNT(cp_vat_reg_c) \
+    ((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX7CNT_MASK) >> CP_VAT_REG_C_TEX7CNT_SHIFT)
+#define CP_VAT_REG_C_SET_TEX7CNT(cp_vat_reg_c, tex7Cnt) { \
+    FDL_ASSERT(!((tex7Cnt) & ~((1 << CP_VAT_REG_C_TEX7CNT_SIZE)-1))); \
+    cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX7CNT_MASK) | (((unsigned long)(tex7Cnt)) << CP_VAT_REG_C_TEX7CNT_SHIFT);\
+}
+#define CP_VAT_REG_C_TEX7FMT_SIZE   3
+#define CP_VAT_REG_C_TEX7FMT_SHIFT  24
+#define CP_VAT_REG_C_TEX7FMT_MASK   0x07000000
+#define CP_VAT_REG_C_GET_TEX7FMT(cp_vat_reg_c) \
+    ((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX7FMT_MASK) >> CP_VAT_REG_C_TEX7FMT_SHIFT)
+#define CP_VAT_REG_C_SET_TEX7FMT(cp_vat_reg_c, tex7Fmt) { \
+    FDL_ASSERT(!((tex7Fmt) & ~((1 << CP_VAT_REG_C_TEX7FMT_SIZE)-1))); \
+    cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX7FMT_MASK) | (((unsigned long)(tex7Fmt)) << CP_VAT_REG_C_TEX7FMT_SHIFT);\
+}
+#define CP_VAT_REG_C_TEX7SHFT_SIZE  5
+#define CP_VAT_REG_C_TEX7SHFT_SHIFT 27
+#define CP_VAT_REG_C_TEX7SHFT_MASK  0xf8000000
+#define CP_VAT_REG_C_GET_TEX7SHFT(cp_vat_reg_c) \
+    ((((unsigned long)(cp_vat_reg_c)) & CP_VAT_REG_C_TEX7SHFT_MASK) >> CP_VAT_REG_C_TEX7SHFT_SHIFT)
+#define CP_VAT_REG_C_SET_TEX7SHFT(cp_vat_reg_c, tex7Shft) { \
+    FDL_ASSERT(!((tex7Shft) & ~((1 << CP_VAT_REG_C_TEX7SHFT_SIZE)-1))); \
+    cp_vat_reg_c = (((unsigned long)(cp_vat_reg_c)) & ~CP_VAT_REG_C_TEX7SHFT_MASK) | (((unsigned long)(tex7Shft)) << CP_VAT_REG_C_TEX7SHFT_SHIFT);\
+}
+#define CP_VAT_REG_C_TOTAL_SIZE 32
+#define CP_VAT_REG_C(tex4Shft, tex5Cnt, tex5Fmt, tex5Shft, tex6Cnt, tex6Fmt, tex6Shft, tex7Cnt, tex7Fmt, tex7Shft) \
+    ((((unsigned long)(tex4Shft)) << CP_VAT_REG_C_TEX4SHFT_SHIFT) | \
+    (((unsigned long)(tex5Cnt)) << CP_VAT_REG_C_TEX5CNT_SHIFT) | \
+    (((unsigned long)(tex5Fmt)) << CP_VAT_REG_C_TEX5FMT_SHIFT) | \
+    (((unsigned long)(tex5Shft)) << CP_VAT_REG_C_TEX5SHFT_SHIFT) | \
+    (((unsigned long)(tex6Cnt)) << CP_VAT_REG_C_TEX6CNT_SHIFT) | \
+    (((unsigned long)(tex6Fmt)) << CP_VAT_REG_C_TEX6FMT_SHIFT) | \
+    (((unsigned long)(tex6Shft)) << CP_VAT_REG_C_TEX6SHFT_SHIFT) | \
+    (((unsigned long)(tex7Cnt)) << CP_VAT_REG_C_TEX7CNT_SHIFT) | \
+    (((unsigned long)(tex7Fmt)) << CP_VAT_REG_C_TEX7FMT_SHIFT) | \
+    (((unsigned long)(tex7Shft)) << CP_VAT_REG_C_TEX7SHFT_SHIFT))
+
+/*
+*  cp_matidx_reg_a struct
+*/
+#define CP_MATIDX_REG_A_POSIDX_SIZE 6
+#define CP_MATIDX_REG_A_POSIDX_SHIFT    0
+#define CP_MATIDX_REG_A_POSIDX_MASK 0x0000003f
+#define CP_MATIDX_REG_A_GET_POSIDX(cp_matidx_reg_a) \
+    ((((unsigned long)(cp_matidx_reg_a)) & CP_MATIDX_REG_A_POSIDX_MASK) >> CP_MATIDX_REG_A_POSIDX_SHIFT)
+#define CP_MATIDX_REG_A_SET_POSIDX(cp_matidx_reg_a, posIdx) { \
+    FDL_ASSERT(!((posIdx) & ~((1 << CP_MATIDX_REG_A_POSIDX_SIZE)-1))); \
+    cp_matidx_reg_a = (((unsigned long)(cp_matidx_reg_a)) & ~CP_MATIDX_REG_A_POSIDX_MASK) | (((unsigned long)(posIdx)) << CP_MATIDX_REG_A_POSIDX_SHIFT);\
+}
+#define CP_MATIDX_REG_A_TEX0IDX_SIZE    6
+#define CP_MATIDX_REG_A_TEX0IDX_SHIFT   6
+#define CP_MATIDX_REG_A_TEX0IDX_MASK    0x00000fc0
+#define CP_MATIDX_REG_A_GET_TEX0IDX(cp_matidx_reg_a) \
+    ((((unsigned long)(cp_matidx_reg_a)) & CP_MATIDX_REG_A_TEX0IDX_MASK) >> CP_MATIDX_REG_A_TEX0IDX_SHIFT)
+#define CP_MATIDX_REG_A_SET_TEX0IDX(cp_matidx_reg_a, tex0Idx) { \
+    FDL_ASSERT(!((tex0Idx) & ~((1 << CP_MATIDX_REG_A_TEX0IDX_SIZE)-1))); \
+    cp_matidx_reg_a = (((unsigned long)(cp_matidx_reg_a)) & ~CP_MATIDX_REG_A_TEX0IDX_MASK) | (((unsigned long)(tex0Idx)) << CP_MATIDX_REG_A_TEX0IDX_SHIFT);\
+}
+#define CP_MATIDX_REG_A_TEX1IDX_SIZE    6
+#define CP_MATIDX_REG_A_TEX1IDX_SHIFT   12
+#define CP_MATIDX_REG_A_TEX1IDX_MASK    0x0003f000
+#define CP_MATIDX_REG_A_GET_TEX1IDX(cp_matidx_reg_a) \
+    ((((unsigned long)(cp_matidx_reg_a)) & CP_MATIDX_REG_A_TEX1IDX_MASK) >> CP_MATIDX_REG_A_TEX1IDX_SHIFT)
+#define CP_MATIDX_REG_A_SET_TEX1IDX(cp_matidx_reg_a, tex1Idx) { \
+    FDL_ASSERT(!((tex1Idx) & ~((1 << CP_MATIDX_REG_A_TEX1IDX_SIZE)-1))); \
+    cp_matidx_reg_a = (((unsigned long)(cp_matidx_reg_a)) & ~CP_MATIDX_REG_A_TEX1IDX_MASK) | (((unsigned long)(tex1Idx)) << CP_MATIDX_REG_A_TEX1IDX_SHIFT);\
+}
+#define CP_MATIDX_REG_A_TEX2IDX_SIZE    6
+#define CP_MATIDX_REG_A_TEX2IDX_SHIFT   18
+#define CP_MATIDX_REG_A_TEX2IDX_MASK    0x00fc0000
+#define CP_MATIDX_REG_A_GET_TEX2IDX(cp_matidx_reg_a) \
+    ((((unsigned long)(cp_matidx_reg_a)) & CP_MATIDX_REG_A_TEX2IDX_MASK) >> CP_MATIDX_REG_A_TEX2IDX_SHIFT)
+#define CP_MATIDX_REG_A_SET_TEX2IDX(cp_matidx_reg_a, tex2Idx) { \
+    FDL_ASSERT(!((tex2Idx) & ~((1 << CP_MATIDX_REG_A_TEX2IDX_SIZE)-1))); \
+    cp_matidx_reg_a = (((unsigned long)(cp_matidx_reg_a)) & ~CP_MATIDX_REG_A_TEX2IDX_MASK) | (((unsigned long)(tex2Idx)) << CP_MATIDX_REG_A_TEX2IDX_SHIFT);\
+}
+#define CP_MATIDX_REG_A_TEX3IDX_SIZE    6
+#define CP_MATIDX_REG_A_TEX3IDX_SHIFT   24
+#define CP_MATIDX_REG_A_TEX3IDX_MASK    0x3f000000
+#define CP_MATIDX_REG_A_GET_TEX3IDX(cp_matidx_reg_a) \
+    ((((unsigned long)(cp_matidx_reg_a)) & CP_MATIDX_REG_A_TEX3IDX_MASK) >> CP_MATIDX_REG_A_TEX3IDX_SHIFT)
+#define CP_MATIDX_REG_A_SET_TEX3IDX(cp_matidx_reg_a, tex3Idx) { \
+    FDL_ASSERT(!((tex3Idx) & ~((1 << CP_MATIDX_REG_A_TEX3IDX_SIZE)-1))); \
+    cp_matidx_reg_a = (((unsigned long)(cp_matidx_reg_a)) & ~CP_MATIDX_REG_A_TEX3IDX_MASK) | (((unsigned long)(tex3Idx)) << CP_MATIDX_REG_A_TEX3IDX_SHIFT);\
+}
+#define CP_MATIDX_REG_A_TOTAL_SIZE  30
+#define CP_MATIDX_REG_A(posIdx, tex0Idx, tex1Idx, tex2Idx, tex3Idx) \
+    ((((unsigned long)(posIdx)) << CP_MATIDX_REG_A_POSIDX_SHIFT) | \
+    (((unsigned long)(tex0Idx)) << CP_MATIDX_REG_A_TEX0IDX_SHIFT) | \
+    (((unsigned long)(tex1Idx)) << CP_MATIDX_REG_A_TEX1IDX_SHIFT) | \
+    (((unsigned long)(tex2Idx)) << CP_MATIDX_REG_A_TEX2IDX_SHIFT) | \
+    (((unsigned long)(tex3Idx)) << CP_MATIDX_REG_A_TEX3IDX_SHIFT))
+
+/*
+*  cp_matidx_reg_b struct
+*/
+#define CP_MATIDX_REG_B_TEX4IDX_SIZE    6
+#define CP_MATIDX_REG_B_TEX4IDX_SHIFT   0
+#define CP_MATIDX_REG_B_TEX4IDX_MASK    0x0000003f
+#define CP_MATIDX_REG_B_GET_TEX4IDX(cp_matidx_reg_b) \
+    ((((unsigned long)(cp_matidx_reg_b)) & CP_MATIDX_REG_B_TEX4IDX_MASK) >> CP_MATIDX_REG_B_TEX4IDX_SHIFT)
+#define CP_MATIDX_REG_B_SET_TEX4IDX(cp_matidx_reg_b, tex4Idx) { \
+    FDL_ASSERT(!((tex4Idx) & ~((1 << CP_MATIDX_REG_B_TEX4IDX_SIZE)-1))); \
+    cp_matidx_reg_b = (((unsigned long)(cp_matidx_reg_b)) & ~CP_MATIDX_REG_B_TEX4IDX_MASK) | (((unsigned long)(tex4Idx)) << CP_MATIDX_REG_B_TEX4IDX_SHIFT);\
+}
+#define CP_MATIDX_REG_B_TEX5IDX_SIZE    6
+#define CP_MATIDX_REG_B_TEX5IDX_SHIFT   6
+#define CP_MATIDX_REG_B_TEX5IDX_MASK    0x00000fc0
+#define CP_MATIDX_REG_B_GET_TEX5IDX(cp_matidx_reg_b) \
+    ((((unsigned long)(cp_matidx_reg_b)) & CP_MATIDX_REG_B_TEX5IDX_MASK) >> CP_MATIDX_REG_B_TEX5IDX_SHIFT)
+#define CP_MATIDX_REG_B_SET_TEX5IDX(cp_matidx_reg_b, tex5Idx) { \
+    FDL_ASSERT(!((tex5Idx) & ~((1 << CP_MATIDX_REG_B_TEX5IDX_SIZE)-1))); \
+    cp_matidx_reg_b = (((unsigned long)(cp_matidx_reg_b)) & ~CP_MATIDX_REG_B_TEX5IDX_MASK) | (((unsigned long)(tex5Idx)) << CP_MATIDX_REG_B_TEX5IDX_SHIFT);\
+}
+#define CP_MATIDX_REG_B_TEX6IDX_SIZE    6
+#define CP_MATIDX_REG_B_TEX6IDX_SHIFT   12
+#define CP_MATIDX_REG_B_TEX6IDX_MASK    0x0003f000
+#define CP_MATIDX_REG_B_GET_TEX6IDX(cp_matidx_reg_b) \
+    ((((unsigned long)(cp_matidx_reg_b)) & CP_MATIDX_REG_B_TEX6IDX_MASK) >> CP_MATIDX_REG_B_TEX6IDX_SHIFT)
+#define CP_MATIDX_REG_B_SET_TEX6IDX(cp_matidx_reg_b, tex6Idx) { \
+    FDL_ASSERT(!((tex6Idx) & ~((1 << CP_MATIDX_REG_B_TEX6IDX_SIZE)-1))); \
+    cp_matidx_reg_b = (((unsigned long)(cp_matidx_reg_b)) & ~CP_MATIDX_REG_B_TEX6IDX_MASK) | (((unsigned long)(tex6Idx)) << CP_MATIDX_REG_B_TEX6IDX_SHIFT);\
+}
+#define CP_MATIDX_REG_B_TEX7IDX_SIZE    6
+#define CP_MATIDX_REG_B_TEX7IDX_SHIFT   18
+#define CP_MATIDX_REG_B_TEX7IDX_MASK    0x00fc0000
+#define CP_MATIDX_REG_B_GET_TEX7IDX(cp_matidx_reg_b) \
+    ((((unsigned long)(cp_matidx_reg_b)) & CP_MATIDX_REG_B_TEX7IDX_MASK) >> CP_MATIDX_REG_B_TEX7IDX_SHIFT)
+#define CP_MATIDX_REG_B_SET_TEX7IDX(cp_matidx_reg_b, tex7Idx) { \
+    FDL_ASSERT(!((tex7Idx) & ~((1 << CP_MATIDX_REG_B_TEX7IDX_SIZE)-1))); \
+    cp_matidx_reg_b = (((unsigned long)(cp_matidx_reg_b)) & ~CP_MATIDX_REG_B_TEX7IDX_MASK) | (((unsigned long)(tex7Idx)) << CP_MATIDX_REG_B_TEX7IDX_SHIFT);\
+}
+#define CP_MATIDX_REG_B_TOTAL_SIZE  24
+#define CP_MATIDX_REG_B(tex4Idx, tex5Idx, tex6Idx, tex7Idx) \
+    ((((unsigned long)(tex4Idx)) << CP_MATIDX_REG_B_TEX4IDX_SHIFT) | \
+    (((unsigned long)(tex5Idx)) << CP_MATIDX_REG_B_TEX5IDX_SHIFT) | \
+    (((unsigned long)(tex6Idx)) << CP_MATIDX_REG_B_TEX6IDX_SHIFT) | \
+    (((unsigned long)(tex7Idx)) << CP_MATIDX_REG_B_TEX7IDX_SHIFT))
+
+/*
+*  cp_array_base_reg struct
+*/
+#define CP_ARRAY_BASE_REG_BASE_SIZE 29
+#define CP_ARRAY_BASE_REG_BASE_SHIFT    0
+#define CP_ARRAY_BASE_REG_BASE_MASK 0x1fffffff
+#define CP_ARRAY_BASE_REG_GET_BASE(cp_array_base_reg) \
+    ((((unsigned long)(cp_array_base_reg)) & CP_ARRAY_BASE_REG_BASE_MASK) >> CP_ARRAY_BASE_REG_BASE_SHIFT)
+#define CP_ARRAY_BASE_REG_SET_BASE(cp_array_base_reg, base) { \
+    FDL_ASSERT(!((base) & ~((1 << CP_ARRAY_BASE_REG_BASE_SIZE)-1))); \
+    cp_array_base_reg = (((unsigned long)(cp_array_base_reg)) & ~CP_ARRAY_BASE_REG_BASE_MASK) | (((unsigned long)(base)) << CP_ARRAY_BASE_REG_BASE_SHIFT);\
+}
+#define CP_ARRAY_BASE_REG_PAD0_SIZE 3
+#define CP_ARRAY_BASE_REG_PAD0_SHIFT    29
+#define CP_ARRAY_BASE_REG_PAD0_MASK 0xe0000000
+#define CP_ARRAY_BASE_REG_GET_PAD0(cp_array_base_reg) \
+    ((((unsigned long)(cp_array_base_reg)) & CP_ARRAY_BASE_REG_PAD0_MASK) >> CP_ARRAY_BASE_REG_PAD0_SHIFT)
+#define CP_ARRAY_BASE_REG_SET_PAD0(cp_array_base_reg, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_ARRAY_BASE_REG_PAD0_SIZE)-1))); \
+    cp_array_base_reg = (((unsigned long)(cp_array_base_reg)) & ~CP_ARRAY_BASE_REG_PAD0_MASK) | (((unsigned long)(pad0)) << CP_ARRAY_BASE_REG_PAD0_SHIFT);\
+}
+#define CP_ARRAY_BASE_REG_TOTAL_SIZE    32
+#define CP_ARRAY_BASE_REG(base) \
+    ((((unsigned long)(base)) << CP_ARRAY_BASE_REG_BASE_SHIFT))
+
+/*
+*  cp_array_stride_reg struct
+*/
+#define CP_ARRAY_STRIDE_REG_STRIDE_SIZE 8
+#define CP_ARRAY_STRIDE_REG_STRIDE_SHIFT    0
+#define CP_ARRAY_STRIDE_REG_STRIDE_MASK 0x000000ff
+#define CP_ARRAY_STRIDE_REG_GET_STRIDE(cp_array_stride_reg) \
+    ((((unsigned long)(cp_array_stride_reg)) & CP_ARRAY_STRIDE_REG_STRIDE_MASK) >> CP_ARRAY_STRIDE_REG_STRIDE_SHIFT)
+#define CP_ARRAY_STRIDE_REG_SET_STRIDE(cp_array_stride_reg, stride) { \
+    FDL_ASSERT(!((stride) & ~((1 << CP_ARRAY_STRIDE_REG_STRIDE_SIZE)-1))); \
+    cp_array_stride_reg = (((unsigned long)(cp_array_stride_reg)) & ~CP_ARRAY_STRIDE_REG_STRIDE_MASK) | (((unsigned long)(stride)) << CP_ARRAY_STRIDE_REG_STRIDE_SHIFT);\
+}
+#define CP_ARRAY_STRIDE_REG_PAD0_SIZE   24
+#define CP_ARRAY_STRIDE_REG_PAD0_SHIFT  8
+#define CP_ARRAY_STRIDE_REG_PAD0_MASK   0xffffff00
+#define CP_ARRAY_STRIDE_REG_GET_PAD0(cp_array_stride_reg) \
+    ((((unsigned long)(cp_array_stride_reg)) & CP_ARRAY_STRIDE_REG_PAD0_MASK) >> CP_ARRAY_STRIDE_REG_PAD0_SHIFT)
+#define CP_ARRAY_STRIDE_REG_SET_PAD0(cp_array_stride_reg, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_ARRAY_STRIDE_REG_PAD0_SIZE)-1))); \
+    cp_array_stride_reg = (((unsigned long)(cp_array_stride_reg)) & ~CP_ARRAY_STRIDE_REG_PAD0_MASK) | (((unsigned long)(pad0)) << CP_ARRAY_STRIDE_REG_PAD0_SHIFT);\
+}
+#define CP_ARRAY_STRIDE_REG_TOTAL_SIZE  32
+#define CP_ARRAY_STRIDE_REG(stride) \
+    ((((unsigned long)(stride)) << CP_ARRAY_STRIDE_REG_STRIDE_SHIFT))
+
+/*
+*  cp_stat_enable_reg struct
+*/
+#define CP_STAT_ENABLE_REG_VC_STAT_SIZE 1
+#define CP_STAT_ENABLE_REG_VC_STAT_SHIFT    0
+#define CP_STAT_ENABLE_REG_VC_STAT_MASK 0x00000001
+#define CP_STAT_ENABLE_REG_GET_VC_STAT(cp_stat_enable_reg) \
+    ((((unsigned long)(cp_stat_enable_reg)) & CP_STAT_ENABLE_REG_VC_STAT_MASK) >> CP_STAT_ENABLE_REG_VC_STAT_SHIFT)
+#define CP_STAT_ENABLE_REG_SET_VC_STAT(cp_stat_enable_reg, vc_stat) { \
+    FDL_ASSERT(!((vc_stat) & ~((1 << CP_STAT_ENABLE_REG_VC_STAT_SIZE)-1))); \
+    cp_stat_enable_reg = (((unsigned long)(cp_stat_enable_reg)) & ~CP_STAT_ENABLE_REG_VC_STAT_MASK) | (((unsigned long)(vc_stat)) << CP_STAT_ENABLE_REG_VC_STAT_SHIFT);\
+}
+#define CP_STAT_ENABLE_REG_PAD0_SIZE    1
+#define CP_STAT_ENABLE_REG_PAD0_SHIFT   1
+#define CP_STAT_ENABLE_REG_PAD0_MASK    0x00000002
+#define CP_STAT_ENABLE_REG_GET_PAD0(cp_stat_enable_reg) \
+    ((((unsigned long)(cp_stat_enable_reg)) & CP_STAT_ENABLE_REG_PAD0_MASK) >> CP_STAT_ENABLE_REG_PAD0_SHIFT)
+#define CP_STAT_ENABLE_REG_SET_PAD0(cp_stat_enable_reg, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_STAT_ENABLE_REG_PAD0_SIZE)-1))); \
+    cp_stat_enable_reg = (((unsigned long)(cp_stat_enable_reg)) & ~CP_STAT_ENABLE_REG_PAD0_MASK) | (((unsigned long)(pad0)) << CP_STAT_ENABLE_REG_PAD0_SHIFT);\
+}
+#define CP_STAT_ENABLE_REG_FRCLK_SIZE   1
+#define CP_STAT_ENABLE_REG_FRCLK_SHIFT  2
+#define CP_STAT_ENABLE_REG_FRCLK_MASK   0x00000004
+#define CP_STAT_ENABLE_REG_GET_FRCLK(cp_stat_enable_reg) \
+    ((((unsigned long)(cp_stat_enable_reg)) & CP_STAT_ENABLE_REG_FRCLK_MASK) >> CP_STAT_ENABLE_REG_FRCLK_SHIFT)
+#define CP_STAT_ENABLE_REG_SET_FRCLK(cp_stat_enable_reg, frclk) { \
+    FDL_ASSERT(!((frclk) & ~((1 << CP_STAT_ENABLE_REG_FRCLK_SIZE)-1))); \
+    cp_stat_enable_reg = (((unsigned long)(cp_stat_enable_reg)) & ~CP_STAT_ENABLE_REG_FRCLK_MASK) | (((unsigned long)(frclk)) << CP_STAT_ENABLE_REG_FRCLK_SHIFT);\
+}
+#define CP_STAT_ENABLE_REG_TOTAL_SIZE   3
+#define CP_STAT_ENABLE_REG(vc_stat, frclk) \
+    ((((unsigned long)(vc_stat)) << CP_STAT_ENABLE_REG_VC_STAT_SHIFT) | \
+    (((unsigned long)(frclk)) << CP_STAT_ENABLE_REG_FRCLK_SHIFT))
+
+/*
+*  cp_stat_sel_reg struct
+*/
+#define CP_STAT_SEL_REG_ATTR_SEL_SIZE   4
+#define CP_STAT_SEL_REG_ATTR_SEL_SHIFT  0
+#define CP_STAT_SEL_REG_ATTR_SEL_MASK   0x0000000f
+#define CP_STAT_SEL_REG_GET_ATTR_SEL(cp_stat_sel_reg) \
+    ((((unsigned long)(cp_stat_sel_reg)) & CP_STAT_SEL_REG_ATTR_SEL_MASK) >> CP_STAT_SEL_REG_ATTR_SEL_SHIFT)
+#define CP_STAT_SEL_REG_SET_ATTR_SEL(cp_stat_sel_reg, attr_sel) { \
+    FDL_ASSERT(!((attr_sel) & ~((1 << CP_STAT_SEL_REG_ATTR_SEL_SIZE)-1))); \
+    cp_stat_sel_reg = (((unsigned long)(cp_stat_sel_reg)) & ~CP_STAT_SEL_REG_ATTR_SEL_MASK) | (((unsigned long)(attr_sel)) << CP_STAT_SEL_REG_ATTR_SEL_SHIFT);\
+}
+#define CP_STAT_SEL_REG_STALLPERF_SEL_SIZE  4
+#define CP_STAT_SEL_REG_STALLPERF_SEL_SHIFT 4
+#define CP_STAT_SEL_REG_STALLPERF_SEL_MASK  0x000000f0
+#define CP_STAT_SEL_REG_GET_STALLPERF_SEL(cp_stat_sel_reg) \
+    ((((unsigned long)(cp_stat_sel_reg)) & CP_STAT_SEL_REG_STALLPERF_SEL_MASK) >> CP_STAT_SEL_REG_STALLPERF_SEL_SHIFT)
+#define CP_STAT_SEL_REG_SET_STALLPERF_SEL(cp_stat_sel_reg, stallperf_sel) { \
+    FDL_ASSERT(!((stallperf_sel) & ~((1 << CP_STAT_SEL_REG_STALLPERF_SEL_SIZE)-1))); \
+    cp_stat_sel_reg = (((unsigned long)(cp_stat_sel_reg)) & ~CP_STAT_SEL_REG_STALLPERF_SEL_MASK) | (((unsigned long)(stallperf_sel)) << CP_STAT_SEL_REG_STALLPERF_SEL_SHIFT);\
+}
+#define CP_STAT_SEL_REG_TOTAL_SIZE  8
+#define CP_STAT_SEL_REG(attr_sel, stallperf_sel) \
+    ((((unsigned long)(attr_sel)) << CP_STAT_SEL_REG_ATTR_SEL_SHIFT) | \
+    (((unsigned long)(stallperf_sel)) << CP_STAT_SEL_REG_STALLPERF_SEL_SHIFT))
+
+/*
+*  cp_stallperf_sel enum
+*/
+#define STALLPERF_ZERO  0x00000000
+#define STALLPERF_ONE   0x00000001
+#define ELEMQ_FULL  0x00000002
+#define MISSQ_FULL  0x00000003
+#define MEMREQ_FULL 0x00000004
+#define VC_STATCNT7 0x00000005
+#define VC_MISS_REP_FULL    0x00000006
+#define VC_STALL_STMBUFLOW  0x00000007
+#define VTX_CNT 0x00000008
+#define ALL_STALL   0x00000009
+#define CP_STALLPERF_SEL_UNUSED_10  0x0000000a
+#define CP_STALLPERF_SEL_UNUSED_11  0x0000000b
+#define CP_STALLPERF_SEL_UNUSED_12  0x0000000c
+#define CP_STALLPERF_SEL_UNUSED_13  0x0000000d
+#define CP_STALLPERF_SEL_UNUSED_14  0x0000000e
+#define CP_STALLPERF_SEL_UNUSED_15  0x0000000f
+
+/*
+*  cp_array_addr value
+*/
+#define ATTR_ARRAY_POS  0x0
+#define ATTR_ARRAY_NRM  0x1
+#define ATTR_ARRAY_COL0 0x2
+#define ATTR_ARRAY_COL1 0x3
+#define ATTR_ARRAY_TEX0 0x4
+#define ATTR_ARRAY_TEX1 0x5
+#define ATTR_ARRAY_TEX2 0x6
+#define ATTR_ARRAY_TEX3 0x7
+#define ATTR_ARRAY_TEX4 0x8
+#define ATTR_ARRAY_TEX5 0x9
+#define ATTR_ARRAY_TEX6 0xa
+#define ATTR_ARRAY_TEX7 0xb
+#define ATTR_ARRAY_XFINDREGA    0xc
+#define ATTR_ARRAY_XFINDREGB    0xd
+#define ATTR_ARRAY_XFINDREGC    0xe
+#define ATTR_ARRAY_XFINDREGD    0xf
+
+/*
+*  cp_xf_loadregs struct
+*/
+#define CP_XF_LOADREGS_ADDR_SIZE    16
+#define CP_XF_LOADREGS_ADDR_SHIFT   0
+#define CP_XF_LOADREGS_ADDR_MASK    0x0000ffff
+#define CP_XF_LOADREGS_GET_ADDR(cp_xf_loadregs) \
+    ((((unsigned long)(cp_xf_loadregs)) & CP_XF_LOADREGS_ADDR_MASK) >> CP_XF_LOADREGS_ADDR_SHIFT)
+#define CP_XF_LOADREGS_SET_ADDR(cp_xf_loadregs, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_XF_LOADREGS_ADDR_SIZE)-1))); \
+    cp_xf_loadregs = (((unsigned long)(cp_xf_loadregs)) & ~CP_XF_LOADREGS_ADDR_MASK) | (((unsigned long)(addr)) << CP_XF_LOADREGS_ADDR_SHIFT);\
+}
+#define CP_XF_LOADREGS_CNT_SIZE 4
+#define CP_XF_LOADREGS_CNT_SHIFT    16
+#define CP_XF_LOADREGS_CNT_MASK 0x000f0000
+#define CP_XF_LOADREGS_GET_CNT(cp_xf_loadregs) \
+    ((((unsigned long)(cp_xf_loadregs)) & CP_XF_LOADREGS_CNT_MASK) >> CP_XF_LOADREGS_CNT_SHIFT)
+#define CP_XF_LOADREGS_SET_CNT(cp_xf_loadregs, cnt) { \
+    FDL_ASSERT(!((cnt) & ~((1 << CP_XF_LOADREGS_CNT_SIZE)-1))); \
+    cp_xf_loadregs = (((unsigned long)(cp_xf_loadregs)) & ~CP_XF_LOADREGS_CNT_MASK) | (((unsigned long)(cnt)) << CP_XF_LOADREGS_CNT_SHIFT);\
+}
+#define CP_XF_LOADREGS_TOTAL_SIZE   20
+#define CP_XF_LOADREGS_UNUSED_SIZE  12
+
+#define CP_XF_LOADREGS(addr, cnt) \
+    ((((unsigned long)(addr)) << CP_XF_LOADREGS_ADDR_SHIFT) | \
+    (((unsigned long)(cnt)) << CP_XF_LOADREGS_CNT_SHIFT))
+
+/*
+*  cp_xf_loadindex struct
+*/
+#define CP_XF_LOADINDEX_ADDR_SIZE   12
+#define CP_XF_LOADINDEX_ADDR_SHIFT  0
+#define CP_XF_LOADINDEX_ADDR_MASK   0x00000fff
+#define CP_XF_LOADINDEX_GET_ADDR(cp_xf_loadindex) \
+    ((((unsigned long)(cp_xf_loadindex)) & CP_XF_LOADINDEX_ADDR_MASK) >> CP_XF_LOADINDEX_ADDR_SHIFT)
+#define CP_XF_LOADINDEX_SET_ADDR(cp_xf_loadindex, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_XF_LOADINDEX_ADDR_SIZE)-1))); \
+    cp_xf_loadindex = (((unsigned long)(cp_xf_loadindex)) & ~CP_XF_LOADINDEX_ADDR_MASK) | (((unsigned long)(addr)) << CP_XF_LOADINDEX_ADDR_SHIFT);\
+}
+#define CP_XF_LOADINDEX_CNT_SIZE    4
+#define CP_XF_LOADINDEX_CNT_SHIFT   12
+#define CP_XF_LOADINDEX_CNT_MASK    0x0000f000
+#define CP_XF_LOADINDEX_GET_CNT(cp_xf_loadindex) \
+    ((((unsigned long)(cp_xf_loadindex)) & CP_XF_LOADINDEX_CNT_MASK) >> CP_XF_LOADINDEX_CNT_SHIFT)
+#define CP_XF_LOADINDEX_SET_CNT(cp_xf_loadindex, cnt) { \
+    FDL_ASSERT(!((cnt) & ~((1 << CP_XF_LOADINDEX_CNT_SIZE)-1))); \
+    cp_xf_loadindex = (((unsigned long)(cp_xf_loadindex)) & ~CP_XF_LOADINDEX_CNT_MASK) | (((unsigned long)(cnt)) << CP_XF_LOADINDEX_CNT_SHIFT);\
+}
+#define CP_XF_LOADINDEX_IDX_SIZE    16
+#define CP_XF_LOADINDEX_IDX_SHIFT   16
+#define CP_XF_LOADINDEX_IDX_MASK    0xffff0000
+#define CP_XF_LOADINDEX_GET_IDX(cp_xf_loadindex) \
+    ((((unsigned long)(cp_xf_loadindex)) & CP_XF_LOADINDEX_IDX_MASK) >> CP_XF_LOADINDEX_IDX_SHIFT)
+#define CP_XF_LOADINDEX_SET_IDX(cp_xf_loadindex, idx) { \
+    FDL_ASSERT(!((idx) & ~((1 << CP_XF_LOADINDEX_IDX_SIZE)-1))); \
+    cp_xf_loadindex = (((unsigned long)(cp_xf_loadindex)) & ~CP_XF_LOADINDEX_IDX_MASK) | (((unsigned long)(idx)) << CP_XF_LOADINDEX_IDX_SHIFT);\
+}
+#define CP_XF_LOADINDEX_TOTAL_SIZE  32
+#define CP_XF_LOADINDEX(addr, cnt, idx) \
+    ((((unsigned long)(addr)) << CP_XF_LOADINDEX_ADDR_SHIFT) | \
+    (((unsigned long)(cnt)) << CP_XF_LOADINDEX_CNT_SHIFT) | \
+    (((unsigned long)(idx)) << CP_XF_LOADINDEX_IDX_SHIFT))
+
+/*
+*  cp_callobj_d1 struct
+*/
+#define CP_CALLOBJ_D1_PAD0_SIZE 5
+#define CP_CALLOBJ_D1_PAD0_SHIFT    0
+#define CP_CALLOBJ_D1_PAD0_MASK 0x0000001f
+#define CP_CALLOBJ_D1_GET_PAD0(cp_callobj_d1) \
+    ((((unsigned long)(cp_callobj_d1)) & CP_CALLOBJ_D1_PAD0_MASK) >> CP_CALLOBJ_D1_PAD0_SHIFT)
+#define CP_CALLOBJ_D1_SET_PAD0(cp_callobj_d1, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_CALLOBJ_D1_PAD0_SIZE)-1))); \
+    cp_callobj_d1 = (((unsigned long)(cp_callobj_d1)) & ~CP_CALLOBJ_D1_PAD0_MASK) | (((unsigned long)(pad0)) << CP_CALLOBJ_D1_PAD0_SHIFT);\
+}
+#define CP_CALLOBJ_D1_ADDR_SIZE 24
+#define CP_CALLOBJ_D1_ADDR_SHIFT    5
+#define CP_CALLOBJ_D1_ADDR_MASK 0x1fffffe0
+#define CP_CALLOBJ_D1_GET_ADDR(cp_callobj_d1) \
+    ((((unsigned long)(cp_callobj_d1)) & CP_CALLOBJ_D1_ADDR_MASK) >> CP_CALLOBJ_D1_ADDR_SHIFT)
+#define CP_CALLOBJ_D1_SET_ADDR(cp_callobj_d1, addr) { \
+    FDL_ASSERT(!((addr) & ~((1 << CP_CALLOBJ_D1_ADDR_SIZE)-1))); \
+    cp_callobj_d1 = (((unsigned long)(cp_callobj_d1)) & ~CP_CALLOBJ_D1_ADDR_MASK) | (((unsigned long)(addr)) << CP_CALLOBJ_D1_ADDR_SHIFT);\
+}
+#define CP_CALLOBJ_D1_TOTAL_SIZE    29
+#define CP_CALLOBJ_D1_UNUSED_SIZE   3
+
+#define CP_CALLOBJ_D1(addr) \
+    ((((unsigned long)(addr)) << CP_CALLOBJ_D1_ADDR_SHIFT))
+
+/*
+*  cp_callobj_d2 struct
+*/
+#define CP_CALLOBJ_D2_PAD0_SIZE 5
+#define CP_CALLOBJ_D2_PAD0_SHIFT    0
+#define CP_CALLOBJ_D2_PAD0_MASK 0x0000001f
+#define CP_CALLOBJ_D2_GET_PAD0(cp_callobj_d2) \
+    ((((unsigned long)(cp_callobj_d2)) & CP_CALLOBJ_D2_PAD0_MASK) >> CP_CALLOBJ_D2_PAD0_SHIFT)
+#define CP_CALLOBJ_D2_SET_PAD0(cp_callobj_d2, pad0) { \
+    FDL_ASSERT(!((pad0) & ~((1 << CP_CALLOBJ_D2_PAD0_SIZE)-1))); \
+    cp_callobj_d2 = (((unsigned long)(cp_callobj_d2)) & ~CP_CALLOBJ_D2_PAD0_MASK) | (((unsigned long)(pad0)) << CP_CALLOBJ_D2_PAD0_SHIFT);\
+}
+#define CP_CALLOBJ_D2_CNT_SIZE  24
+#define CP_CALLOBJ_D2_CNT_SHIFT 5
+#define CP_CALLOBJ_D2_CNT_MASK  0x1fffffe0
+#define CP_CALLOBJ_D2_GET_CNT(cp_callobj_d2) \
+    ((((unsigned long)(cp_callobj_d2)) & CP_CALLOBJ_D2_CNT_MASK) >> CP_CALLOBJ_D2_CNT_SHIFT)
+#define CP_CALLOBJ_D2_SET_CNT(cp_callobj_d2, cnt) { \
+    FDL_ASSERT(!((cnt) & ~((1 << CP_CALLOBJ_D2_CNT_SIZE)-1))); \
+    cp_callobj_d2 = (((unsigned long)(cp_callobj_d2)) & ~CP_CALLOBJ_D2_CNT_MASK) | (((unsigned long)(cnt)) << CP_CALLOBJ_D2_CNT_SHIFT);\
+}
+#define CP_CALLOBJ_D2_TOTAL_SIZE    29
+#define CP_CALLOBJ_D2_UNUSED_SIZE   3
+
+#define CP_CALLOBJ_D2(cnt) \
+    ((((unsigned long)(cnt)) << CP_CALLOBJ_D2_CNT_SHIFT))
+
+
+
+#define SC_CP_OPCODE_SET_INDEX(line, cp_opcode,index) \
+	FAST_GPFLAGSET(line, cp_opcode,index,CP_OPCODE_INDEX)
+
+#define SC_CP_OPCODE_SET_CMD(line, cp_opcode,cmd) \
+	FAST_GPFLAGSET(line, cp_opcode,cmd,CP_OPCODE_CMD)
+
+#define SC_CP_STREAM_REG_SET_INDEX(line, cp_stream_reg,index) \
+	FAST_GPFLAGSET(line, cp_stream_reg,index,CP_STREAM_REG_INDEX)
+
+#define SC_CP_STREAM_REG_SET_ADDR(line, cp_stream_reg,addr) \
+	FAST_GPFLAGSET(line, cp_stream_reg,addr,CP_STREAM_REG_ADDR)
+
+#define SC_CP_REG_STATUS_SET_OVFL(line, cp_reg_status,ovfl) \
+	FAST_GPFLAGSET(line, cp_reg_status,ovfl,CP_REG_STATUS_OVFL)
+
+#define SC_CP_REG_STATUS_SET_UNFL(line, cp_reg_status,unfl) \
+	FAST_GPFLAGSET(line, cp_reg_status,unfl,CP_REG_STATUS_UNFL)
+
+#define SC_CP_REG_STATUS_SET_FIFO_RDIDLE(line, cp_reg_status,fifo_rdidle) \
+	FAST_GPFLAGSET(line, cp_reg_status,fifo_rdidle,CP_REG_STATUS_FIFO_RDIDLE)
+
+#define SC_CP_REG_STATUS_SET_CPIDLE(line, cp_reg_status,cpidle) \
+	FAST_GPFLAGSET(line, cp_reg_status,cpidle,CP_REG_STATUS_CPIDLE)
+
+#define SC_CP_REG_STATUS_SET_FIFOBRK(line, cp_reg_status,fifobrk) \
+	FAST_GPFLAGSET(line, cp_reg_status,fifobrk,CP_REG_STATUS_FIFOBRK)
+
+#define SC_CP_REG_ENABLE_SET_FIFORD(line, cp_reg_enable,fiford) \
+	FAST_GPFLAGSET(line, cp_reg_enable,fiford,CP_REG_ENABLE_FIFORD)
+
+#define SC_CP_REG_ENABLE_SET_FIFOBRK(line, cp_reg_enable,fifobrk) \
+	FAST_GPFLAGSET(line, cp_reg_enable,fifobrk,CP_REG_ENABLE_FIFOBRK)
+
+#define SC_CP_REG_ENABLE_SET_OVFLINT(line, cp_reg_enable,ovflint) \
+	FAST_GPFLAGSET(line, cp_reg_enable,ovflint,CP_REG_ENABLE_OVFLINT)
+
+#define SC_CP_REG_ENABLE_SET_UNFLINT(line, cp_reg_enable,unflint) \
+	FAST_GPFLAGSET(line, cp_reg_enable,unflint,CP_REG_ENABLE_UNFLINT)
+
+#define SC_CP_REG_ENABLE_SET_WRPTRINC(line, cp_reg_enable,wrptrinc) \
+	FAST_GPFLAGSET(line, cp_reg_enable,wrptrinc,CP_REG_ENABLE_WRPTRINC)
+
+#define SC_CP_REG_ENABLE_SET_FIFOBRKINT(line, cp_reg_enable,fifobrkint) \
+	FAST_GPFLAGSET(line, cp_reg_enable,fifobrkint,CP_REG_ENABLE_FIFOBRKINT)
+
+#define SC_CP_REG_CLR_SET_OVFLINT(line, cp_reg_clr,ovflint) \
+	FAST_GPFLAGSET(line, cp_reg_clr,ovflint,CP_REG_CLR_OVFLINT)
+
+#define SC_CP_REG_CLR_SET_UNFLINT(line, cp_reg_clr,unflint) \
+	FAST_GPFLAGSET(line, cp_reg_clr,unflint,CP_REG_CLR_UNFLINT)
+
+#define SC_CP_REG_CLR_SET_PERFCNT(line, cp_reg_clr,perfcnt) \
+	FAST_GPFLAGSET(line, cp_reg_clr,perfcnt,CP_REG_CLR_PERFCNT)
+
+#define SC_CP_REG_MEMPERFSEL_SET_PERFSEL(line, cp_reg_memperfsel,perfsel) \
+	FAST_GPFLAGSET(line, cp_reg_memperfsel,perfsel,CP_REG_MEMPERFSEL_PERFSEL)
+
+#define SC_CP_REG_FIFO_BASEL_SET_PAD0(line, cp_reg_fifo_basel,pad0) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_basel,pad0,CP_REG_FIFO_BASEL_PAD0)
+
+#define SC_CP_REG_FIFO_BASEL_SET_ADDR(line, cp_reg_fifo_basel,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_basel,addr,CP_REG_FIFO_BASEL_ADDR)
+
+#define SC_CP_REG_FIFO_BASEH_SET_ADDR(line, cp_reg_fifo_baseh,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_baseh,addr,CP_REG_FIFO_BASEH_ADDR)
+
+#define SC_CP_REG_FIFO_TOPL_SET_PAD0(line, cp_reg_fifo_topl,pad0) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_topl,pad0,CP_REG_FIFO_TOPL_PAD0)
+
+#define SC_CP_REG_FIFO_TOPL_SET_ADDR(line, cp_reg_fifo_topl,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_topl,addr,CP_REG_FIFO_TOPL_ADDR)
+
+#define SC_CP_REG_FIFO_TOPH_SET_ADDR(line, cp_reg_fifo_toph,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_toph,addr,CP_REG_FIFO_TOPH_ADDR)
+
+#define SC_CP_REG_FIFO_HICNTL_SET_PAD0(line, cp_reg_fifo_hicntl,pad0) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_hicntl,pad0,CP_REG_FIFO_HICNTL_PAD0)
+
+#define SC_CP_REG_FIFO_HICNTL_SET_ADDR(line, cp_reg_fifo_hicntl,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_hicntl,addr,CP_REG_FIFO_HICNTL_ADDR)
+
+#define SC_CP_REG_FIFO_HICNTH_SET_ADDR(line, cp_reg_fifo_hicnth,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_hicnth,addr,CP_REG_FIFO_HICNTH_ADDR)
+
+#define SC_CP_REG_FIFO_LOCNTL_SET_PAD0(line, cp_reg_fifo_locntl,pad0) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_locntl,pad0,CP_REG_FIFO_LOCNTL_PAD0)
+
+#define SC_CP_REG_FIFO_LOCNTL_SET_ADDR(line, cp_reg_fifo_locntl,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_locntl,addr,CP_REG_FIFO_LOCNTL_ADDR)
+
+#define SC_CP_REG_FIFO_LOCNTH_SET_ADDR(line, cp_reg_fifo_locnth,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_locnth,addr,CP_REG_FIFO_LOCNTH_ADDR)
+
+#define SC_CP_REG_FIFO_COUNTL_SET_PAD0(line, cp_reg_fifo_countl,pad0) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_countl,pad0,CP_REG_FIFO_COUNTL_PAD0)
+
+#define SC_CP_REG_FIFO_COUNTL_SET_ADDR(line, cp_reg_fifo_countl,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_countl,addr,CP_REG_FIFO_COUNTL_ADDR)
+
+#define SC_CP_REG_FIFO_COUNTH_SET_ADDR(line, cp_reg_fifo_counth,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_counth,addr,CP_REG_FIFO_COUNTH_ADDR)
+
+#define SC_CP_REG_FIFO_WPTRL_SET_PAD0(line, cp_reg_fifo_wptrl,pad0) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_wptrl,pad0,CP_REG_FIFO_WPTRL_PAD0)
+
+#define SC_CP_REG_FIFO_WPTRL_SET_ADDR(line, cp_reg_fifo_wptrl,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_wptrl,addr,CP_REG_FIFO_WPTRL_ADDR)
+
+#define SC_CP_REG_FIFO_WPTRH_SET_ADDR(line, cp_reg_fifo_wptrh,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_wptrh,addr,CP_REG_FIFO_WPTRH_ADDR)
+
+#define SC_CP_REG_FIFO_RPTRL_SET_PAD0(line, cp_reg_fifo_rptrl,pad0) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_rptrl,pad0,CP_REG_FIFO_RPTRL_PAD0)
+
+#define SC_CP_REG_FIFO_RPTRL_SET_ADDR(line, cp_reg_fifo_rptrl,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_rptrl,addr,CP_REG_FIFO_RPTRL_ADDR)
+
+#define SC_CP_REG_FIFO_RPTRH_SET_ADDR(line, cp_reg_fifo_rptrh,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_rptrh,addr,CP_REG_FIFO_RPTRH_ADDR)
+
+#define SC_CP_REG_FIFO_BRKL_SET_PAD0(line, cp_reg_fifo_brkl,pad0) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_brkl,pad0,CP_REG_FIFO_BRKL_PAD0)
+
+#define SC_CP_REG_FIFO_BRKL_SET_ADDR(line, cp_reg_fifo_brkl,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_brkl,addr,CP_REG_FIFO_BRKL_ADDR)
+
+#define SC_CP_REG_FIFO_BRKH_SET_ADDR(line, cp_reg_fifo_brkh,addr) \
+	FAST_GPFLAGSET(line, cp_reg_fifo_brkh,addr,CP_REG_FIFO_BRKH_ADDR)
+
+#define SC_CP_VCD_REG_LO_SET_PMIDX(line, cp_vcd_reg_lo,pmidx) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,pmidx,CP_VCD_REG_LO_PMIDX)
+
+#define SC_CP_VCD_REG_LO_SET_T0MIDX(line, cp_vcd_reg_lo,t0midx) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,t0midx,CP_VCD_REG_LO_T0MIDX)
+
+#define SC_CP_VCD_REG_LO_SET_T1MIDX(line, cp_vcd_reg_lo,t1midx) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,t1midx,CP_VCD_REG_LO_T1MIDX)
+
+#define SC_CP_VCD_REG_LO_SET_T2MIDX(line, cp_vcd_reg_lo,t2midx) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,t2midx,CP_VCD_REG_LO_T2MIDX)
+
+#define SC_CP_VCD_REG_LO_SET_T3MIDX(line, cp_vcd_reg_lo,t3midx) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,t3midx,CP_VCD_REG_LO_T3MIDX)
+
+#define SC_CP_VCD_REG_LO_SET_T4MIDX(line, cp_vcd_reg_lo,t4midx) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,t4midx,CP_VCD_REG_LO_T4MIDX)
+
+#define SC_CP_VCD_REG_LO_SET_T5MIDX(line, cp_vcd_reg_lo,t5midx) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,t5midx,CP_VCD_REG_LO_T5MIDX)
+
+#define SC_CP_VCD_REG_LO_SET_T6MIDX(line, cp_vcd_reg_lo,t6midx) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,t6midx,CP_VCD_REG_LO_T6MIDX)
+
+#define SC_CP_VCD_REG_LO_SET_T7MIDX(line, cp_vcd_reg_lo,t7midx) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,t7midx,CP_VCD_REG_LO_T7MIDX)
+
+#define SC_CP_VCD_REG_LO_SET_POS(line, cp_vcd_reg_lo,pos) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,pos,CP_VCD_REG_LO_POS)
+
+#define SC_CP_VCD_REG_LO_SET_NRM(line, cp_vcd_reg_lo,nrm) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,nrm,CP_VCD_REG_LO_NRM)
+
+#define SC_CP_VCD_REG_LO_SET_COL0(line, cp_vcd_reg_lo,col0) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,col0,CP_VCD_REG_LO_COL0)
+
+#define SC_CP_VCD_REG_LO_SET_COL1(line, cp_vcd_reg_lo,col1) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_lo,col1,CP_VCD_REG_LO_COL1)
+
+#define SC_CP_VCD_REG_HI_SET_TEX0(line, cp_vcd_reg_hi,tex0) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex0,CP_VCD_REG_HI_TEX0)
+
+#define SC_CP_VCD_REG_HI_SET_TEX1(line, cp_vcd_reg_hi,tex1) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex1,CP_VCD_REG_HI_TEX1)
+
+#define SC_CP_VCD_REG_HI_SET_TEX2(line, cp_vcd_reg_hi,tex2) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex2,CP_VCD_REG_HI_TEX2)
+
+#define SC_CP_VCD_REG_HI_SET_TEX3(line, cp_vcd_reg_hi,tex3) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex3,CP_VCD_REG_HI_TEX3)
+
+#define SC_CP_VCD_REG_HI_SET_TEX4(line, cp_vcd_reg_hi,tex4) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex4,CP_VCD_REG_HI_TEX4)
+
+#define SC_CP_VCD_REG_HI_SET_TEX5(line, cp_vcd_reg_hi,tex5) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex5,CP_VCD_REG_HI_TEX5)
+
+#define SC_CP_VCD_REG_HI_SET_TEX6(line, cp_vcd_reg_hi,tex6) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex6,CP_VCD_REG_HI_TEX6)
+
+#define SC_CP_VCD_REG_HI_SET_TEX7(line, cp_vcd_reg_hi,tex7) \
+	FAST_GPFLAGSET(line, cp_vcd_reg_hi,tex7,CP_VCD_REG_HI_TEX7)
+
+#define SC_CP_VAT_REG_A_SET_POSCNT(line, cp_vat_reg_a,posCnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,posCnt,CP_VAT_REG_A_POSCNT)
+
+#define SC_CP_VAT_REG_A_SET_POSFMT(line, cp_vat_reg_a,posFmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,posFmt,CP_VAT_REG_A_POSFMT)
+
+#define SC_CP_VAT_REG_A_SET_POSSHFT(line, cp_vat_reg_a,posShft) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,posShft,CP_VAT_REG_A_POSSHFT)
+
+#define SC_CP_VAT_REG_A_SET_NRMCNT(line, cp_vat_reg_a,nrmCnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,nrmCnt,CP_VAT_REG_A_NRMCNT)
+
+#define SC_CP_VAT_REG_A_SET_NRMFMT(line, cp_vat_reg_a,nrmFmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,nrmFmt,CP_VAT_REG_A_NRMFMT)
+
+#define SC_CP_VAT_REG_A_SET_COL0CNT(line, cp_vat_reg_a,Col0Cnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,Col0Cnt,CP_VAT_REG_A_COL0CNT)
+
+#define SC_CP_VAT_REG_A_SET_COL0FMT(line, cp_vat_reg_a,Col0Fmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,Col0Fmt,CP_VAT_REG_A_COL0FMT)
+
+#define SC_CP_VAT_REG_A_SET_COL1CNT(line, cp_vat_reg_a,Col1Cnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,Col1Cnt,CP_VAT_REG_A_COL1CNT)
+
+#define SC_CP_VAT_REG_A_SET_COL1FMT(line, cp_vat_reg_a,Col1Fmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,Col1Fmt,CP_VAT_REG_A_COL1FMT)
+
+#define SC_CP_VAT_REG_A_SET_TEX0CNT(line, cp_vat_reg_a,tex0Cnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,tex0Cnt,CP_VAT_REG_A_TEX0CNT)
+
+#define SC_CP_VAT_REG_A_SET_TEX0FMT(line, cp_vat_reg_a,tex0Fmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,tex0Fmt,CP_VAT_REG_A_TEX0FMT)
+
+#define SC_CP_VAT_REG_A_SET_TEX0SHFT(line, cp_vat_reg_a,tex0Shft) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,tex0Shft,CP_VAT_REG_A_TEX0SHFT)
+
+#define SC_CP_VAT_REG_A_SET_BYTEDEQUANT(line, cp_vat_reg_a,byteDequant) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,byteDequant,CP_VAT_REG_A_BYTEDEQUANT)
+
+#define SC_CP_VAT_REG_A_SET_NORMALINDEX3(line, cp_vat_reg_a,normalIndex3) \
+	FAST_GPFLAGSET(line, cp_vat_reg_a,normalIndex3,CP_VAT_REG_A_NORMALINDEX3)
+
+#define SC_CP_VAT_REG_B_SET_TEX1CNT(line, cp_vat_reg_b,tex1Cnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex1Cnt,CP_VAT_REG_B_TEX1CNT)
+
+#define SC_CP_VAT_REG_B_SET_TEX1FMT(line, cp_vat_reg_b,tex1Fmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex1Fmt,CP_VAT_REG_B_TEX1FMT)
+
+#define SC_CP_VAT_REG_B_SET_TEX1SHFT(line, cp_vat_reg_b,tex1Shft) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex1Shft,CP_VAT_REG_B_TEX1SHFT)
+
+#define SC_CP_VAT_REG_B_SET_TEX2CNT(line, cp_vat_reg_b,tex2Cnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex2Cnt,CP_VAT_REG_B_TEX2CNT)
+
+#define SC_CP_VAT_REG_B_SET_TEX2FMT(line, cp_vat_reg_b,tex2Fmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex2Fmt,CP_VAT_REG_B_TEX2FMT)
+
+#define SC_CP_VAT_REG_B_SET_TEX2SHFT(line, cp_vat_reg_b,tex2Shft) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex2Shft,CP_VAT_REG_B_TEX2SHFT)
+
+#define SC_CP_VAT_REG_B_SET_TEX3CNT(line, cp_vat_reg_b,tex3Cnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex3Cnt,CP_VAT_REG_B_TEX3CNT)
+
+#define SC_CP_VAT_REG_B_SET_TEX3FMT(line, cp_vat_reg_b,tex3Fmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex3Fmt,CP_VAT_REG_B_TEX3FMT)
+
+#define SC_CP_VAT_REG_B_SET_TEX3SHFT(line, cp_vat_reg_b,tex3Shft) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex3Shft,CP_VAT_REG_B_TEX3SHFT)
+
+#define SC_CP_VAT_REG_B_SET_TEX4CNT(line, cp_vat_reg_b,tex4Cnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex4Cnt,CP_VAT_REG_B_TEX4CNT)
+
+#define SC_CP_VAT_REG_B_SET_TEX4FMT(line, cp_vat_reg_b,tex4Fmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,tex4Fmt,CP_VAT_REG_B_TEX4FMT)
+
+#define SC_CP_VAT_REG_B_SET_VCACHE_ENHANCE(line, cp_vat_reg_b,vcache_enhance) \
+	FAST_GPFLAGSET(line, cp_vat_reg_b,vcache_enhance,CP_VAT_REG_B_VCACHE_ENHANCE)
+
+#define SC_CP_VAT_REG_C_SET_TEX4SHFT(line, cp_vat_reg_c,tex4Shft) \
+	FAST_GPFLAGSET(line, cp_vat_reg_c,tex4Shft,CP_VAT_REG_C_TEX4SHFT)
+
+#define SC_CP_VAT_REG_C_SET_TEX5CNT(line, cp_vat_reg_c,tex5Cnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_c,tex5Cnt,CP_VAT_REG_C_TEX5CNT)
+
+#define SC_CP_VAT_REG_C_SET_TEX5FMT(line, cp_vat_reg_c,tex5Fmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_c,tex5Fmt,CP_VAT_REG_C_TEX5FMT)
+
+#define SC_CP_VAT_REG_C_SET_TEX5SHFT(line, cp_vat_reg_c,tex5Shft) \
+	FAST_GPFLAGSET(line, cp_vat_reg_c,tex5Shft,CP_VAT_REG_C_TEX5SHFT)
+
+#define SC_CP_VAT_REG_C_SET_TEX6CNT(line, cp_vat_reg_c,tex6Cnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_c,tex6Cnt,CP_VAT_REG_C_TEX6CNT)
+
+#define SC_CP_VAT_REG_C_SET_TEX6FMT(line, cp_vat_reg_c,tex6Fmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_c,tex6Fmt,CP_VAT_REG_C_TEX6FMT)
+
+#define SC_CP_VAT_REG_C_SET_TEX6SHFT(line, cp_vat_reg_c,tex6Shft) \
+	FAST_GPFLAGSET(line, cp_vat_reg_c,tex6Shft,CP_VAT_REG_C_TEX6SHFT)
+
+#define SC_CP_VAT_REG_C_SET_TEX7CNT(line, cp_vat_reg_c,tex7Cnt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_c,tex7Cnt,CP_VAT_REG_C_TEX7CNT)
+
+#define SC_CP_VAT_REG_C_SET_TEX7FMT(line, cp_vat_reg_c,tex7Fmt) \
+	FAST_GPFLAGSET(line, cp_vat_reg_c,tex7Fmt,CP_VAT_REG_C_TEX7FMT)
+
+#define SC_CP_VAT_REG_C_SET_TEX7SHFT(line, cp_vat_reg_c,tex7Shft) \
+	FAST_GPFLAGSET(line, cp_vat_reg_c,tex7Shft,CP_VAT_REG_C_TEX7SHFT)
+
+#define SC_CP_MATIDX_REG_A_SET_POSIDX(line, cp_matidx_reg_a,posIdx) \
+	FAST_GPFLAGSET(line, cp_matidx_reg_a,posIdx,CP_MATIDX_REG_A_POSIDX)
+
+#define SC_CP_MATIDX_REG_A_SET_TEX0IDX(line, cp_matidx_reg_a,tex0Idx) \
+	FAST_GPFLAGSET(line, cp_matidx_reg_a,tex0Idx,CP_MATIDX_REG_A_TEX0IDX)
+
+#define SC_CP_MATIDX_REG_A_SET_TEX1IDX(line, cp_matidx_reg_a,tex1Idx) \
+	FAST_GPFLAGSET(line, cp_matidx_reg_a,tex1Idx,CP_MATIDX_REG_A_TEX1IDX)
+
+#define SC_CP_MATIDX_REG_A_SET_TEX2IDX(line, cp_matidx_reg_a,tex2Idx) \
+	FAST_GPFLAGSET(line, cp_matidx_reg_a,tex2Idx,CP_MATIDX_REG_A_TEX2IDX)
+
+#define SC_CP_MATIDX_REG_A_SET_TEX3IDX(line, cp_matidx_reg_a,tex3Idx) \
+	FAST_GPFLAGSET(line, cp_matidx_reg_a,tex3Idx,CP_MATIDX_REG_A_TEX3IDX)
+
+#define SC_CP_MATIDX_REG_B_SET_TEX4IDX(line, cp_matidx_reg_b,tex4Idx) \
+	FAST_GPFLAGSET(line, cp_matidx_reg_b,tex4Idx,CP_MATIDX_REG_B_TEX4IDX)
+
+#define SC_CP_MATIDX_REG_B_SET_TEX5IDX(line, cp_matidx_reg_b,tex5Idx) \
+	FAST_GPFLAGSET(line, cp_matidx_reg_b,tex5Idx,CP_MATIDX_REG_B_TEX5IDX)
+
+#define SC_CP_MATIDX_REG_B_SET_TEX6IDX(line, cp_matidx_reg_b,tex6Idx) \
+	FAST_GPFLAGSET(line, cp_matidx_reg_b,tex6Idx,CP_MATIDX_REG_B_TEX6IDX)
+
+#define SC_CP_MATIDX_REG_B_SET_TEX7IDX(line, cp_matidx_reg_b,tex7Idx) \
+	FAST_GPFLAGSET(line, cp_matidx_reg_b,tex7Idx,CP_MATIDX_REG_B_TEX7IDX)
+
+#define SC_CP_ARRAY_BASE_REG_SET_BASE(line, cp_array_base_reg,base) \
+	FAST_GPFLAGSET(line, cp_array_base_reg,base,CP_ARRAY_BASE_REG_BASE)
+
+#define SC_CP_ARRAY_BASE_REG_SET_PAD0(line, cp_array_base_reg,pad0) \
+	FAST_GPFLAGSET(line, cp_array_base_reg,pad0,CP_ARRAY_BASE_REG_PAD0)
+
+#define SC_CP_ARRAY_STRIDE_REG_SET_STRIDE(line, cp_array_stride_reg,stride) \
+	FAST_GPFLAGSET(line, cp_array_stride_reg,stride,CP_ARRAY_STRIDE_REG_STRIDE)
+
+#define SC_CP_ARRAY_STRIDE_REG_SET_PAD0(line, cp_array_stride_reg,pad0) \
+	FAST_GPFLAGSET(line, cp_array_stride_reg,pad0,CP_ARRAY_STRIDE_REG_PAD0)
+
+#define SC_CP_STAT_ENABLE_REG_SET_VC_STAT(line, cp_stat_enable_reg,vc_stat) \
+	FAST_GPFLAGSET(line, cp_stat_enable_reg,vc_stat,CP_STAT_ENABLE_REG_VC_STAT)
+
+#define SC_CP_STAT_ENABLE_REG_SET_PAD0(line, cp_stat_enable_reg,pad0) \
+	FAST_GPFLAGSET(line, cp_stat_enable_reg,pad0,CP_STAT_ENABLE_REG_PAD0)
+
+#define SC_CP_STAT_ENABLE_REG_SET_FRCLK(line, cp_stat_enable_reg,frclk) \
+	FAST_GPFLAGSET(line, cp_stat_enable_reg,frclk,CP_STAT_ENABLE_REG_FRCLK)
+
+#define SC_CP_STAT_SEL_REG_SET_ATTR_SEL(line, cp_stat_sel_reg,attr_sel) \
+	FAST_GPFLAGSET(line, cp_stat_sel_reg,attr_sel,CP_STAT_SEL_REG_ATTR_SEL)
+
+#define SC_CP_STAT_SEL_REG_SET_STALLPERF_SEL(line, cp_stat_sel_reg,stallperf_sel) \
+	FAST_GPFLAGSET(line, cp_stat_sel_reg,stallperf_sel,CP_STAT_SEL_REG_STALLPERF_SEL)
+
+#define SC_CP_XF_LOADREGS_SET_ADDR(line, cp_xf_loadregs,addr) \
+	FAST_GPFLAGSET(line, cp_xf_loadregs,addr,CP_XF_LOADREGS_ADDR)
+
+#define SC_CP_XF_LOADREGS_SET_CNT(line, cp_xf_loadregs,cnt) \
+	FAST_GPFLAGSET(line, cp_xf_loadregs,cnt,CP_XF_LOADREGS_CNT)
+
+#define SC_CP_XF_LOADINDEX_SET_ADDR(line, cp_xf_loadindex,addr) \
+	FAST_GPFLAGSET(line, cp_xf_loadindex,addr,CP_XF_LOADINDEX_ADDR)
+
+#define SC_CP_XF_LOADINDEX_SET_CNT(line, cp_xf_loadindex,cnt) \
+	FAST_GPFLAGSET(line, cp_xf_loadindex,cnt,CP_XF_LOADINDEX_CNT)
+
+#define SC_CP_XF_LOADINDEX_SET_IDX(line, cp_xf_loadindex,idx) \
+	FAST_GPFLAGSET(line, cp_xf_loadindex,idx,CP_XF_LOADINDEX_IDX)
+
+#define SC_CP_CALLOBJ_D1_SET_PAD0(line, cp_callobj_d1,pad0) \
+	FAST_GPFLAGSET(line, cp_callobj_d1,pad0,CP_CALLOBJ_D1_PAD0)
+
+#define SC_CP_CALLOBJ_D1_SET_ADDR(line, cp_callobj_d1,addr) \
+	FAST_GPFLAGSET(line, cp_callobj_d1,addr,CP_CALLOBJ_D1_ADDR)
+
+#define SC_CP_CALLOBJ_D2_SET_PAD0(line, cp_callobj_d2,pad0) \
+	FAST_GPFLAGSET(line, cp_callobj_d2,pad0,CP_CALLOBJ_D2_PAD0)
+
+#define SC_CP_CALLOBJ_D2_SET_CNT(line, cp_callobj_d2,cnt) \
+	FAST_GPFLAGSET(line, cp_callobj_d2,cnt,CP_CALLOBJ_D2_CNT)
+
+#endif /* __FDL_CP_REG_H__ */
diff --git a/include/revolution/private/gen_reg.h b/include/revolution/private/gen_reg.h
new file mode 100644
index 0000000000..09aca016c0
--- /dev/null
+++ b/include/revolution/private/gen_reg.h
@@ -0,0 +1,163 @@
+#ifndef GEN_REG_H
+#define GEN_REG_H
+
+#include <revolution/private/GXFDLShortcut.h>
+
+#define GEN_MODE_RID_SIZE	8
+#define GEN_MODE_RID_SHIFT	24
+#define GEN_MODE_RID_MASK	0xff000000
+#define GEN_MODE_GET_RID(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_RID_MASK) >> GEN_MODE_RID_SHIFT)
+
+#define GEN_MODE_NTEX_SIZE	4
+#define GEN_MODE_NTEX_SHIFT	0
+#define GEN_MODE_NTEX_MASK	0x0000000f
+#define GEN_MODE_GET_NTEX(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_NTEX_MASK) >> GEN_MODE_NTEX_SHIFT)
+
+#define GEN_MODE_NTEX_SIZE	4
+#define GEN_MODE_NTEX_SHIFT	0
+#define GEN_MODE_NTEX_MASK	0x0000000f
+#define GEN_MODE_GET_NTEX(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_NTEX_MASK) >> GEN_MODE_NTEX_SHIFT)
+
+#define GEN_MODE_NCOL_SIZE	3
+#define GEN_MODE_NCOL_SHIFT	4
+#define GEN_MODE_NCOL_MASK	0x00000070
+#define GEN_MODE_GET_NCOL(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_NCOL_MASK) >> GEN_MODE_NCOL_SHIFT)
+
+#define GEN_MODE_PAD0_SIZE	1
+#define GEN_MODE_PAD0_SHIFT	7
+#define GEN_MODE_PAD0_MASK	0x00000080
+#define GEN_MODE_GET_PAD0(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_PAD0_MASK) >> GEN_MODE_PAD0_SHIFT)
+
+#define GEN_MODE_FLAT_EN_SIZE	1
+#define GEN_MODE_FLAT_EN_SHIFT	8
+#define GEN_MODE_FLAT_EN_MASK	0x00000100
+#define GEN_MODE_GET_FLAT_EN(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_FLAT_EN_MASK) >> GEN_MODE_FLAT_EN_SHIFT)
+
+#define GEN_MODE_MS_EN_SIZE	1
+#define GEN_MODE_MS_EN_SHIFT	9
+#define GEN_MODE_MS_EN_MASK	0x00000200
+#define GEN_MODE_GET_MS_EN(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_MS_EN_MASK) >> GEN_MODE_MS_EN_SHIFT)
+
+#define GEN_MODE_NTEV_SIZE	4
+#define GEN_MODE_NTEV_SHIFT	10
+#define GEN_MODE_NTEV_MASK	0x00003c00
+#define GEN_MODE_GET_NTEV(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_NTEV_MASK) >> GEN_MODE_NTEV_SHIFT)
+
+#define GEN_MODE_REJECT_EN_SIZE	2
+#define GEN_MODE_REJECT_EN_SHIFT	14
+#define GEN_MODE_REJECT_EN_MASK	0x0000c000
+#define GEN_MODE_GET_REJECT_EN(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_REJECT_EN_MASK) >> GEN_MODE_REJECT_EN_SHIFT)
+
+#define GEN_MODE_NBMP_SIZE	3
+#define GEN_MODE_NBMP_SHIFT	16
+#define GEN_MODE_NBMP_MASK	0x00070000
+#define GEN_MODE_GET_NBMP(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_NBMP_MASK) >> GEN_MODE_NBMP_SHIFT)
+
+#define GEN_MODE_ZFREEZE_SIZE	1
+#define GEN_MODE_ZFREEZE_SHIFT	19
+#define GEN_MODE_ZFREEZE_MASK	0x00080000
+#define GEN_MODE_GET_ZFREEZE(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_ZFREEZE_MASK) >> GEN_MODE_ZFREEZE_SHIFT)
+
+#define GEN_MODE_PAD1_SIZE	4
+#define GEN_MODE_PAD1_SHIFT	20
+#define GEN_MODE_PAD1_MASK	0x00f00000
+#define GEN_MODE_GET_PAD1(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_PAD1_MASK) >> GEN_MODE_PAD1_SHIFT)
+
+#define GEN_MODE_RID_SIZE	8
+#define GEN_MODE_RID_SHIFT	24
+#define GEN_MODE_RID_MASK	0xff000000
+#define GEN_MODE_GET_RID(gen_mode) \
+	((((unsigned long)(gen_mode)) & GEN_MODE_RID_MASK) >> GEN_MODE_RID_SHIFT)
+
+
+#define SC_GEN_MODE_SET_NTEX(line, gen_mode,ntex) \
+	FAST_GPFLAGSET(line, gen_mode,ntex,GEN_MODE_NTEX)
+
+#define SC_GEN_MODE_SET_NCOL(line, gen_mode,ncol) \
+	FAST_GPFLAGSET(line, gen_mode,ncol,GEN_MODE_NCOL)
+
+#define SC_GEN_MODE_SET_PAD0(line, gen_mode,pad0) \
+	FAST_GPFLAGSET(line, gen_mode,pad0,GEN_MODE_PAD0)
+
+#define SC_GEN_MODE_SET_FLAT_EN(line, gen_mode,flat_en) \
+	FAST_GPFLAGSET(line, gen_mode,flat_en,GEN_MODE_FLAT_EN)
+
+#define SC_GEN_MODE_SET_MS_EN(line, gen_mode,ms_en) \
+	FAST_GPFLAGSET(line, gen_mode,ms_en,GEN_MODE_MS_EN)
+
+#define SC_GEN_MODE_SET_NTEV(line, gen_mode,ntev) \
+	FAST_GPFLAGSET(line, gen_mode,ntev,GEN_MODE_NTEV)
+
+#define SC_GEN_MODE_SET_REJECT_EN(line, gen_mode,reject_en) \
+	FAST_GPFLAGSET(line, gen_mode,reject_en,GEN_MODE_REJECT_EN)
+
+#define SC_GEN_MODE_SET_NBMP(line, gen_mode,nbmp) \
+	FAST_GPFLAGSET(line, gen_mode,nbmp,GEN_MODE_NBMP)
+
+#define SC_GEN_MODE_SET_ZFREEZE(line, gen_mode,zfreeze) \
+	FAST_GPFLAGSET(line, gen_mode,zfreeze,GEN_MODE_ZFREEZE)
+
+#define SC_GEN_MODE_SET_PAD1(line, gen_mode,pad1) \
+	FAST_GPFLAGSET(line, gen_mode,pad1,GEN_MODE_PAD1)
+
+#define SC_GEN_MODE_SET_RID(line, gen_mode,rid) \
+	FAST_GPFLAGSET(line, gen_mode,rid,GEN_MODE_RID)
+
+#define SC_GEN_MSLOC_SET_XS0(line, gen_msloc,xs0) \
+	FAST_GPFLAGSET(line, gen_msloc,xs0,GEN_MSLOC_XS0)
+
+#define SC_GEN_MSLOC_SET_YS0(line, gen_msloc,ys0) \
+	FAST_GPFLAGSET(line, gen_msloc,ys0,GEN_MSLOC_YS0)
+
+#define SC_GEN_MSLOC_SET_XS1(line, gen_msloc,xs1) \
+	FAST_GPFLAGSET(line, gen_msloc,xs1,GEN_MSLOC_XS1)
+
+#define SC_GEN_MSLOC_SET_YS1(line, gen_msloc,ys1) \
+	FAST_GPFLAGSET(line, gen_msloc,ys1,GEN_MSLOC_YS1)
+
+#define SC_GEN_MSLOC_SET_XS2(line, gen_msloc,xs2) \
+	FAST_GPFLAGSET(line, gen_msloc,xs2,GEN_MSLOC_XS2)
+
+#define SC_GEN_MSLOC_SET_YS2(line, gen_msloc,ys2) \
+	FAST_GPFLAGSET(line, gen_msloc,ys2,GEN_MSLOC_YS2)
+
+#define SC_GEN_MSLOC_SET_RID(line, gen_msloc,rid) \
+	FAST_GPFLAGSET(line, gen_msloc,rid,GEN_MSLOC_RID)
+
+#define SC_GEN_COLOR_SET_ALPHA(line, gen_color,alpha) \
+	FAST_GPFLAGSET(line, gen_color,alpha,GEN_COLOR_ALPHA)
+
+#define SC_GEN_COLOR_SET_BLUE(line, gen_color,blue) \
+	FAST_GPFLAGSET(line, gen_color,blue,GEN_COLOR_BLUE)
+
+#define SC_GEN_COLOR_SET_GREEN(line, gen_color,green) \
+	FAST_GPFLAGSET(line, gen_color,green,GEN_COLOR_GREEN)
+
+#define SC_GEN_COLOR_SET_RED(line, gen_color,red) \
+	FAST_GPFLAGSET(line, gen_color,red,GEN_COLOR_RED)
+
+#define SC_GEN_Z24_COLOR_SET_BLUE(line, gen_z24_color,blue) \
+	FAST_GPFLAGSET(line, gen_z24_color,blue,GEN_Z24_COLOR_BLUE)
+
+#define SC_GEN_Z24_COLOR_SET_GREEN(line, gen_z24_color,green) \
+	FAST_GPFLAGSET(line, gen_z24_color,green,GEN_Z24_COLOR_GREEN)
+
+#define SC_GEN_Z24_COLOR_SET_RED(line, gen_z24_color,red) \
+	FAST_GPFLAGSET(line, gen_z24_color,red,GEN_Z24_COLOR_RED)
+
+#define SC_GEN_Z24_COLOR_SET_PAD0(line, gen_z24_color,pad0) \
+	FAST_GPFLAGSET(line, gen_z24_color,pad0,GEN_Z24_COLOR_PAD0)
+
+#endif // GEN_REG_H
diff --git a/include/revolution/private/pe_reg.h b/include/revolution/private/pe_reg.h
new file mode 100644
index 0000000000..837948a38c
--- /dev/null
+++ b/include/revolution/private/pe_reg.h
@@ -0,0 +1,1160 @@
+#ifndef PE_REG_H
+#define PE_REG_H
+
+#include <revolution/private/GXFDLShortcut.h>
+
+#define PE_REFRESH_RID_SIZE     8
+#define PE_REFRESH_RID_SHIFT    24
+#define PE_REFRESH_RID_MASK     0xff000000
+#define PE_REFRESH_GET_RID(pe_refresh) \
+        ((((unsigned long)(pe_refresh)) & PE_REFRESH_RID_MASK) >> PE_REFRESH_RID_SHIFT)
+
+#define PE_REFRESH_ENABLE_SIZE  1
+#define PE_REFRESH_ENABLE_SHIFT 9
+#define PE_REFRESH_ENABLE_MASK  0x00000200
+#define PE_REFRESH_GET_ENABLE(pe_refresh) \
+        ((((unsigned long)(pe_refresh)) & PE_REFRESH_ENABLE_MASK) >> PE_REFRESH_ENABLE_SHIFT)
+
+#define PE_REFRESH_INTERVAL_SIZE        9
+#define PE_REFRESH_INTERVAL_SHIFT       0
+#define PE_REFRESH_INTERVAL_MASK        0x000001ff
+#define PE_REFRESH_GET_INTERVAL(pe_refresh) \
+        ((((unsigned long)(pe_refresh)) & PE_REFRESH_INTERVAL_MASK) >> PE_REFRESH_INTERVAL_SHIFT)
+
+#define PE_REFRESH_TOTAL_SIZE   32
+#define PE_REFRESH(interval, enable, rid) \
+        ((((unsigned long)(interval)) << PE_REFRESH_INTERVAL_SHIFT) | \
+         (((unsigned long)(enable)) << PE_REFRESH_ENABLE_SHIFT) | \
+         (((unsigned long)(rid)) << PE_REFRESH_RID_SHIFT))
+
+#define PE_CHICKEN_PIWR_SIZE	1
+#define PE_CHICKEN_PIWR_SHIFT	0
+#define PE_CHICKEN_PIWR_MASK	0x00000001
+#define PE_CHICKEN_GET_PIWR(pe_chicken) \
+	((((unsigned long)(pe_chicken)) & PE_CHICKEN_PIWR_MASK) >> PE_CHICKEN_PIWR_SHIFT)
+
+#define PE_CHICKEN_TXCPY_FMT_SIZE	1
+#define PE_CHICKEN_TXCPY_FMT_SHIFT	1
+#define PE_CHICKEN_TXCPY_FMT_MASK	0x00000002
+#define PE_CHICKEN_GET_TXCPY_FMT(pe_chicken) \
+    ((((unsigned long)(pe_chicken)) & PE_CHICKEN_TXCPY_FMT_MASK) >> PE_CHICKEN_TXCPY_FMT_SHIFT)
+
+#define PE_CHICKEN_TXCPY_CCV_SIZE	1
+#define PE_CHICKEN_TXCPY_CCV_SHIFT	2
+#define PE_CHICKEN_TXCPY_CCV_MASK	0x00000004
+#define PE_CHICKEN_GET_TXCPY_CCV(pe_chicken) \
+    ((((unsigned long)(pe_chicken)) & PE_CHICKEN_TXCPY_CCV_MASK) >> PE_CHICKEN_TXCPY_CCV_SHIFT)
+
+#define PE_CHICKEN_BLENDOP_SIZE	1
+#define PE_CHICKEN_BLENDOP_SHIFT	3
+#define PE_CHICKEN_BLENDOP_MASK	0x00000008
+#define PE_CHICKEN_GET_BLENDOP(pe_chicken) \
+	((((unsigned long)(pe_chicken)) & PE_CHICKEN_BLENDOP_MASK) >> PE_CHICKEN_BLENDOP_SHIFT)
+
+#define PE_CHICKEN_RID_SIZE	8
+#define PE_CHICKEN_RID_SHIFT	24
+#define PE_CHICKEN_RID_MASK	0xff000000
+#define PE_CHICKEN_GET_RID(pe_chicken) \
+    ((((unsigned long)(pe_chicken)) & PE_CHICKEN_RID_MASK) >> PE_CHICKEN_RID_SHIFT)
+
+#define PE_CMODE0_RID_SIZE      8
+#define PE_CMODE0_RID_SHIFT     24
+#define PE_CMODE0_RID_MASK      0xff000000
+#define PE_CMODE0_GET_RID(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_RID_MASK) >> PE_CMODE0_RID_SHIFT)
+
+#define PE_CMODE1_RID_SIZE      8
+#define PE_CMODE1_RID_SHIFT     24
+#define PE_CMODE1_RID_MASK      0xff000000
+#define PE_CMODE1_GET_RID(pe_cmode1) \
+        ((((unsigned long)(pe_cmode1)) & PE_CMODE1_RID_MASK) >> PE_CMODE1_RID_SHIFT)
+
+#define PE_ZMODE_RID_SIZE       8
+#define PE_ZMODE_RID_SHIFT      24
+#define PE_ZMODE_RID_MASK       0xff000000
+#define PE_ZMODE_GET_RID(pe_zmode) \
+        ((((unsigned long)(pe_zmode)) & PE_ZMODE_RID_MASK) >> PE_ZMODE_RID_SHIFT)
+
+#define PE_CONTROL_RID_SIZE     8
+#define PE_CONTROL_RID_SHIFT    24
+#define PE_CONTROL_RID_MASK     0xff000000
+#define PE_CONTROL_GET_RID(pe_control) \
+        ((((unsigned long)(pe_control)) & PE_CONTROL_RID_MASK) >> PE_CONTROL_RID_SHIFT)
+
+#define PE_COPY_CMD_GAMMA_SIZE  2
+#define PE_COPY_CMD_GAMMA_SHIFT 7
+#define PE_COPY_CMD_GAMMA_MASK  0x00000180
+#define PE_COPY_CMD_GET_GAMMA(pe_copy_cmd) \
+        ((((unsigned long)(pe_copy_cmd)) & PE_COPY_CMD_GAMMA_MASK) >> PE_COPY_CMD_GAMMA_SHIFT)
+
+#define PE_TOKEN_TOKEN_SIZE     16
+#define PE_TOKEN_TOKEN_SHIFT    0
+#define PE_TOKEN_TOKEN_MASK     0x0000ffff
+#define PE_TOKEN_GET_TOKEN(pe_token) \
+        ((((unsigned long)(pe_token)) & PE_TOKEN_TOKEN_MASK) >> PE_TOKEN_TOKEN_SHIFT)
+#define PE_TOKEN_SET_TOKEN(pe_token, token) { \
+        FDL_ASSERT(!((token) & ~((1 << PE_TOKEN_TOKEN_SIZE)-1))); \
+        pe_token = (((unsigned long)(pe_token)) & ~PE_TOKEN_TOKEN_MASK) | (((unsigned long)(token)) << PE_TOKEN_TOKEN_SHIFT);\
+}
+
+#define PE_TOKEN_RID_SIZE       8
+#define PE_TOKEN_RID_SHIFT      24
+#define PE_TOKEN_RID_MASK       0xff000000
+#define PE_TOKEN_GET_RID(pe_token) \
+        ((((unsigned long)(pe_token)) & PE_TOKEN_RID_MASK) >> PE_TOKEN_RID_SHIFT)
+#define PE_TOKEN_SET_RID(pe_token, rid) { \
+        FDL_ASSERT(!((rid) & ~((1 << PE_TOKEN_RID_SIZE)-1))); \
+        pe_token = (((unsigned long)(pe_token)) & ~PE_TOKEN_RID_MASK) | (((unsigned long)(rid)) << PE_TOKEN_RID_SHIFT);\
+}
+
+#define PE_TOKEN_INT_TOKEN_SIZE 16
+#define PE_TOKEN_INT_TOKEN_SHIFT        0
+#define PE_TOKEN_INT_TOKEN_MASK 0x0000ffff
+#define PE_TOKEN_INT_GET_TOKEN(pe_token_int) \
+        ((((unsigned long)(pe_token_int)) & PE_TOKEN_INT_TOKEN_MASK) >> PE_TOKEN_INT_TOKEN_SHIFT)
+#define PE_TOKEN_INT_SET_TOKEN(pe_token_int, token) { \
+        FDL_ASSERT(!((token) & ~((1 << PE_TOKEN_INT_TOKEN_SIZE)-1))); \
+        pe_token_int = (((unsigned long)(pe_token_int)) & ~PE_TOKEN_INT_TOKEN_MASK) | (((unsigned long)(token)) << PE_TOKEN_INT_TOKEN_SHIFT);\
+}
+
+#define PE_TOKEN_INT_RID_SIZE   8
+#define PE_TOKEN_INT_RID_SHIFT  24
+#define PE_TOKEN_INT_RID_MASK   0xff000000
+#define PE_TOKEN_INT_GET_RID(pe_token_int) \
+        ((((unsigned long)(pe_token_int)) & PE_TOKEN_INT_RID_MASK) >> PE_TOKEN_INT_RID_SHIFT)
+#define PE_TOKEN_INT_SET_RID(pe_token_int, rid) { \
+        FDL_ASSERT(!((rid) & ~((1 << PE_TOKEN_INT_RID_SIZE)-1))); \
+        pe_token_int = (((unsigned long)(pe_token_int)) & ~PE_TOKEN_INT_RID_MASK) | (((unsigned long)(rid)) << PE_TOKEN_INT_RID_SHIFT);\
+}
+#define PE_TOKEN_INT_TOTAL_SIZE 32
+#define PE_TOKEN_INT(token, rid) \
+        ((((unsigned long)(token)) << PE_TOKEN_INT_TOKEN_SHIFT) | \
+         (((unsigned long)(rid)) << PE_TOKEN_INT_RID_SHIFT))
+
+#define PE_FINISH_DST_SIZE      2
+#define PE_FINISH_DST_SHIFT     0
+#define PE_FINISH_DST_MASK      0x00000003
+#define PE_FINISH_GET_DST(pe_finish) \
+        ((((unsigned long)(pe_finish)) & PE_FINISH_DST_MASK) >> PE_FINISH_DST_SHIFT)
+#define PE_FINISH_SET_DST(pe_finish, dst) { \
+        FDL_ASSERT(!((dst) & ~((1 << PE_FINISH_DST_SIZE)-1))); \
+        pe_finish = (((unsigned long)(pe_finish)) & ~PE_FINISH_DST_MASK) | (((unsigned long)(dst)) << PE_FINISH_DST_SHIFT);\
+}
+#define PE_FINISH_PAD0_SIZE     22
+#define PE_FINISH_PAD0_SHIFT    2
+#define PE_FINISH_PAD0_MASK     0x00fffffc
+#define PE_FINISH_GET_PAD0(pe_finish) \
+        ((((unsigned long)(pe_finish)) & PE_FINISH_PAD0_MASK) >> PE_FINISH_PAD0_SHIFT)
+#define PE_FINISH_SET_PAD0(pe_finish, pad0) { \
+        FDL_ASSERT(!((pad0) & ~((1 << PE_FINISH_PAD0_SIZE)-1))); \
+        pe_finish = (((unsigned long)(pe_finish)) & ~PE_FINISH_PAD0_MASK) | (((unsigned long)(pad0)) << PE_FINISH_PAD0_SHIFT);\
+}
+#define PE_FINISH_RID_SIZE      8
+#define PE_FINISH_RID_SHIFT     24
+#define PE_FINISH_RID_MASK      0xff000000
+#define PE_FINISH_GET_RID(pe_finish) \
+        ((((unsigned long)(pe_finish)) & PE_FINISH_RID_MASK) >> PE_FINISH_RID_SHIFT)
+#define PE_FINISH_SET_RID(pe_finish, rid) { \
+        FDL_ASSERT(!((rid) & ~((1 << PE_FINISH_RID_SIZE)-1))); \
+        pe_finish = (((unsigned long)(pe_finish)) & ~PE_FINISH_RID_MASK) | (((unsigned long)(rid)) << PE_FINISH_RID_SHIFT);\
+}
+#define PE_FINISH_TOTAL_SIZE    32
+#define PE_FINISH(dst, rid) \
+        ((((unsigned long)(dst)) << PE_FINISH_DST_SHIFT) | \
+         (((unsigned long)(rid)) << PE_FINISH_RID_SHIFT))
+
+#define PE_PI_CTL_AFMT_SIZE	2
+#define PE_PI_CTL_AFMT_SHIFT	0
+#define PE_PI_CTL_AFMT_MASK	0x00000003
+#define PE_PI_CTL_GET_AFMT(pe_pi_ctl) \
+	((((unsigned long)(pe_pi_ctl)) & PE_PI_CTL_AFMT_MASK) >> PE_PI_CTL_AFMT_SHIFT)
+#define PE_PI_CTL_SET_AFMT(pe_pi_ctl, afmt) { \
+	FDL_ASSERT(!((afmt) & ~((1 << PE_PI_CTL_AFMT_SIZE)-1))); \
+	pe_pi_ctl = (((unsigned long)(pe_pi_ctl)) & ~PE_PI_CTL_AFMT_MASK) | (((unsigned long)(afmt)) << PE_PI_CTL_AFMT_SHIFT);\
+}
+#define PE_PI_CTL_ZFMT_SIZE	1
+#define PE_PI_CTL_ZFMT_SHIFT	2
+#define PE_PI_CTL_ZFMT_MASK	0x00000004
+#define PE_PI_CTL_GET_ZFMT(pe_pi_ctl) \
+	((((unsigned long)(pe_pi_ctl)) & PE_PI_CTL_ZFMT_MASK) >> PE_PI_CTL_ZFMT_SHIFT)
+#define PE_PI_CTL_SET_ZFMT(pe_pi_ctl, zfmt) { \
+	FDL_ASSERT(!((zfmt) & ~((1 << PE_PI_CTL_ZFMT_SIZE)-1))); \
+	pe_pi_ctl = (((unsigned long)(pe_pi_ctl)) & ~PE_PI_CTL_ZFMT_MASK) | (((unsigned long)(zfmt)) << PE_PI_CTL_ZFMT_SHIFT);\
+}
+#define PE_PI_CTL_PAD0_SIZE	21
+#define PE_PI_CTL_PAD0_SHIFT	3
+#define PE_PI_CTL_PAD0_MASK	0x00fffff8
+#define PE_PI_CTL_GET_PAD0(pe_pi_ctl) \
+	((((unsigned long)(pe_pi_ctl)) & PE_PI_CTL_PAD0_MASK) >> PE_PI_CTL_PAD0_SHIFT)
+#define PE_PI_CTL_SET_PAD0(pe_pi_ctl, pad0) { \
+	FDL_ASSERT(!((pad0) & ~((1 << PE_PI_CTL_PAD0_SIZE)-1))); \
+	pe_pi_ctl = (((unsigned long)(pe_pi_ctl)) & ~PE_PI_CTL_PAD0_MASK) | (((unsigned long)(pad0)) << PE_PI_CTL_PAD0_SHIFT);\
+}
+#define PE_PI_CTL_RID_SIZE	8
+#define PE_PI_CTL_RID_SHIFT	24
+#define PE_PI_CTL_RID_MASK	0xff000000
+#define PE_PI_CTL_GET_RID(pe_pi_ctl) \
+	((((unsigned long)(pe_pi_ctl)) & PE_PI_CTL_RID_MASK) >> PE_PI_CTL_RID_SHIFT)
+#define PE_PI_CTL_SET_RID(pe_pi_ctl, rid) { \
+	FDL_ASSERT(!((rid) & ~((1 << PE_PI_CTL_RID_SIZE)-1))); \
+	pe_pi_ctl = (((unsigned long)(pe_pi_ctl)) & ~PE_PI_CTL_RID_MASK) | (((unsigned long)(rid)) << PE_PI_CTL_RID_SHIFT);\
+}
+#define PE_PI_CTL_TOTAL_SIZE	32
+#define PE_PI_CTL(afmt, zfmt, rid) \
+	((((unsigned long)(afmt)) << PE_PI_CTL_AFMT_SHIFT) | \
+	 (((unsigned long)(zfmt)) << PE_PI_CTL_ZFMT_SHIFT) | \
+	 (((unsigned long)(rid)) << PE_PI_CTL_RID_SHIFT))
+
+#define PE_CMODE0_BLEND_ENABLE_SIZE     1
+#define PE_CMODE0_BLEND_ENABLE_SHIFT    0
+#define PE_CMODE0_BLEND_ENABLE_MASK     0x00000001
+#define PE_CMODE0_GET_BLEND_ENABLE(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_BLEND_ENABLE_MASK) >> PE_CMODE0_BLEND_ENABLE_SHIFT)
+#define PE_CMODE0_SET_BLEND_ENABLE(pe_cmode0, blend_enable) { \
+        FDL_ASSERT(!((blend_enable) & ~((1 << PE_CMODE0_BLEND_ENABLE_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_BLEND_ENABLE_MASK) | (((unsigned long)(blend_enable)) << PE_CMODE0_BLEND_ENABLE_SHIFT);\
+}
+#define PE_CMODE0_LOGICOP_ENABLE_SIZE   1
+#define PE_CMODE0_LOGICOP_ENABLE_SHIFT  1
+#define PE_CMODE0_LOGICOP_ENABLE_MASK   0x00000002
+#define PE_CMODE0_GET_LOGICOP_ENABLE(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_LOGICOP_ENABLE_MASK) >> PE_CMODE0_LOGICOP_ENABLE_SHIFT)
+#define PE_CMODE0_SET_LOGICOP_ENABLE(pe_cmode0, logicop_enable) { \
+        FDL_ASSERT(!((logicop_enable) & ~((1 << PE_CMODE0_LOGICOP_ENABLE_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_LOGICOP_ENABLE_MASK) | (((unsigned long)(logicop_enable)) << PE_CMODE0_LOGICOP_ENABLE_SHIFT);\
+}
+#define PE_CMODE0_DITHER_ENABLE_SIZE    1
+#define PE_CMODE0_DITHER_ENABLE_SHIFT   2
+#define PE_CMODE0_DITHER_ENABLE_MASK    0x00000004
+#define PE_CMODE0_GET_DITHER_ENABLE(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_DITHER_ENABLE_MASK) >> PE_CMODE0_DITHER_ENABLE_SHIFT)
+#define PE_CMODE0_SET_DITHER_ENABLE(pe_cmode0, dither_enable) { \
+        FDL_ASSERT(!((dither_enable) & ~((1 << PE_CMODE0_DITHER_ENABLE_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_DITHER_ENABLE_MASK) | (((unsigned long)(dither_enable)) << PE_CMODE0_DITHER_ENABLE_SHIFT);\
+}
+#define PE_CMODE0_COLOR_MASK_SIZE       1
+#define PE_CMODE0_COLOR_MASK_SHIFT      3
+#define PE_CMODE0_COLOR_MASK_MASK       0x00000008
+#define PE_CMODE0_GET_COLOR_MASK(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_COLOR_MASK_MASK) >> PE_CMODE0_COLOR_MASK_SHIFT)
+#define PE_CMODE0_SET_COLOR_MASK(pe_cmode0, color_mask) { \
+        FDL_ASSERT(!((color_mask) & ~((1 << PE_CMODE0_COLOR_MASK_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_COLOR_MASK_MASK) | (((unsigned long)(color_mask)) << PE_CMODE0_COLOR_MASK_SHIFT);\
+}
+#define PE_CMODE0_ALPHA_MASK_SIZE       1
+#define PE_CMODE0_ALPHA_MASK_SHIFT      4
+#define PE_CMODE0_ALPHA_MASK_MASK       0x00000010
+#define PE_CMODE0_GET_ALPHA_MASK(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_ALPHA_MASK_MASK) >> PE_CMODE0_ALPHA_MASK_SHIFT)
+#define PE_CMODE0_SET_ALPHA_MASK(pe_cmode0, alpha_mask) { \
+        FDL_ASSERT(!((alpha_mask) & ~((1 << PE_CMODE0_ALPHA_MASK_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_ALPHA_MASK_MASK) | (((unsigned long)(alpha_mask)) << PE_CMODE0_ALPHA_MASK_SHIFT);\
+}
+#define PE_CMODE0_DFACTOR_SIZE  3
+#define PE_CMODE0_DFACTOR_SHIFT 5
+#define PE_CMODE0_DFACTOR_MASK  0x000000e0
+#define PE_CMODE0_GET_DFACTOR(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_DFACTOR_MASK) >> PE_CMODE0_DFACTOR_SHIFT)
+#define PE_CMODE0_SET_DFACTOR(pe_cmode0, dfactor) { \
+        FDL_ASSERT(!((dfactor) & ~((1 << PE_CMODE0_DFACTOR_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_DFACTOR_MASK) | (((unsigned long)(dfactor)) << PE_CMODE0_DFACTOR_SHIFT);\
+}
+#define PE_CMODE0_SFACTOR_SIZE  3
+#define PE_CMODE0_SFACTOR_SHIFT 8
+#define PE_CMODE0_SFACTOR_MASK  0x00000700
+#define PE_CMODE0_GET_SFACTOR(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_SFACTOR_MASK) >> PE_CMODE0_SFACTOR_SHIFT)
+#define PE_CMODE0_SET_SFACTOR(pe_cmode0, sfactor) { \
+        FDL_ASSERT(!((sfactor) & ~((1 << PE_CMODE0_SFACTOR_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_SFACTOR_MASK) | (((unsigned long)(sfactor)) << PE_CMODE0_SFACTOR_SHIFT);\
+}
+#define PE_CMODE0_BLENDOP_SIZE  1
+#define PE_CMODE0_BLENDOP_SHIFT 11
+#define PE_CMODE0_BLENDOP_MASK  0x00000800
+#define PE_CMODE0_GET_BLENDOP(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_BLENDOP_MASK) >> PE_CMODE0_BLENDOP_SHIFT)
+#define PE_CMODE0_SET_BLENDOP(pe_cmode0, blendop) { \
+        FDL_ASSERT(!((blendop) & ~((1 << PE_CMODE0_BLENDOP_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_BLENDOP_MASK) | (((unsigned long)(blendop)) << PE_CMODE0_BLENDOP_SHIFT);\
+}
+#define PE_CMODE0_LOGICOP_SIZE  4
+#define PE_CMODE0_LOGICOP_SHIFT 12
+#define PE_CMODE0_LOGICOP_MASK  0x0000f000
+#define PE_CMODE0_GET_LOGICOP(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_LOGICOP_MASK) >> PE_CMODE0_LOGICOP_SHIFT)
+#define PE_CMODE0_SET_LOGICOP(pe_cmode0, logicop) { \
+        FDL_ASSERT(!((logicop) & ~((1 << PE_CMODE0_LOGICOP_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_LOGICOP_MASK) | (((unsigned long)(logicop)) << PE_CMODE0_LOGICOP_SHIFT);\
+}
+#define PE_CMODE0_PAD0_SIZE     8
+#define PE_CMODE0_PAD0_SHIFT    16
+#define PE_CMODE0_PAD0_MASK     0x00ff0000
+#define PE_CMODE0_GET_PAD0(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_PAD0_MASK) >> PE_CMODE0_PAD0_SHIFT)
+#define PE_CMODE0_SET_PAD0(pe_cmode0, pad0) { \
+        FDL_ASSERT(!((pad0) & ~((1 << PE_CMODE0_PAD0_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_PAD0_MASK) | (((unsigned long)(pad0)) << PE_CMODE0_PAD0_SHIFT);\
+}
+#define PE_CMODE0_RID_SIZE      8
+#define PE_CMODE0_RID_SHIFT     24
+#define PE_CMODE0_RID_MASK      0xff000000
+#define PE_CMODE0_GET_RID(pe_cmode0) \
+        ((((unsigned long)(pe_cmode0)) & PE_CMODE0_RID_MASK) >> PE_CMODE0_RID_SHIFT)
+#define PE_CMODE0_SET_RID(pe_cmode0, rid) { \
+        FDL_ASSERT(!((rid) & ~((1 << PE_CMODE0_RID_SIZE)-1))); \
+        pe_cmode0 = (((unsigned long)(pe_cmode0)) & ~PE_CMODE0_RID_MASK) | (((unsigned long)(rid)) << PE_CMODE0_RID_SHIFT);\
+}
+#define PE_CMODE0_TOTAL_SIZE    32
+#define PE_CMODE0(blend_enable, logicop_enable, dither_enable, color_mask, alpha_mask, dfactor, sfactor, blendop, logicop, rid) \
+        ((((unsigned long)(blend_enable)) << PE_CMODE0_BLEND_ENABLE_SHIFT) | \
+         (((unsigned long)(logicop_enable)) << PE_CMODE0_LOGICOP_ENABLE_SHIFT) | \
+         (((unsigned long)(dither_enable)) << PE_CMODE0_DITHER_ENABLE_SHIFT) | \
+         (((unsigned long)(color_mask)) << PE_CMODE0_COLOR_MASK_SHIFT) | \
+         (((unsigned long)(alpha_mask)) << PE_CMODE0_ALPHA_MASK_SHIFT) | \
+         (((unsigned long)(dfactor)) << PE_CMODE0_DFACTOR_SHIFT) | \
+         (((unsigned long)(sfactor)) << PE_CMODE0_SFACTOR_SHIFT) | \
+         (((unsigned long)(blendop)) << PE_CMODE0_BLENDOP_SHIFT) | \
+         (((unsigned long)(logicop)) << PE_CMODE0_LOGICOP_SHIFT) | \
+         (((unsigned long)(rid)) << PE_CMODE0_RID_SHIFT))
+
+#define PE_CMODE1_CONSTANT_ALPHA_SIZE   8
+#define PE_CMODE1_CONSTANT_ALPHA_SHIFT  0
+#define PE_CMODE1_CONSTANT_ALPHA_MASK   0x000000ff
+#define PE_CMODE1_GET_CONSTANT_ALPHA(pe_cmode1) \
+        ((((unsigned long)(pe_cmode1)) & PE_CMODE1_CONSTANT_ALPHA_MASK) >> PE_CMODE1_CONSTANT_ALPHA_SHIFT)
+#define PE_CMODE1_SET_CONSTANT_ALPHA(pe_cmode1, constant_alpha) { \
+        FDL_ASSERT(!((constant_alpha) & ~((1 << PE_CMODE1_CONSTANT_ALPHA_SIZE)-1))); \
+        pe_cmode1 = (((unsigned long)(pe_cmode1)) & ~PE_CMODE1_CONSTANT_ALPHA_MASK) | (((unsigned long)(constant_alpha)) << PE_CMODE1_CONSTANT_ALPHA_SHIFT);\
+}
+#define PE_CMODE1_CONSTANT_ALPHA_ENABLE_SIZE    1
+#define PE_CMODE1_CONSTANT_ALPHA_ENABLE_SHIFT   8
+#define PE_CMODE1_CONSTANT_ALPHA_ENABLE_MASK    0x00000100
+#define PE_CMODE1_GET_CONSTANT_ALPHA_ENABLE(pe_cmode1) \
+        ((((unsigned long)(pe_cmode1)) & PE_CMODE1_CONSTANT_ALPHA_ENABLE_MASK) >> PE_CMODE1_CONSTANT_ALPHA_ENABLE_SHIFT)
+#define PE_CMODE1_SET_CONSTANT_ALPHA_ENABLE(pe_cmode1, constant_alpha_enable) { \
+        FDL_ASSERT(!((constant_alpha_enable) & ~((1 << PE_CMODE1_CONSTANT_ALPHA_ENABLE_SIZE)-1))); \
+        pe_cmode1 = (((unsigned long)(pe_cmode1)) & ~PE_CMODE1_CONSTANT_ALPHA_ENABLE_MASK) | (((unsigned long)(constant_alpha_enable)) << PE_CMODE1_CONSTANT_ALPHA_ENABLE_SHIFT);\
+}
+#define PE_CMODE1_YUV_SIZE      2
+#define PE_CMODE1_YUV_SHIFT     9
+#define PE_CMODE1_YUV_MASK      0x00000600
+#define PE_CMODE1_GET_YUV(pe_cmode1) \
+        ((((unsigned long)(pe_cmode1)) & PE_CMODE1_YUV_MASK) >> PE_CMODE1_YUV_SHIFT)
+#define PE_CMODE1_SET_YUV(pe_cmode1, yuv) { \
+        FDL_ASSERT(!((yuv) & ~((1 << PE_CMODE1_YUV_SIZE)-1))); \
+        pe_cmode1 = (((unsigned long)(pe_cmode1)) & ~PE_CMODE1_YUV_MASK) | (((unsigned long)(yuv)) << PE_CMODE1_YUV_SHIFT);\
+}
+#define PE_CMODE1_PAD0_SIZE     13
+#define PE_CMODE1_PAD0_SHIFT    11
+#define PE_CMODE1_PAD0_MASK     0x00fff800
+#define PE_CMODE1_GET_PAD0(pe_cmode1) \
+        ((((unsigned long)(pe_cmode1)) & PE_CMODE1_PAD0_MASK) >> PE_CMODE1_PAD0_SHIFT)
+#define PE_CMODE1_SET_PAD0(pe_cmode1, pad0) { \
+        FDL_ASSERT(!((pad0) & ~((1 << PE_CMODE1_PAD0_SIZE)-1))); \
+        pe_cmode1 = (((unsigned long)(pe_cmode1)) & ~PE_CMODE1_PAD0_MASK) | (((unsigned long)(pad0)) << PE_CMODE1_PAD0_SHIFT);\
+}
+#define PE_CMODE1_RID_SIZE      8
+#define PE_CMODE1_RID_SHIFT     24
+#define PE_CMODE1_RID_MASK      0xff000000
+#define PE_CMODE1_GET_RID(pe_cmode1) \
+        ((((unsigned long)(pe_cmode1)) & PE_CMODE1_RID_MASK) >> PE_CMODE1_RID_SHIFT)
+#define PE_CMODE1_SET_RID(pe_cmode1, rid) { \
+        FDL_ASSERT(!((rid) & ~((1 << PE_CMODE1_RID_SIZE)-1))); \
+        pe_cmode1 = (((unsigned long)(pe_cmode1)) & ~PE_CMODE1_RID_MASK) | (((unsigned long)(rid)) << PE_CMODE1_RID_SHIFT);\
+}
+#define PE_CMODE1_TOTAL_SIZE    32
+#define PE_CMODE1(constant_alpha, constant_alpha_enable, yuv, rid) \
+        ((((unsigned long)(constant_alpha)) << PE_CMODE1_CONSTANT_ALPHA_SHIFT) | \
+         (((unsigned long)(constant_alpha_enable)) << PE_CMODE1_CONSTANT_ALPHA_ENABLE_SHIFT) | \
+         (((unsigned long)(yuv)) << PE_CMODE1_YUV_SHIFT) | \
+         (((unsigned long)(rid)) << PE_CMODE1_RID_SHIFT))
+
+#define PE_ZMODE_ENABLE_SIZE    1
+#define PE_ZMODE_ENABLE_SHIFT   0
+#define PE_ZMODE_ENABLE_MASK    0x00000001
+#define PE_ZMODE_GET_ENABLE(pe_zmode) \
+        ((((unsigned long)(pe_zmode)) & PE_ZMODE_ENABLE_MASK) >> PE_ZMODE_ENABLE_SHIFT)
+#define PE_ZMODE_SET_ENABLE(pe_zmode, enable) { \
+        FDL_ASSERT(!((enable) & ~((1 << PE_ZMODE_ENABLE_SIZE)-1))); \
+        pe_zmode = (((unsigned long)(pe_zmode)) & ~PE_ZMODE_ENABLE_MASK) | (((unsigned long)(enable)) << PE_ZMODE_ENABLE_SHIFT);\
+}
+#define PE_ZMODE_FUNC_SIZE      3
+#define PE_ZMODE_FUNC_SHIFT     1
+#define PE_ZMODE_FUNC_MASK      0x0000000e
+#define PE_ZMODE_GET_FUNC(pe_zmode) \
+        ((((unsigned long)(pe_zmode)) & PE_ZMODE_FUNC_MASK) >> PE_ZMODE_FUNC_SHIFT)
+#define PE_ZMODE_SET_FUNC(pe_zmode, func) { \
+        FDL_ASSERT(!((func) & ~((1 << PE_ZMODE_FUNC_SIZE)-1))); \
+        pe_zmode = (((unsigned long)(pe_zmode)) & ~PE_ZMODE_FUNC_MASK) | (((unsigned long)(func)) << PE_ZMODE_FUNC_SHIFT);\
+}
+#define PE_ZMODE_MASK_SIZE      1
+#define PE_ZMODE_MASK_SHIFT     4
+#define PE_ZMODE_MASK_MASK      0x00000010
+#define PE_ZMODE_GET_MASK(pe_zmode) \
+        ((((unsigned long)(pe_zmode)) & PE_ZMODE_MASK_MASK) >> PE_ZMODE_MASK_SHIFT)
+#define PE_ZMODE_SET_MASK(pe_zmode, mask) { \
+        FDL_ASSERT(!((mask) & ~((1 << PE_ZMODE_MASK_SIZE)-1))); \
+        pe_zmode = (((unsigned long)(pe_zmode)) & ~PE_ZMODE_MASK_MASK) | (((unsigned long)(mask)) << PE_ZMODE_MASK_SHIFT);\
+}
+#define PE_ZMODE_PAD0_SIZE      19
+#define PE_ZMODE_PAD0_SHIFT     5
+#define PE_ZMODE_PAD0_MASK      0x00ffffe0
+#define PE_ZMODE_GET_PAD0(pe_zmode) \
+        ((((unsigned long)(pe_zmode)) & PE_ZMODE_PAD0_MASK) >> PE_ZMODE_PAD0_SHIFT)
+#define PE_ZMODE_SET_PAD0(pe_zmode, pad0) { \
+        FDL_ASSERT(!((pad0) & ~((1 << PE_ZMODE_PAD0_SIZE)-1))); \
+        pe_zmode = (((unsigned long)(pe_zmode)) & ~PE_ZMODE_PAD0_MASK) | (((unsigned long)(pad0)) << PE_ZMODE_PAD0_SHIFT);\
+}
+#define PE_ZMODE_RID_SIZE       8
+#define PE_ZMODE_RID_SHIFT      24
+#define PE_ZMODE_RID_MASK       0xff000000
+#define PE_ZMODE_GET_RID(pe_zmode) \
+        ((((unsigned long)(pe_zmode)) & PE_ZMODE_RID_MASK) >> PE_ZMODE_RID_SHIFT)
+#define PE_ZMODE_SET_RID(pe_zmode, rid) { \
+        FDL_ASSERT(!((rid) & ~((1 << PE_ZMODE_RID_SIZE)-1))); \
+        pe_zmode = (((unsigned long)(pe_zmode)) & ~PE_ZMODE_RID_MASK) | (((unsigned long)(rid)) << PE_ZMODE_RID_SHIFT);\
+}
+#define PE_ZMODE_TOTAL_SIZE     32
+#define PE_ZMODE(enable, func, mask, rid) \
+        ((((unsigned long)(enable)) << PE_ZMODE_ENABLE_SHIFT) | \
+         (((unsigned long)(func)) << PE_ZMODE_FUNC_SHIFT) | \
+         (((unsigned long)(mask)) << PE_ZMODE_MASK_SHIFT) | \
+         (((unsigned long)(rid)) << PE_ZMODE_RID_SHIFT))
+
+#define PE_PI_EFB_ADDR_PAD0_SIZE	2
+#define PE_PI_EFB_ADDR_PAD0_SHIFT	0
+#define PE_PI_EFB_ADDR_PAD0_MASK	0x00000003
+#define PE_PI_EFB_ADDR_GET_PAD0(pe_pi_efb_addr) \
+	((((unsigned long)(pe_pi_efb_addr)) & PE_PI_EFB_ADDR_PAD0_MASK) >> PE_PI_EFB_ADDR_PAD0_SHIFT)
+#define PE_PI_EFB_ADDR_SET_PAD0(pe_pi_efb_addr, pad0) { \
+	FDL_ASSERT(!((pad0) & ~((1 << PE_PI_EFB_ADDR_PAD0_SIZE)-1))); \
+	pe_pi_efb_addr = (((unsigned long)(pe_pi_efb_addr)) & ~PE_PI_EFB_ADDR_PAD0_MASK) | (((unsigned long)(pad0)) << PE_PI_EFB_ADDR_PAD0_SHIFT);\
+}
+#define PE_PI_EFB_ADDR_X_SIZE	10
+#define PE_PI_EFB_ADDR_X_SHIFT	2
+#define PE_PI_EFB_ADDR_X_MASK	0x00000ffc
+#define PE_PI_EFB_ADDR_GET_X(pe_pi_efb_addr) \
+	((((unsigned long)(pe_pi_efb_addr)) & PE_PI_EFB_ADDR_X_MASK) >> PE_PI_EFB_ADDR_X_SHIFT)
+#define PE_PI_EFB_ADDR_SET_X(pe_pi_efb_addr, x) { \
+	FDL_ASSERT(!((x) & ~((1 << PE_PI_EFB_ADDR_X_SIZE)-1))); \
+	pe_pi_efb_addr = (((unsigned long)(pe_pi_efb_addr)) & ~PE_PI_EFB_ADDR_X_MASK) | (((unsigned long)(x)) << PE_PI_EFB_ADDR_X_SHIFT);\
+}
+#define PE_PI_EFB_ADDR_Y_SIZE	10
+#define PE_PI_EFB_ADDR_Y_SHIFT	12
+#define PE_PI_EFB_ADDR_Y_MASK	0x003ff000
+#define PE_PI_EFB_ADDR_GET_Y(pe_pi_efb_addr) \
+	((((unsigned long)(pe_pi_efb_addr)) & PE_PI_EFB_ADDR_Y_MASK) >> PE_PI_EFB_ADDR_Y_SHIFT)
+#define PE_PI_EFB_ADDR_SET_Y(pe_pi_efb_addr, y) { \
+	FDL_ASSERT(!((y) & ~((1 << PE_PI_EFB_ADDR_Y_SIZE)-1))); \
+	pe_pi_efb_addr = (((unsigned long)(pe_pi_efb_addr)) & ~PE_PI_EFB_ADDR_Y_MASK) | (((unsigned long)(y)) << PE_PI_EFB_ADDR_Y_SHIFT);\
+}
+#define PE_PI_EFB_ADDR_TYPE_SIZE	2
+#define PE_PI_EFB_ADDR_TYPE_SHIFT	22
+#define PE_PI_EFB_ADDR_TYPE_MASK	0x00c00000
+#define PE_PI_EFB_ADDR_GET_TYPE(pe_pi_efb_addr) \
+	((((unsigned long)(pe_pi_efb_addr)) & PE_PI_EFB_ADDR_TYPE_MASK) >> PE_PI_EFB_ADDR_TYPE_SHIFT)
+#define PE_PI_EFB_ADDR_SET_TYPE(pe_pi_efb_addr, type) { \
+	FDL_ASSERT(!((type) & ~((1 << PE_PI_EFB_ADDR_TYPE_SIZE)-1))); \
+	pe_pi_efb_addr = (((unsigned long)(pe_pi_efb_addr)) & ~PE_PI_EFB_ADDR_TYPE_MASK) | (((unsigned long)(type)) << PE_PI_EFB_ADDR_TYPE_SHIFT);\
+}
+#define PE_PI_EFB_ADDR_TOTAL_SIZE	24
+#define PE_PI_EFB_ADDR(x, y, type) \
+	((((unsigned long)(x)) << PE_PI_EFB_ADDR_X_SHIFT) | \
+	 (((unsigned long)(y)) << PE_PI_EFB_ADDR_Y_SHIFT) | \
+	 (((unsigned long)(type)) << PE_PI_EFB_ADDR_TYPE_SHIFT))
+
+#define PE_INTRCTL_INT0EN_SIZE	1
+#define PE_INTRCTL_INT0EN_SHIFT	0
+#define PE_INTRCTL_INT0EN_MASK	0x00000001
+#define PE_INTRCTL_GET_INT0EN(pe_intrctl) \
+	((((unsigned long)(pe_intrctl)) & PE_INTRCTL_INT0EN_MASK) >> PE_INTRCTL_INT0EN_SHIFT)
+#define PE_INTRCTL_SET_INT0EN(pe_intrctl, int0en) { \
+	FDL_ASSERT(!((int0en) & ~((1 << PE_INTRCTL_INT0EN_SIZE)-1))); \
+	pe_intrctl = (((unsigned long)(pe_intrctl)) & ~PE_INTRCTL_INT0EN_MASK) | (((unsigned long)(int0en)) << PE_INTRCTL_INT0EN_SHIFT);\
+}
+#define PE_INTRCTL_INT1EN_SIZE	1
+#define PE_INTRCTL_INT1EN_SHIFT	1
+#define PE_INTRCTL_INT1EN_MASK	0x00000002
+#define PE_INTRCTL_GET_INT1EN(pe_intrctl) \
+	((((unsigned long)(pe_intrctl)) & PE_INTRCTL_INT1EN_MASK) >> PE_INTRCTL_INT1EN_SHIFT)
+#define PE_INTRCTL_SET_INT1EN(pe_intrctl, int1en) { \
+	FDL_ASSERT(!((int1en) & ~((1 << PE_INTRCTL_INT1EN_SIZE)-1))); \
+	pe_intrctl = (((unsigned long)(pe_intrctl)) & ~PE_INTRCTL_INT1EN_MASK) | (((unsigned long)(int1en)) << PE_INTRCTL_INT1EN_SHIFT);\
+}
+#define PE_INTRCTL_INT0CLR_SIZE	1
+#define PE_INTRCTL_INT0CLR_SHIFT	2
+#define PE_INTRCTL_INT0CLR_MASK	0x00000004
+#define PE_INTRCTL_GET_INT0CLR(pe_intrctl) \
+	((((unsigned long)(pe_intrctl)) & PE_INTRCTL_INT0CLR_MASK) >> PE_INTRCTL_INT0CLR_SHIFT)
+#define PE_INTRCTL_SET_INT0CLR(pe_intrctl, int0clr) { \
+	FDL_ASSERT(!((int0clr) & ~((1 << PE_INTRCTL_INT0CLR_SIZE)-1))); \
+	pe_intrctl = (((unsigned long)(pe_intrctl)) & ~PE_INTRCTL_INT0CLR_MASK) | (((unsigned long)(int0clr)) << PE_INTRCTL_INT0CLR_SHIFT);\
+}
+#define PE_INTRCTL_INT1CLR_SIZE	1
+#define PE_INTRCTL_INT1CLR_SHIFT	3
+#define PE_INTRCTL_INT1CLR_MASK	0x00000008
+#define PE_INTRCTL_GET_INT1CLR(pe_intrctl) \
+	((((unsigned long)(pe_intrctl)) & PE_INTRCTL_INT1CLR_MASK) >> PE_INTRCTL_INT1CLR_SHIFT)
+#define PE_INTRCTL_SET_INT1CLR(pe_intrctl, int1clr) { \
+	FDL_ASSERT(!((int1clr) & ~((1 << PE_INTRCTL_INT1CLR_SIZE)-1))); \
+	pe_intrctl = (((unsigned long)(pe_intrctl)) & ~PE_INTRCTL_INT1CLR_MASK) | (((unsigned long)(int1clr)) << PE_INTRCTL_INT1CLR_SHIFT);\
+}
+#define PE_INTRCTL_TOTAL_SIZE	4
+#define PE_INTRCTL(int0en, int1en, int0clr, int1clr) \
+	((((unsigned long)(int0en)) << PE_INTRCTL_INT0EN_SHIFT) | \
+	 (((unsigned long)(int1en)) << PE_INTRCTL_INT1EN_SHIFT) | \
+	 (((unsigned long)(int0clr)) << PE_INTRCTL_INT0CLR_SHIFT) | \
+	 (((unsigned long)(int1clr)) << PE_INTRCTL_INT1CLR_SHIFT))
+
+#define SC_PE_ZMODE_SET_ENABLE(line, pe_zmode,enable) \
+	FAST_GPFLAGSET(line, pe_zmode,enable,PE_ZMODE_ENABLE)
+
+#define SC_PE_ZMODE_SET_FUNC(line, pe_zmode,func) \
+	FAST_GPFLAGSET(line, pe_zmode,func,PE_ZMODE_FUNC)
+
+#define SC_PE_ZMODE_SET_MASK(line, pe_zmode,mask) \
+	FAST_GPFLAGSET(line, pe_zmode,mask,PE_ZMODE_MASK)
+
+#define SC_PE_ZMODE_SET_PAD0(line, pe_zmode,pad0) \
+	FAST_GPFLAGSET(line, pe_zmode,pad0,PE_ZMODE_PAD0)
+
+#define SC_PE_ZMODE_SET_RID(line, pe_zmode,rid) \
+	FAST_GPFLAGSET(line, pe_zmode,rid,PE_ZMODE_RID)
+
+#define SC_PE_CMODE0_SET_BLEND_ENABLE(line, pe_cmode0,blend_enable) \
+	FAST_GPFLAGSET(line, pe_cmode0,blend_enable,PE_CMODE0_BLEND_ENABLE)
+
+#define SC_PE_CMODE0_SET_LOGICOP_ENABLE(line, pe_cmode0,logicop_enable) \
+	FAST_GPFLAGSET(line, pe_cmode0,logicop_enable,PE_CMODE0_LOGICOP_ENABLE)
+
+#define SC_PE_CMODE0_SET_DITHER_ENABLE(line, pe_cmode0,dither_enable) \
+	FAST_GPFLAGSET(line, pe_cmode0,dither_enable,PE_CMODE0_DITHER_ENABLE)
+
+#define SC_PE_CMODE0_SET_COLOR_MASK(line, pe_cmode0,color_mask) \
+	FAST_GPFLAGSET(line, pe_cmode0,color_mask,PE_CMODE0_COLOR_MASK)
+
+#define SC_PE_CMODE0_SET_ALPHA_MASK(line, pe_cmode0,alpha_mask) \
+	FAST_GPFLAGSET(line, pe_cmode0,alpha_mask,PE_CMODE0_ALPHA_MASK)
+
+#define SC_PE_CMODE0_SET_DFACTOR(line, pe_cmode0,dfactor) \
+	FAST_GPFLAGSET(line, pe_cmode0,dfactor,PE_CMODE0_DFACTOR)
+
+#define SC_PE_CMODE0_SET_SFACTOR(line, pe_cmode0,sfactor) \
+	FAST_GPFLAGSET(line, pe_cmode0,sfactor,PE_CMODE0_SFACTOR)
+
+#define SC_PE_CMODE0_SET_BLENDOP(line, pe_cmode0,blendop) \
+	FAST_GPFLAGSET(line, pe_cmode0,blendop,PE_CMODE0_BLENDOP)
+
+#define SC_PE_CMODE0_SET_LOGICOP(line, pe_cmode0,logicop) \
+	FAST_GPFLAGSET(line, pe_cmode0,logicop,PE_CMODE0_LOGICOP)
+
+#define SC_PE_CMODE0_SET_PAD0(line, pe_cmode0,pad0) \
+	FAST_GPFLAGSET(line, pe_cmode0,pad0,PE_CMODE0_PAD0)
+
+#define SC_PE_CMODE0_SET_RID(line, pe_cmode0,rid) \
+	FAST_GPFLAGSET(line, pe_cmode0,rid,PE_CMODE0_RID)
+
+#define SC_PE_CMODE1_SET_CONSTANT_ALPHA(line, pe_cmode1,constant_alpha) \
+	FAST_GPFLAGSET(line, pe_cmode1,constant_alpha,PE_CMODE1_CONSTANT_ALPHA)
+
+#define SC_PE_CMODE1_SET_CONSTANT_ALPHA_ENABLE(line, pe_cmode1,constant_alpha_enable) \
+	FAST_GPFLAGSET(line, pe_cmode1,constant_alpha_enable,PE_CMODE1_CONSTANT_ALPHA_ENABLE)
+
+#define SC_PE_CMODE1_SET_YUV(line, pe_cmode1,yuv) \
+	FAST_GPFLAGSET(line, pe_cmode1,yuv,PE_CMODE1_YUV)
+
+#define SC_PE_CMODE1_SET_PAD0(line, pe_cmode1,pad0) \
+	FAST_GPFLAGSET(line, pe_cmode1,pad0,PE_CMODE1_PAD0)
+
+#define SC_PE_CMODE1_SET_RID(line, pe_cmode1,rid) \
+	FAST_GPFLAGSET(line, pe_cmode1,rid,PE_CMODE1_RID)
+
+#define SC_PE_CONTROL_SET_PIXTYPE(line, pe_control,pixtype) \
+	FAST_GPFLAGSET(line, pe_control,pixtype,PE_CONTROL_PIXTYPE)
+
+#define SC_PE_CONTROL_SET_ZCMODE(line, pe_control,zcmode) \
+	FAST_GPFLAGSET(line, pe_control,zcmode,PE_CONTROL_ZCMODE)
+
+#define SC_PE_CONTROL_SET_ZTOP(line, pe_control,ztop) \
+	FAST_GPFLAGSET(line, pe_control,ztop,PE_CONTROL_ZTOP)
+
+#define SC_PE_CONTROL_SET_PAD0(line, pe_control,pad0) \
+	FAST_GPFLAGSET(line, pe_control,pad0,PE_CONTROL_PAD0)
+
+#define SC_PE_CONTROL_SET_RID(line, pe_control,rid) \
+	FAST_GPFLAGSET(line, pe_control,rid,PE_CONTROL_RID)
+
+#define SC_PE_FIELD_MASK_SET_EVEN(line, pe_field_mask,even) \
+	FAST_GPFLAGSET(line, pe_field_mask,even,PE_FIELD_MASK_EVEN)
+
+#define SC_PE_FIELD_MASK_SET_ODD(line, pe_field_mask,odd) \
+	FAST_GPFLAGSET(line, pe_field_mask,odd,PE_FIELD_MASK_ODD)
+
+#define SC_PE_FIELD_MASK_SET_PAD0(line, pe_field_mask,pad0) \
+	FAST_GPFLAGSET(line, pe_field_mask,pad0,PE_FIELD_MASK_PAD0)
+
+#define SC_PE_FIELD_MASK_SET_RID(line, pe_field_mask,rid) \
+	FAST_GPFLAGSET(line, pe_field_mask,rid,PE_FIELD_MASK_RID)
+
+#define SC_PE_FINISH_SET_DST(line, pe_finish,dst) \
+	FAST_GPFLAGSET(line, pe_finish,dst,PE_FINISH_DST)
+
+#define SC_PE_FINISH_SET_PAD0(line, pe_finish,pad0) \
+	FAST_GPFLAGSET(line, pe_finish,pad0,PE_FINISH_PAD0)
+
+#define SC_PE_FINISH_SET_RID(line, pe_finish,rid) \
+	FAST_GPFLAGSET(line, pe_finish,rid,PE_FINISH_RID)
+
+#define SC_PE_REFRESH_SET_INTERVAL(line, pe_refresh,interval) \
+	FAST_GPFLAGSET(line, pe_refresh,interval,PE_REFRESH_INTERVAL)
+
+#define SC_PE_REFRESH_SET_ENABLE(line, pe_refresh,enable) \
+	FAST_GPFLAGSET(line, pe_refresh,enable,PE_REFRESH_ENABLE)
+
+#define SC_PE_REFRESH_SET_PAD0(line, pe_refresh,pad0) \
+	FAST_GPFLAGSET(line, pe_refresh,pad0,PE_REFRESH_PAD0)
+
+#define SC_PE_REFRESH_SET_RID(line, pe_refresh,rid) \
+	FAST_GPFLAGSET(line, pe_refresh,rid,PE_REFRESH_RID)
+
+#define SC_PE_TOKEN_SET_TOKEN(line, pe_token,token) \
+	FAST_GPFLAGSET(line, pe_token,token,PE_TOKEN_TOKEN)
+
+#define SC_PE_TOKEN_SET_PAD0(line, pe_token,pad0) \
+	FAST_GPFLAGSET(line, pe_token,pad0,PE_TOKEN_PAD0)
+
+#define SC_PE_TOKEN_SET_RID(line, pe_token,rid) \
+	FAST_GPFLAGSET(line, pe_token,rid,PE_TOKEN_RID)
+
+#define SC_PE_TOKEN_INT_SET_TOKEN(line, pe_token_int,token) \
+	FAST_GPFLAGSET(line, pe_token_int,token,PE_TOKEN_INT_TOKEN)
+
+#define SC_PE_TOKEN_INT_SET_PAD0(line, pe_token_int,pad0) \
+	FAST_GPFLAGSET(line, pe_token_int,pad0,PE_TOKEN_INT_PAD0)
+
+#define SC_PE_TOKEN_INT_SET_RID(line, pe_token_int,rid) \
+	FAST_GPFLAGSET(line, pe_token_int,rid,PE_TOKEN_INT_RID)
+
+#define SC_PE_COPY_SRC_ADDR_SET_X(line, pe_copy_src_addr,x) \
+	FAST_GPFLAGSET(line, pe_copy_src_addr,x,PE_COPY_SRC_ADDR_X)
+
+#define SC_PE_COPY_SRC_ADDR_SET_Y(line, pe_copy_src_addr,y) \
+	FAST_GPFLAGSET(line, pe_copy_src_addr,y,PE_COPY_SRC_ADDR_Y)
+
+#define SC_PE_COPY_SRC_ADDR_SET_PAD0(line, pe_copy_src_addr,pad0) \
+	FAST_GPFLAGSET(line, pe_copy_src_addr,pad0,PE_COPY_SRC_ADDR_PAD0)
+
+#define SC_PE_COPY_SRC_ADDR_SET_RID(line, pe_copy_src_addr,rid) \
+	FAST_GPFLAGSET(line, pe_copy_src_addr,rid,PE_COPY_SRC_ADDR_RID)
+
+#define SC_PE_COPY_SRC_SIZE_SET_X(line, pe_copy_src_size,x) \
+	FAST_GPFLAGSET(line, pe_copy_src_size,x,PE_COPY_SRC_SIZE_X)
+
+#define SC_PE_COPY_SRC_SIZE_SET_Y(line, pe_copy_src_size,y) \
+	FAST_GPFLAGSET(line, pe_copy_src_size,y,PE_COPY_SRC_SIZE_Y)
+
+#define SC_PE_COPY_SRC_SIZE_SET_PAD0(line, pe_copy_src_size,pad0) \
+	FAST_GPFLAGSET(line, pe_copy_src_size,pad0,PE_COPY_SRC_SIZE_PAD0)
+
+#define SC_PE_COPY_SRC_SIZE_SET_RID(line, pe_copy_src_size,rid) \
+	FAST_GPFLAGSET(line, pe_copy_src_size,rid,PE_COPY_SRC_SIZE_RID)
+
+#define SC_PE_COPY_DST_BASE_SET_BASE(line, pe_copy_dst_base,base) \
+	FAST_GPFLAGSET(line, pe_copy_dst_base,base,PE_COPY_DST_BASE_BASE)
+
+#define SC_PE_COPY_DST_BASE_SET_PAD0(line, pe_copy_dst_base,pad0) \
+	FAST_GPFLAGSET(line, pe_copy_dst_base,pad0,PE_COPY_DST_BASE_PAD0)
+
+#define SC_PE_COPY_DST_BASE_SET_RID(line, pe_copy_dst_base,rid) \
+	FAST_GPFLAGSET(line, pe_copy_dst_base,rid,PE_COPY_DST_BASE_RID)
+
+#define SC_PE_COPY_DST_STRIDE_SET_STRIDE(line, pe_copy_dst_stride,stride) \
+	FAST_GPFLAGSET(line, pe_copy_dst_stride,stride,PE_COPY_DST_STRIDE_STRIDE)
+
+#define SC_PE_COPY_DST_STRIDE_SET_PAD0(line, pe_copy_dst_stride,pad0) \
+	FAST_GPFLAGSET(line, pe_copy_dst_stride,pad0,PE_COPY_DST_STRIDE_PAD0)
+
+#define SC_PE_COPY_DST_STRIDE_SET_RID(line, pe_copy_dst_stride,rid) \
+	FAST_GPFLAGSET(line, pe_copy_dst_stride,rid,PE_COPY_DST_STRIDE_RID)
+
+#define SC_PE_COPY_SCALE_SET_SCALE(line, pe_copy_scale,scale) \
+	FAST_GPFLAGSET(line, pe_copy_scale,scale,PE_COPY_SCALE_SCALE)
+
+#define SC_PE_COPY_SCALE_SET_PAD0(line, pe_copy_scale,pad0) \
+	FAST_GPFLAGSET(line, pe_copy_scale,pad0,PE_COPY_SCALE_PAD0)
+
+#define SC_PE_COPY_SCALE_SET_RID(line, pe_copy_scale,rid) \
+	FAST_GPFLAGSET(line, pe_copy_scale,rid,PE_COPY_SCALE_RID)
+
+#define SC_PE_COPY_CLEAR_COLOR_AR_SET_RED(line, pe_copy_clear_color_ar,red) \
+	FAST_GPFLAGSET(line, pe_copy_clear_color_ar,red,PE_COPY_CLEAR_COLOR_AR_RED)
+
+#define SC_PE_COPY_CLEAR_COLOR_AR_SET_ALPHA(line, pe_copy_clear_color_ar,alpha) \
+	FAST_GPFLAGSET(line, pe_copy_clear_color_ar,alpha,PE_COPY_CLEAR_COLOR_AR_ALPHA)
+
+#define SC_PE_COPY_CLEAR_COLOR_AR_SET_PAD0(line, pe_copy_clear_color_ar,pad0) \
+	FAST_GPFLAGSET(line, pe_copy_clear_color_ar,pad0,PE_COPY_CLEAR_COLOR_AR_PAD0)
+
+#define SC_PE_COPY_CLEAR_COLOR_AR_SET_RID(line, pe_copy_clear_color_ar,rid) \
+	FAST_GPFLAGSET(line, pe_copy_clear_color_ar,rid,PE_COPY_CLEAR_COLOR_AR_RID)
+
+#define SC_PE_COPY_CLEAR_COLOR_GB_SET_BLUE(line, pe_copy_clear_color_gb,blue) \
+	FAST_GPFLAGSET(line, pe_copy_clear_color_gb,blue,PE_COPY_CLEAR_COLOR_GB_BLUE)
+
+#define SC_PE_COPY_CLEAR_COLOR_GB_SET_GREEN(line, pe_copy_clear_color_gb,green) \
+	FAST_GPFLAGSET(line, pe_copy_clear_color_gb,green,PE_COPY_CLEAR_COLOR_GB_GREEN)
+
+#define SC_PE_COPY_CLEAR_COLOR_GB_SET_PAD0(line, pe_copy_clear_color_gb,pad0) \
+	FAST_GPFLAGSET(line, pe_copy_clear_color_gb,pad0,PE_COPY_CLEAR_COLOR_GB_PAD0)
+
+#define SC_PE_COPY_CLEAR_COLOR_GB_SET_RID(line, pe_copy_clear_color_gb,rid) \
+	FAST_GPFLAGSET(line, pe_copy_clear_color_gb,rid,PE_COPY_CLEAR_COLOR_GB_RID)
+
+#define SC_PE_COPY_CLEAR_Z_SET_DATA(line, pe_copy_clear_z,data) \
+	FAST_GPFLAGSET(line, pe_copy_clear_z,data,PE_COPY_CLEAR_Z_DATA)
+
+#define SC_PE_COPY_CLEAR_Z_SET_RID(line, pe_copy_clear_z,rid) \
+	FAST_GPFLAGSET(line, pe_copy_clear_z,rid,PE_COPY_CLEAR_Z_RID)
+
+#define SC_PE_COPY_CMD_SET_CLAMP_TOP(line, pe_copy_cmd,clamp_top) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,clamp_top,PE_COPY_CMD_CLAMP_TOP)
+
+#define SC_PE_COPY_CMD_SET_CLAMP_BOTTOM(line, pe_copy_cmd,clamp_bottom) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,clamp_bottom,PE_COPY_CMD_CLAMP_BOTTOM)
+
+#define SC_PE_COPY_CMD_SET_PAD0(line, pe_copy_cmd,pad0) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,pad0,PE_COPY_CMD_PAD0)
+
+#define SC_PE_COPY_CMD_SET_TEX_FORMATH(line, pe_copy_cmd,tex_formatH) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,tex_formatH,PE_COPY_CMD_TEX_FORMATH)
+
+#define SC_PE_COPY_CMD_SET_TEX_FORMAT(line, pe_copy_cmd,tex_format) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,tex_format,PE_COPY_CMD_TEX_FORMAT)
+
+#define SC_PE_COPY_CMD_SET_GAMMA(line, pe_copy_cmd,gamma) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,gamma,PE_COPY_CMD_GAMMA)
+
+#define SC_PE_COPY_CMD_SET_MIP_MAP_FILTER(line, pe_copy_cmd,mip_map_filter) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,mip_map_filter,PE_COPY_CMD_MIP_MAP_FILTER)
+
+#define SC_PE_COPY_CMD_SET_VERTICAL_SCALE(line, pe_copy_cmd,vertical_scale) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,vertical_scale,PE_COPY_CMD_VERTICAL_SCALE)
+
+#define SC_PE_COPY_CMD_SET_CLEAR(line, pe_copy_cmd,clear) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,clear,PE_COPY_CMD_CLEAR)
+
+#define SC_PE_COPY_CMD_SET_INTERLACED(line, pe_copy_cmd,interlaced) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,interlaced,PE_COPY_CMD_INTERLACED)
+
+#define SC_PE_COPY_CMD_SET_OPCODE(line, pe_copy_cmd,opcode) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,opcode,PE_COPY_CMD_OPCODE)
+
+#define SC_PE_COPY_CMD_SET_CCV(line, pe_copy_cmd,ccv) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,ccv,PE_COPY_CMD_CCV)
+
+#define SC_PE_COPY_CMD_SET_PAD1(line, pe_copy_cmd,pad1) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,pad1,PE_COPY_CMD_PAD1)
+
+#define SC_PE_COPY_CMD_SET_RID(line, pe_copy_cmd,rid) \
+	FAST_GPFLAGSET(line, pe_copy_cmd,rid,PE_COPY_CMD_RID)
+
+#define SC_PE_COPY_VFILTER0_SET_COEFF0(line, pe_copy_vfilter0,coeff0) \
+	FAST_GPFLAGSET(line, pe_copy_vfilter0,coeff0,PE_COPY_VFILTER0_COEFF0)
+
+#define SC_PE_COPY_VFILTER0_SET_COEFF1(line, pe_copy_vfilter0,coeff1) \
+	FAST_GPFLAGSET(line, pe_copy_vfilter0,coeff1,PE_COPY_VFILTER0_COEFF1)
+
+#define SC_PE_COPY_VFILTER0_SET_COEFF2(line, pe_copy_vfilter0,coeff2) \
+	FAST_GPFLAGSET(line, pe_copy_vfilter0,coeff2,PE_COPY_VFILTER0_COEFF2)
+
+#define SC_PE_COPY_VFILTER0_SET_COEFF3(line, pe_copy_vfilter0,coeff3) \
+	FAST_GPFLAGSET(line, pe_copy_vfilter0,coeff3,PE_COPY_VFILTER0_COEFF3)
+
+#define SC_PE_COPY_VFILTER0_SET_RID(line, pe_copy_vfilter0,rid) \
+	FAST_GPFLAGSET(line, pe_copy_vfilter0,rid,PE_COPY_VFILTER0_RID)
+
+#define SC_PE_COPY_VFILTER1_SET_COEFF4(line, pe_copy_vfilter1,coeff4) \
+	FAST_GPFLAGSET(line, pe_copy_vfilter1,coeff4,PE_COPY_VFILTER1_COEFF4)
+
+#define SC_PE_COPY_VFILTER1_SET_COEFF5(line, pe_copy_vfilter1,coeff5) \
+	FAST_GPFLAGSET(line, pe_copy_vfilter1,coeff5,PE_COPY_VFILTER1_COEFF5)
+
+#define SC_PE_COPY_VFILTER1_SET_COEFF6(line, pe_copy_vfilter1,coeff6) \
+	FAST_GPFLAGSET(line, pe_copy_vfilter1,coeff6,PE_COPY_VFILTER1_COEFF6)
+
+#define SC_PE_COPY_VFILTER1_SET_PAD0(line, pe_copy_vfilter1,pad0) \
+	FAST_GPFLAGSET(line, pe_copy_vfilter1,pad0,PE_COPY_VFILTER1_PAD0)
+
+#define SC_PE_COPY_VFILTER1_SET_RID(line, pe_copy_vfilter1,rid) \
+	FAST_GPFLAGSET(line, pe_copy_vfilter1,rid,PE_COPY_VFILTER1_RID)
+
+#define SC_PE_XBOUND_SET_LEFT(line, pe_xbound,left) \
+	FAST_GPFLAGSET(line, pe_xbound,left,PE_XBOUND_LEFT)
+
+#define SC_PE_XBOUND_SET_RIGHT(line, pe_xbound,right) \
+	FAST_GPFLAGSET(line, pe_xbound,right,PE_XBOUND_RIGHT)
+
+#define SC_PE_XBOUND_SET_PAD0(line, pe_xbound,pad0) \
+	FAST_GPFLAGSET(line, pe_xbound,pad0,PE_XBOUND_PAD0)
+
+#define SC_PE_XBOUND_SET_RID(line, pe_xbound,rid) \
+	FAST_GPFLAGSET(line, pe_xbound,rid,PE_XBOUND_RID)
+
+#define SC_PE_YBOUND_SET_TOP(line, pe_ybound,top) \
+	FAST_GPFLAGSET(line, pe_ybound,top,PE_YBOUND_TOP)
+
+#define SC_PE_YBOUND_SET_BOTTOM(line, pe_ybound,bottom) \
+	FAST_GPFLAGSET(line, pe_ybound,bottom,PE_YBOUND_BOTTOM)
+
+#define SC_PE_YBOUND_SET_PAD0(line, pe_ybound,pad0) \
+	FAST_GPFLAGSET(line, pe_ybound,pad0,PE_YBOUND_PAD0)
+
+#define SC_PE_YBOUND_SET_RID(line, pe_ybound,rid) \
+	FAST_GPFLAGSET(line, pe_ybound,rid,PE_YBOUND_RID)
+
+#define SC_PE_PERFMODE_SET_CNTR0(line, pe_perfmode,cntr0) \
+	FAST_GPFLAGSET(line, pe_perfmode,cntr0,PE_PERFMODE_CNTR0)
+
+#define SC_PE_PERFMODE_SET_CNTR1(line, pe_perfmode,cntr1) \
+	FAST_GPFLAGSET(line, pe_perfmode,cntr1,PE_PERFMODE_CNTR1)
+
+#define SC_PE_PERFMODE_SET_CNTR2(line, pe_perfmode,cntr2) \
+	FAST_GPFLAGSET(line, pe_perfmode,cntr2,PE_PERFMODE_CNTR2)
+
+#define SC_PE_PERFMODE_SET_CNTR3(line, pe_perfmode,cntr3) \
+	FAST_GPFLAGSET(line, pe_perfmode,cntr3,PE_PERFMODE_CNTR3)
+
+#define SC_PE_PERFMODE_SET_CNTR4(line, pe_perfmode,cntr4) \
+	FAST_GPFLAGSET(line, pe_perfmode,cntr4,PE_PERFMODE_CNTR4)
+
+#define SC_PE_PERFMODE_SET_CNTR5(line, pe_perfmode,cntr5) \
+	FAST_GPFLAGSET(line, pe_perfmode,cntr5,PE_PERFMODE_CNTR5)
+
+#define SC_PE_PERFMODE_SET_PAD0(line, pe_perfmode,pad0) \
+	FAST_GPFLAGSET(line, pe_perfmode,pad0,PE_PERFMODE_PAD0)
+
+#define SC_PE_PERFMODE_SET_RID(line, pe_perfmode,rid) \
+	FAST_GPFLAGSET(line, pe_perfmode,rid,PE_PERFMODE_RID)
+
+#define SC_PE_CHICKEN_SET_PIWR(line, pe_chicken,piwr) \
+	FAST_GPFLAGSET(line, pe_chicken,piwr,PE_CHICKEN_PIWR)
+
+#define SC_PE_CHICKEN_SET_TXCPY_FMT(line, pe_chicken,txcpy_fmt) \
+	FAST_GPFLAGSET(line, pe_chicken,txcpy_fmt,PE_CHICKEN_TXCPY_FMT)
+
+#define SC_PE_CHICKEN_SET_TXCPY_CCV(line, pe_chicken,txcpy_ccv) \
+	FAST_GPFLAGSET(line, pe_chicken,txcpy_ccv,PE_CHICKEN_TXCPY_CCV)
+
+#define SC_PE_CHICKEN_SET_BLENDOP(line, pe_chicken,blendop) \
+	FAST_GPFLAGSET(line, pe_chicken,blendop,PE_CHICKEN_BLENDOP)
+
+#define SC_PE_CHICKEN_SET_PAD0(line, pe_chicken,pad0) \
+	FAST_GPFLAGSET(line, pe_chicken,pad0,PE_CHICKEN_PAD0)
+
+#define SC_PE_CHICKEN_SET_RID(line, pe_chicken,rid) \
+	FAST_GPFLAGSET(line, pe_chicken,rid,PE_CHICKEN_RID)
+
+#define SC_PE_QUAD_OFFSET_SET_X(line, pe_quad_offset,x) \
+	FAST_GPFLAGSET(line, pe_quad_offset,x,PE_QUAD_OFFSET_X)
+
+#define SC_PE_QUAD_OFFSET_SET_Y(line, pe_quad_offset,y) \
+	FAST_GPFLAGSET(line, pe_quad_offset,y,PE_QUAD_OFFSET_Y)
+
+#define SC_PE_QUAD_OFFSET_SET_PAD0(line, pe_quad_offset,pad0) \
+	FAST_GPFLAGSET(line, pe_quad_offset,pad0,PE_QUAD_OFFSET_PAD0)
+
+#define SC_PE_QUAD_OFFSET_SET_RID(line, pe_quad_offset,rid) \
+	FAST_GPFLAGSET(line, pe_quad_offset,rid,PE_QUAD_OFFSET_RID)
+
+#define SC_PE_COLOR_RGB8_SET_BLUE(line, pe_color_rgb8,blue) \
+	FAST_GPFLAGSET(line, pe_color_rgb8,blue,PE_COLOR_RGB8_BLUE)
+
+#define SC_PE_COLOR_RGB8_SET_GREEN(line, pe_color_rgb8,green) \
+	FAST_GPFLAGSET(line, pe_color_rgb8,green,PE_COLOR_RGB8_GREEN)
+
+#define SC_PE_COLOR_RGB8_SET_RED(line, pe_color_rgb8,red) \
+	FAST_GPFLAGSET(line, pe_color_rgb8,red,PE_COLOR_RGB8_RED)
+
+#define SC_PE_COLOR_RGB8_SET_PAD0(line, pe_color_rgb8,pad0) \
+	FAST_GPFLAGSET(line, pe_color_rgb8,pad0,PE_COLOR_RGB8_PAD0)
+
+#define SC_PE_COLOR_RGBA6_SET_ALPHA(line, pe_color_rgba6,alpha) \
+	FAST_GPFLAGSET(line, pe_color_rgba6,alpha,PE_COLOR_RGBA6_ALPHA)
+
+#define SC_PE_COLOR_RGBA6_SET_BLUE(line, pe_color_rgba6,blue) \
+	FAST_GPFLAGSET(line, pe_color_rgba6,blue,PE_COLOR_RGBA6_BLUE)
+
+#define SC_PE_COLOR_RGBA6_SET_GREEN(line, pe_color_rgba6,green) \
+	FAST_GPFLAGSET(line, pe_color_rgba6,green,PE_COLOR_RGBA6_GREEN)
+
+#define SC_PE_COLOR_RGBA6_SET_RED(line, pe_color_rgba6,red) \
+	FAST_GPFLAGSET(line, pe_color_rgba6,red,PE_COLOR_RGBA6_RED)
+
+#define SC_PE_COLOR_RGBA6_SET_PAD0(line, pe_color_rgba6,pad0) \
+	FAST_GPFLAGSET(line, pe_color_rgba6,pad0,PE_COLOR_RGBA6_PAD0)
+
+#define SC_PE_COLOR_RGBAA_SET_BLUE(line, pe_color_rgbaa,blue) \
+	FAST_GPFLAGSET(line, pe_color_rgbaa,blue,PE_COLOR_RGBAA_BLUE)
+
+#define SC_PE_COLOR_RGBAA_SET_GREEN(line, pe_color_rgbaa,green) \
+	FAST_GPFLAGSET(line, pe_color_rgbaa,green,PE_COLOR_RGBAA_GREEN)
+
+#define SC_PE_COLOR_RGBAA_SET_RED(line, pe_color_rgbaa,red) \
+	FAST_GPFLAGSET(line, pe_color_rgbaa,red,PE_COLOR_RGBAA_RED)
+
+#define SC_PE_TEX_COPY_I4_SET_I1(line, pe_tex_copy_i4,i1) \
+	FAST_GPFLAGSET(line, pe_tex_copy_i4,i1,PE_TEX_COPY_I4_I1)
+
+#define SC_PE_TEX_COPY_I4_SET_I0(line, pe_tex_copy_i4,i0) \
+	FAST_GPFLAGSET(line, pe_tex_copy_i4,i0,PE_TEX_COPY_I4_I0)
+
+#define SC_PE_TEX_COPY_IA4_SET_I(line, pe_tex_copy_ia4,i) \
+	FAST_GPFLAGSET(line, pe_tex_copy_ia4,i,PE_TEX_COPY_IA4_I)
+
+#define SC_PE_TEX_COPY_IA4_SET_ALPHA(line, pe_tex_copy_ia4,alpha) \
+	FAST_GPFLAGSET(line, pe_tex_copy_ia4,alpha,PE_TEX_COPY_IA4_ALPHA)
+
+#define SC_PE_TEX_COPY_IA8_SET_I(line, pe_tex_copy_ia8,i) \
+	FAST_GPFLAGSET(line, pe_tex_copy_ia8,i,PE_TEX_COPY_IA8_I)
+
+#define SC_PE_TEX_COPY_IA8_SET_ALPHA(line, pe_tex_copy_ia8,alpha) \
+	FAST_GPFLAGSET(line, pe_tex_copy_ia8,alpha,PE_TEX_COPY_IA8_ALPHA)
+
+#define SC_PE_TEX_COPY_R5G6B5_SET_BLUE(line, pe_tex_copy_r5g6b5,blue) \
+	FAST_GPFLAGSET(line, pe_tex_copy_r5g6b5,blue,PE_TEX_COPY_R5G6B5_BLUE)
+
+#define SC_PE_TEX_COPY_R5G6B5_SET_GREEN(line, pe_tex_copy_r5g6b5,green) \
+	FAST_GPFLAGSET(line, pe_tex_copy_r5g6b5,green,PE_TEX_COPY_R5G6B5_GREEN)
+
+#define SC_PE_TEX_COPY_R5G6B5_SET_RED(line, pe_tex_copy_r5g6b5,red) \
+	FAST_GPFLAGSET(line, pe_tex_copy_r5g6b5,red,PE_TEX_COPY_R5G6B5_RED)
+
+#define SC_PE_TEX_COPY_RGB5_SET_BLUE(line, pe_tex_copy_rgb5,blue) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgb5,blue,PE_TEX_COPY_RGB5_BLUE)
+
+#define SC_PE_TEX_COPY_RGB5_SET_GREEN(line, pe_tex_copy_rgb5,green) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgb5,green,PE_TEX_COPY_RGB5_GREEN)
+
+#define SC_PE_TEX_COPY_RGB5_SET_RED(line, pe_tex_copy_rgb5,red) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgb5,red,PE_TEX_COPY_RGB5_RED)
+
+#define SC_PE_TEX_COPY_RGB5_SET_FORMAT(line, pe_tex_copy_rgb5,format) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgb5,format,PE_TEX_COPY_RGB5_FORMAT)
+
+#define SC_PE_TEX_COPY_RGB4A3_SET_BLUE(line, pe_tex_copy_rgb4a3,blue) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgb4a3,blue,PE_TEX_COPY_RGB4A3_BLUE)
+
+#define SC_PE_TEX_COPY_RGB4A3_SET_GREEN(line, pe_tex_copy_rgb4a3,green) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgb4a3,green,PE_TEX_COPY_RGB4A3_GREEN)
+
+#define SC_PE_TEX_COPY_RGB4A3_SET_RED(line, pe_tex_copy_rgb4a3,red) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgb4a3,red,PE_TEX_COPY_RGB4A3_RED)
+
+#define SC_PE_TEX_COPY_RGB4A3_SET_ALPHA(line, pe_tex_copy_rgb4a3,alpha) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgb4a3,alpha,PE_TEX_COPY_RGB4A3_ALPHA)
+
+#define SC_PE_TEX_COPY_RGB4A3_SET_FORMAT(line, pe_tex_copy_rgb4a3,format) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgb4a3,format,PE_TEX_COPY_RGB4A3_FORMAT)
+
+#define SC_PE_TEX_COPY_RGBA8_SET_RED(line, pe_tex_copy_rgba8,red) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgba8,red,PE_TEX_COPY_RGBA8_RED)
+
+#define SC_PE_TEX_COPY_RGBA8_SET_ALPHA(line, pe_tex_copy_rgba8,alpha) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgba8,alpha,PE_TEX_COPY_RGBA8_ALPHA)
+
+#define SC_PE_TEX_COPY_RGBA8_SET_BLUE(line, pe_tex_copy_rgba8,blue) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgba8,blue,PE_TEX_COPY_RGBA8_BLUE)
+
+#define SC_PE_TEX_COPY_RGBA8_SET_GREEN(line, pe_tex_copy_rgba8,green) \
+	FAST_GPFLAGSET(line, pe_tex_copy_rgba8,green,PE_TEX_COPY_RGBA8_GREEN)
+
+#define SC_PE_MASK_SET_M0(line, pe_mask,m0) \
+	FAST_GPFLAGSET(line, pe_mask,m0,PE_MASK_M0)
+
+#define SC_PE_MASK_SET_M1(line, pe_mask,m1) \
+	FAST_GPFLAGSET(line, pe_mask,m1,PE_MASK_M1)
+
+#define SC_PE_MASK_SET_M2(line, pe_mask,m2) \
+	FAST_GPFLAGSET(line, pe_mask,m2,PE_MASK_M2)
+
+#define SC_PE_MASK_SET_M3(line, pe_mask,m3) \
+	FAST_GPFLAGSET(line, pe_mask,m3,PE_MASK_M3)
+
+#define SC_PE_MISC_SET_V0(line, pe_misc,v0) \
+	FAST_GPFLAGSET(line, pe_misc,v0,PE_MISC_V0)
+
+#define SC_PE_MISC_SET_V1(line, pe_misc,v1) \
+	FAST_GPFLAGSET(line, pe_misc,v1,PE_MISC_V1)
+
+#define SC_PE_MISC_SET_V2(line, pe_misc,v2) \
+	FAST_GPFLAGSET(line, pe_misc,v2,PE_MISC_V2)
+
+#define SC_PE_MISC_SET_V3(line, pe_misc,v3) \
+	FAST_GPFLAGSET(line, pe_misc,v3,PE_MISC_V3)
+
+#define SC_PE_MISC_SET_ST(line, pe_misc,st) \
+	FAST_GPFLAGSET(line, pe_misc,st,PE_MISC_ST)
+
+#define SC_PE_MISC_SET_SB(line, pe_misc,sb) \
+	FAST_GPFLAGSET(line, pe_misc,sb,PE_MISC_SB)
+
+#define SC_PE_MISC_SET_SL(line, pe_misc,sl) \
+	FAST_GPFLAGSET(line, pe_misc,sl,PE_MISC_SL)
+
+#define SC_PE_MISC_SET_SR(line, pe_misc,sr) \
+	FAST_GPFLAGSET(line, pe_misc,sr,PE_MISC_SR)
+
+#define SC_PE_MISC_SET_TT(line, pe_misc,tt) \
+	FAST_GPFLAGSET(line, pe_misc,tt,PE_MISC_TT)
+
+#define SC_PE_MISC_SET_TB(line, pe_misc,tb) \
+	FAST_GPFLAGSET(line, pe_misc,tb,PE_MISC_TB)
+
+#define SC_PE_MISC_SET_TL(line, pe_misc,tl) \
+	FAST_GPFLAGSET(line, pe_misc,tl,PE_MISC_TL)
+
+#define SC_PE_MISC_SET_TR(line, pe_misc,tr) \
+	FAST_GPFLAGSET(line, pe_misc,tr,PE_MISC_TR)
+
+#define SC_PE_MISC_SET_TM(line, pe_misc,tm) \
+	FAST_GPFLAGSET(line, pe_misc,tm,PE_MISC_TM)
+
+#define SC_PE_MISC_SET_TP(line, pe_misc,tp) \
+	FAST_GPFLAGSET(line, pe_misc,tp,PE_MISC_TP)
+
+#define SC_PE_MISC_SET_SV(line, pe_misc,sv) \
+	FAST_GPFLAGSET(line, pe_misc,sv,PE_MISC_SV)
+
+#define SC_PE_TAG_SET_CYCLE(line, pe_tag,cycle) \
+	FAST_GPFLAGSET(line, pe_tag,cycle,PE_TAG_CYCLE)
+
+#define SC_PE_TAG_SET_YEC(line, pe_tag,yec) \
+	FAST_GPFLAGSET(line, pe_tag,yec,PE_TAG_YEC)
+
+#define SC_PE_TAG_SET_YOC(line, pe_tag,yoc) \
+	FAST_GPFLAGSET(line, pe_tag,yoc,PE_TAG_YOC)
+
+#define SC_PE_TAG_SET_XOC(line, pe_tag,xoc) \
+	FAST_GPFLAGSET(line, pe_tag,xoc,PE_TAG_XOC)
+
+#define SC_PE_TAG_SET_CLR(line, pe_tag,clr) \
+	FAST_GPFLAGSET(line, pe_tag,clr,PE_TAG_CLR)
+
+#define SC_PE_CMD_SET_VALID(line, pe_cmd,valid) \
+	FAST_GPFLAGSET(line, pe_cmd,valid,PE_CMD_VALID)
+
+#define SC_PE_CMD_SET_OP(line, pe_cmd,op) \
+	FAST_GPFLAGSET(line, pe_cmd,op,PE_CMD_OP)
+
+#define SC_PE_CMD_SET_BANKA(line, pe_cmd,bankA) \
+	FAST_GPFLAGSET(line, pe_cmd,bankA,PE_CMD_BANKA)
+
+#define SC_PE_CMD_SET_BANKB(line, pe_cmd,bankB) \
+	FAST_GPFLAGSET(line, pe_cmd,bankB,PE_CMD_BANKB)
+
+#define SC_PE_INTRCTL_SET_INT0EN(line, pe_intrctl,int0en) \
+	FAST_GPFLAGSET(line, pe_intrctl,int0en,PE_INTRCTL_INT0EN)
+
+#define SC_PE_INTRCTL_SET_INT1EN(line, pe_intrctl,int1en) \
+	FAST_GPFLAGSET(line, pe_intrctl,int1en,PE_INTRCTL_INT1EN)
+
+#define SC_PE_INTRCTL_SET_INT0CLR(line, pe_intrctl,int0clr) \
+	FAST_GPFLAGSET(line, pe_intrctl,int0clr,PE_INTRCTL_INT0CLR)
+
+#define SC_PE_INTRCTL_SET_INT1CLR(line, pe_intrctl,int1clr) \
+	FAST_GPFLAGSET(line, pe_intrctl,int1clr,PE_INTRCTL_INT1CLR)
+
+#define SC_PE_PI_EFB_ADDR_SET_PAD0(line, pe_pi_efb_addr,pad0) \
+	FAST_GPFLAGSET(line, pe_pi_efb_addr,pad0,PE_PI_EFB_ADDR_PAD0)
+
+#define SC_PE_PI_EFB_ADDR_SET_X(line, pe_pi_efb_addr,x) \
+	FAST_GPFLAGSET(line, pe_pi_efb_addr,x,PE_PI_EFB_ADDR_X)
+
+#define SC_PE_PI_EFB_ADDR_SET_Y(line, pe_pi_efb_addr,y) \
+	FAST_GPFLAGSET(line, pe_pi_efb_addr,y,PE_PI_EFB_ADDR_Y)
+
+#define SC_PE_PI_EFB_ADDR_SET_TYPE(line, pe_pi_efb_addr,type) \
+	FAST_GPFLAGSET(line, pe_pi_efb_addr,type,PE_PI_EFB_ADDR_TYPE)
+
+#define SC_PE_PI_ZMODE_SET_ZEN(line, pe_pi_zmode,zen) \
+	FAST_GPFLAGSET(line, pe_pi_zmode,zen,PE_PI_ZMODE_ZEN)
+
+#define SC_PE_PI_ZMODE_SET_ZFUNC(line, pe_pi_zmode,zfunc) \
+	FAST_GPFLAGSET(line, pe_pi_zmode,zfunc,PE_PI_ZMODE_ZFUNC)
+
+#define SC_PE_PI_ZMODE_SET_MASK(line, pe_pi_zmode,mask) \
+	FAST_GPFLAGSET(line, pe_pi_zmode,mask,PE_PI_ZMODE_MASK)
+
+#define SC_PE_PI_ZMODE_SET_PAD0(line, pe_pi_zmode,pad0) \
+	FAST_GPFLAGSET(line, pe_pi_zmode,pad0,PE_PI_ZMODE_PAD0)
+
+#define SC_PE_PI_ZMODE_SET_RID(line, pe_pi_zmode,rid) \
+	FAST_GPFLAGSET(line, pe_pi_zmode,rid,PE_PI_ZMODE_RID)
+
+#define SC_PE_PI_CMODE0_SET_BEN(line, pe_pi_cmode0,ben) \
+	FAST_GPFLAGSET(line, pe_pi_cmode0,ben,PE_PI_CMODE0_BEN)
+
+#define SC_PE_PI_CMODE0_SET_LEN(line, pe_pi_cmode0,len) \
+	FAST_GPFLAGSET(line, pe_pi_cmode0,len,PE_PI_CMODE0_LEN)
+
+#define SC_PE_PI_CMODE0_SET_DEN(line, pe_pi_cmode0,den) \
+	FAST_GPFLAGSET(line, pe_pi_cmode0,den,PE_PI_CMODE0_DEN)
+
+#define SC_PE_PI_CMODE0_SET_CMSK(line, pe_pi_cmode0,cmsk) \
+	FAST_GPFLAGSET(line, pe_pi_cmode0,cmsk,PE_PI_CMODE0_CMSK)
+
+#define SC_PE_PI_CMODE0_SET_AMSK(line, pe_pi_cmode0,amsk) \
+	FAST_GPFLAGSET(line, pe_pi_cmode0,amsk,PE_PI_CMODE0_AMSK)
+
+#define SC_PE_PI_CMODE0_SET_DFACTOR(line, pe_pi_cmode0,dfactor) \
+	FAST_GPFLAGSET(line, pe_pi_cmode0,dfactor,PE_PI_CMODE0_DFACTOR)
+
+#define SC_PE_PI_CMODE0_SET_SFACTOR(line, pe_pi_cmode0,sfactor) \
+	FAST_GPFLAGSET(line, pe_pi_cmode0,sfactor,PE_PI_CMODE0_SFACTOR)
+
+#define SC_PE_PI_CMODE0_SET_LOGICOP(line, pe_pi_cmode0,logicop) \
+	FAST_GPFLAGSET(line, pe_pi_cmode0,logicop,PE_PI_CMODE0_LOGICOP)
+
+#define SC_PE_PI_CMODE0_SET_PAD0(line, pe_pi_cmode0,pad0) \
+	FAST_GPFLAGSET(line, pe_pi_cmode0,pad0,PE_PI_CMODE0_PAD0)
+
+#define SC_PE_PI_CMODE0_SET_RID(line, pe_pi_cmode0,rid) \
+	FAST_GPFLAGSET(line, pe_pi_cmode0,rid,PE_PI_CMODE0_RID)
+
+#define SC_PE_PI_CMODE1_SET_CONSTALPHA(line, pe_pi_cmode1,constAlpha) \
+	FAST_GPFLAGSET(line, pe_pi_cmode1,constAlpha,PE_PI_CMODE1_CONSTALPHA)
+
+#define SC_PE_PI_CMODE1_SET_EN(line, pe_pi_cmode1,en) \
+	FAST_GPFLAGSET(line, pe_pi_cmode1,en,PE_PI_CMODE1_EN)
+
+#define SC_PE_PI_CMODE1_SET_PAD0(line, pe_pi_cmode1,pad0) \
+	FAST_GPFLAGSET(line, pe_pi_cmode1,pad0,PE_PI_CMODE1_PAD0)
+
+#define SC_PE_PI_CMODE1_SET_RID(line, pe_pi_cmode1,rid) \
+	FAST_GPFLAGSET(line, pe_pi_cmode1,rid,PE_PI_CMODE1_RID)
+
+#define SC_PE_PI_ALPHA_THRESHOLD_SET_ALPHA_THRESHOLD(line, pe_pi_alpha_threshold,alpha_threshold) \
+	FAST_GPFLAGSET(line, pe_pi_alpha_threshold,alpha_threshold,PE_PI_ALPHA_THRESHOLD_ALPHA_THRESHOLD)
+
+#define SC_PE_PI_ALPHA_THRESHOLD_SET_AFUNCTION(line, pe_pi_alpha_threshold,afunction) \
+	FAST_GPFLAGSET(line, pe_pi_alpha_threshold,afunction,PE_PI_ALPHA_THRESHOLD_AFUNCTION)
+
+#define SC_PE_PI_ALPHA_THRESHOLD_SET_PAD0(line, pe_pi_alpha_threshold,pad0) \
+	FAST_GPFLAGSET(line, pe_pi_alpha_threshold,pad0,PE_PI_ALPHA_THRESHOLD_PAD0)
+
+#define SC_PE_PI_ALPHA_THRESHOLD_SET_RID(line, pe_pi_alpha_threshold,rid) \
+	FAST_GPFLAGSET(line, pe_pi_alpha_threshold,rid,PE_PI_ALPHA_THRESHOLD_RID)
+
+#define SC_PE_PI_CTL_SET_AFMT(line, pe_pi_ctl,afmt) \
+	FAST_GPFLAGSET(line, pe_pi_ctl,afmt,PE_PI_CTL_AFMT)
+
+#define SC_PE_PI_CTL_SET_ZFMT(line, pe_pi_ctl,zfmt) \
+	FAST_GPFLAGSET(line, pe_pi_ctl,zfmt,PE_PI_CTL_ZFMT)
+
+#define SC_PE_PI_CTL_SET_PAD0(line, pe_pi_ctl,pad0) \
+	FAST_GPFLAGSET(line, pe_pi_ctl,pad0,PE_PI_CTL_PAD0)
+
+#define SC_PE_PI_CTL_SET_RID(line, pe_pi_ctl,rid) \
+	FAST_GPFLAGSET(line, pe_pi_ctl,rid,PE_PI_CTL_RID)
+
+#endif // PE_REG_H
diff --git a/include/revolution/private/pi_reg.h b/include/revolution/private/pi_reg.h
new file mode 100644
index 0000000000..37fe2c401a
--- /dev/null
+++ b/include/revolution/private/pi_reg.h
@@ -0,0 +1,73 @@
+#ifndef PI_REG_H
+#define PI_REG_H
+
+#include <revolution/private/GXFDLShortcut.h>
+
+#define PI_REG_INTSR	0x000
+#define PI_REG_INTMSK	0x004
+#define PI_REG_CPBAS	0x00C
+#define PI_REG_CPTOP	0x010
+#define PI_REG_CPWRT	0x014
+#define PI_REG_CPABT	0x018
+#define PI_REG_PIESR	0x01C
+#define PI_REG_PIEAR	0x020
+#define PI_REG_CONFIG	0x024
+#define PI_REG_DURAR	0x028
+#define PI_REG_CHIPID	0x02C
+#define PI_REG_STRGTH	0x030
+#define PI_REG_CPUDBB	0x034
+
+#define PI_REGSP_CP	0x0C000000
+#define PI_REGSP_PE	0x0C001000
+#define PI_REGSP_VI	0x0C002000
+#define PI_REGSP_PI	0x0C003000
+#define PI_REGSP_MEM	0x0C004000
+#define PI_REGSP_DSP	0x0C005000
+#define PI_REGSP_IO	0x0C006000
+#define PI_GFXSP	0x0C008000
+
+#define PI_CPWRT_REG_CPWRT_SIZE	24
+#define PI_CPWRT_REG_CPWRT_SHIFT	5
+#define PI_CPWRT_REG_CPWRT_MASK	0x1fffffe0
+#define PI_CPWRT_REG_GET_CPWRT(pi_cpwrt_reg) \
+	((((unsigned long)(pi_cpwrt_reg)) & PI_CPWRT_REG_CPWRT_MASK) >> PI_CPWRT_REG_CPWRT_SHIFT)
+
+#define XF_PERF0_F_PERF_B_SIZE	5
+#define XF_PERF0_F_PERF_B_SHIFT	5
+#define XF_PERF0_F_PERF_B_MASK	0x000003e0
+#define XF_PERF0_F_GET_PERF_B(xf_perf0_f) \
+	((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_B_MASK) >> XF_PERF0_F_PERF_B_SHIFT)
+
+#define XF_PERF0_F_PERF_C_SIZE	5
+#define XF_PERF0_F_PERF_C_SHIFT	10
+#define XF_PERF0_F_PERF_C_MASK	0x00007c00
+#define XF_PERF0_F_GET_PERF_C(xf_perf0_f) \
+	((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_C_MASK) >> XF_PERF0_F_PERF_C_SHIFT)
+
+#define XF_PERF0_F_PERF_D_SIZE	5
+#define XF_PERF0_F_PERF_D_SHIFT	15
+#define XF_PERF0_F_PERF_D_MASK	0x000f8000
+#define XF_PERF0_F_GET_PERF_D(xf_perf0_f) \
+	((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_D_MASK) >> XF_PERF0_F_PERF_D_SHIFT)
+
+#define XF_PERF0_F_PERF_A_SIZE	5
+#define XF_PERF0_F_PERF_A_SHIFT	0
+#define XF_PERF0_F_PERF_A_MASK	0x0000001f
+#define XF_PERF0_F_GET_PERF_A(xf_perf0_f) \
+	((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_A_MASK) >> XF_PERF0_F_PERF_A_SHIFT)
+
+#define PI_CPWRT_REG_CPWRAP_SIZE	1
+#define PI_CPWRT_REG_CPWRAP_SHIFT	29
+#define PI_CPWRT_REG_CPWRAP_MASK	0x20000000
+#define PI_CPWRT_REG_GET_CPWRAP(pi_cpwrt_reg) \
+	((((unsigned long)(pi_cpwrt_reg)) & PI_CPWRT_REG_CPWRAP_MASK) >> PI_CPWRT_REG_CPWRAP_SHIFT)
+
+
+#define SC_PI_CPWRT_REG_SET_CPWRT(line, pi_cpwrt_reg,cpwrt) \
+	FAST_GPFLAGSET(line, pi_cpwrt_reg,cpwrt,PI_CPWRT_REG_CPWRT)
+
+#define SC_PI_CPWRT_REG_SET_CPWRAP(line, pi_cpwrt_reg,cpwrap) \
+	FAST_GPFLAGSET(line, pi_cpwrt_reg,cpwrap,PI_CPWRT_REG_CPWRAP)
+
+
+#endif // PI_REG_H
diff --git a/include/revolution/private/ras_reg.h b/include/revolution/private/ras_reg.h
new file mode 100644
index 0000000000..58d56e86a8
--- /dev/null
+++ b/include/revolution/private/ras_reg.h
@@ -0,0 +1,232 @@
+#ifndef RAS_REG
+#define RAS_REG
+
+#define RAS1_TREF_RID_SIZE	8
+#define RAS1_TREF_RID_SHIFT	24
+#define RAS1_TREF_RID_MASK	0xff000000
+#define RAS1_TREF_GET_RID(ras1_tref) \
+	((((unsigned long)(ras1_tref)) & RAS1_TREF_RID_MASK) >> RAS1_TREF_RID_SHIFT)
+
+#define RAS1_IREF_RID_SIZE	8
+#define RAS1_IREF_RID_SHIFT	24
+#define RAS1_IREF_RID_MASK	0xff000000
+#define RAS1_IREF_GET_RID(ras1_iref) \
+    ((((unsigned long)(ras1_iref)) & RAS1_IREF_RID_MASK) >> RAS1_IREF_RID_SHIFT)
+
+#define RAS_PERF_SELA_SIZE	5
+#define RAS_PERF_SELA_SHIFT	0
+#define RAS_PERF_SELA_MASK	0x0000001f
+#define RAS_PERF_GET_SELA(ras_perf) \
+    ((((unsigned long)(ras_perf)) & RAS_PERF_SELA_MASK) >> RAS_PERF_SELA_SHIFT)
+
+#define RAS_PERF_SELB_SIZE	5
+#define RAS_PERF_SELB_SHIFT	5
+#define RAS_PERF_SELB_MASK	0x000003e0
+#define RAS_PERF_GET_SELB(ras_perf) \
+    ((((unsigned long)(ras_perf)) & RAS_PERF_SELB_MASK) >> RAS_PERF_SELB_SHIFT)
+
+#define RAS_PERF_NTEV_SIZE	5
+#define RAS_PERF_NTEV_SHIFT	10
+#define RAS_PERF_NTEV_MASK	0x00007c00
+#define RAS_PERF_GET_NTEV(ras_perf) \
+    ((((unsigned long)(ras_perf)) & RAS_PERF_NTEV_MASK) >> RAS_PERF_NTEV_SHIFT)
+
+#define RAS_PERF_NBMP_SIZE	3
+#define RAS_PERF_NBMP_SHIFT	15
+#define RAS_PERF_NBMP_MASK	0x00038000
+#define RAS_PERF_GET_NBMP(ras_perf) \
+    ((((unsigned long)(ras_perf)) & RAS_PERF_NBMP_MASK) >> RAS_PERF_NBMP_SHIFT)
+
+#define RAS_PERF_NBR_SIZE	3
+#define RAS_PERF_NBR_SHIFT	18
+#define RAS_PERF_NBR_MASK	0x001c0000
+#define RAS_PERF_GET_NBR(ras_perf) \
+    ((((unsigned long)(ras_perf)) & RAS_PERF_NBR_MASK) >> RAS_PERF_NBR_SHIFT)
+
+#define RAS_PERF_PAD0_SIZE	3
+#define RAS_PERF_PAD0_SHIFT	21
+#define RAS_PERF_PAD0_MASK	0x00e00000
+#define RAS_PERF_GET_PAD0(ras_perf) \
+    ((((unsigned long)(ras_perf)) & RAS_PERF_PAD0_MASK) >> RAS_PERF_PAD0_SHIFT)
+#define RAS_PERF_RID_SIZE	8
+#define RAS_PERF_RID_SHIFT	24
+#define RAS_PERF_RID_MASK	0xff000000
+#define RAS_PERF_GET_RID(ras_perf) \
+    ((((unsigned long)(ras_perf)) & RAS_PERF_RID_MASK) >> RAS_PERF_RID_SHIFT)
+    
+#define RAS_PERF_TOTAL_SIZE	32
+#define RAS_PERF(selA, selB, ntev, nbmp, nbr, rid) \
+    ((((unsigned long)(selA)) << RAS_PERF_SELA_SHIFT) | \
+        (((unsigned long)(selB)) << RAS_PERF_SELB_SHIFT) | \
+        (((unsigned long)(ntev)) << RAS_PERF_NTEV_SHIFT) | \
+        (((unsigned long)(nbmp)) << RAS_PERF_NBMP_SHIFT) | \
+        (((unsigned long)(nbr)) << RAS_PERF_NBR_SHIFT) | \
+        (((unsigned long)(rid)) << RAS_PERF_RID_SHIFT))
+
+#define RAS1_TREF_TI0_SIZE	3
+#define RAS1_TREF_TI0_SHIFT	0
+#define RAS1_TREF_TI0_MASK	0x00000007
+#define RAS1_TREF_GET_TI0(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_TI0_MASK) >> RAS1_TREF_TI0_SHIFT)
+
+#define RAS1_TREF_TC0_SIZE	3
+#define RAS1_TREF_TC0_SHIFT	3
+#define RAS1_TREF_TC0_MASK	0x00000038
+#define RAS1_TREF_GET_TC0(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_TC0_MASK) >> RAS1_TREF_TC0_SHIFT)
+
+#define RAS1_TREF_TE0_SIZE	1
+#define RAS1_TREF_TE0_SHIFT	6
+#define RAS1_TREF_TE0_MASK	0x00000040
+#define RAS1_TREF_GET_TE0(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_TE0_MASK) >> RAS1_TREF_TE0_SHIFT)
+
+#define RAS1_TREF_CC0_SIZE	3
+#define RAS1_TREF_CC0_SHIFT	7
+#define RAS1_TREF_CC0_MASK	0x00000380
+#define RAS1_TREF_GET_CC0(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_CC0_MASK) >> RAS1_TREF_CC0_SHIFT)
+
+#define RAS1_TREF_PAD0_SIZE	2
+#define RAS1_TREF_PAD0_SHIFT	10
+#define RAS1_TREF_PAD0_MASK	0x00000c00
+#define RAS1_TREF_GET_PAD0(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_PAD0_MASK) >> RAS1_TREF_PAD0_SHIFT)
+
+#define RAS1_TREF_TI1_SIZE	3
+#define RAS1_TREF_TI1_SHIFT	12
+#define RAS1_TREF_TI1_MASK	0x00007000
+#define RAS1_TREF_GET_TI1(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_TI1_MASK) >> RAS1_TREF_TI1_SHIFT)
+
+#define RAS1_TREF_TC1_SIZE	3
+#define RAS1_TREF_TC1_SHIFT	15
+#define RAS1_TREF_TC1_MASK	0x00038000
+#define RAS1_TREF_GET_TC1(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_TC1_MASK) >> RAS1_TREF_TC1_SHIFT)
+
+#define RAS1_TREF_TE1_SIZE	1
+#define RAS1_TREF_TE1_SHIFT	18
+#define RAS1_TREF_TE1_MASK	0x00040000
+#define RAS1_TREF_GET_TE1(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_TE1_MASK) >> RAS1_TREF_TE1_SHIFT)
+
+#define RAS1_TREF_CC1_SIZE	3
+#define RAS1_TREF_CC1_SHIFT	19
+#define RAS1_TREF_CC1_MASK	0x00380000
+#define RAS1_TREF_GET_CC1(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_CC1_MASK) >> RAS1_TREF_CC1_SHIFT)
+
+#define RAS1_TREF_PAD1_SIZE	2
+#define RAS1_TREF_PAD1_SHIFT	22
+#define RAS1_TREF_PAD1_MASK	0x00c00000
+#define RAS1_TREF_GET_PAD1(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_PAD1_MASK) >> RAS1_TREF_PAD1_SHIFT)
+
+#define RAS1_TREF_RID_SIZE	8
+#define RAS1_TREF_RID_SHIFT	24
+#define RAS1_TREF_RID_MASK	0xff000000
+#define RAS1_TREF_GET_RID(ras1_tref) \
+    ((((unsigned long)(ras1_tref)) & RAS1_TREF_RID_MASK) >> RAS1_TREF_RID_SHIFT)
+
+#define SC_RAS1_SS_SET_SS0(line, ras1_ss,ss0) \
+	FAST_GPFLAGSET(line, ras1_ss,ss0,RAS1_SS_SS0)
+
+#define SC_RAS1_SS_SET_TS0(line, ras1_ss,ts0) \
+	FAST_GPFLAGSET(line, ras1_ss,ts0,RAS1_SS_TS0)
+
+#define SC_RAS1_SS_SET_SS1(line, ras1_ss,ss1) \
+	FAST_GPFLAGSET(line, ras1_ss,ss1,RAS1_SS_SS1)
+
+#define SC_RAS1_SS_SET_TS1(line, ras1_ss,ts1) \
+	FAST_GPFLAGSET(line, ras1_ss,ts1,RAS1_SS_TS1)
+
+#define SC_RAS1_SS_SET_PAD0(line, ras1_ss,pad0) \
+	FAST_GPFLAGSET(line, ras1_ss,pad0,RAS1_SS_PAD0)
+
+#define SC_RAS1_SS_SET_RID(line, ras1_ss,rid) \
+	FAST_GPFLAGSET(line, ras1_ss,rid,RAS1_SS_RID)
+
+#define SC_RAS1_IREF_SET_BI0(line, ras1_iref,bi0) \
+	FAST_GPFLAGSET(line, ras1_iref,bi0,RAS1_IREF_BI0)
+
+#define SC_RAS1_IREF_SET_BC0(line, ras1_iref,bc0) \
+	FAST_GPFLAGSET(line, ras1_iref,bc0,RAS1_IREF_BC0)
+
+#define SC_RAS1_IREF_SET_BI1(line, ras1_iref,bi1) \
+	FAST_GPFLAGSET(line, ras1_iref,bi1,RAS1_IREF_BI1)
+
+#define SC_RAS1_IREF_SET_BC1(line, ras1_iref,bc1) \
+	FAST_GPFLAGSET(line, ras1_iref,bc1,RAS1_IREF_BC1)
+
+#define SC_RAS1_IREF_SET_BI2(line, ras1_iref,bi2) \
+	FAST_GPFLAGSET(line, ras1_iref,bi2,RAS1_IREF_BI2)
+
+#define SC_RAS1_IREF_SET_BC2(line, ras1_iref,bc2) \
+	FAST_GPFLAGSET(line, ras1_iref,bc2,RAS1_IREF_BC2)
+
+#define SC_RAS1_IREF_SET_BI3(line, ras1_iref,bi3) \
+	FAST_GPFLAGSET(line, ras1_iref,bi3,RAS1_IREF_BI3)
+
+#define SC_RAS1_IREF_SET_BC3(line, ras1_iref,bc3) \
+	FAST_GPFLAGSET(line, ras1_iref,bc3,RAS1_IREF_BC3)
+
+#define SC_RAS1_IREF_SET_RID(line, ras1_iref,rid) \
+	FAST_GPFLAGSET(line, ras1_iref,rid,RAS1_IREF_RID)
+
+#define SC_RAS1_TREF_SET_TI0(line, ras1_tref,ti0) \
+	FAST_GPFLAGSET(line, ras1_tref,ti0,RAS1_TREF_TI0)
+
+#define SC_RAS1_TREF_SET_TC0(line, ras1_tref,tc0) \
+	FAST_GPFLAGSET(line, ras1_tref,tc0,RAS1_TREF_TC0)
+
+#define SC_RAS1_TREF_SET_TE0(line, ras1_tref,te0) \
+	FAST_GPFLAGSET(line, ras1_tref,te0,RAS1_TREF_TE0)
+
+#define SC_RAS1_TREF_SET_CC0(line, ras1_tref,cc0) \
+	FAST_GPFLAGSET(line, ras1_tref,cc0,RAS1_TREF_CC0)
+
+#define SC_RAS1_TREF_SET_PAD0(line, ras1_tref,pad0) \
+	FAST_GPFLAGSET(line, ras1_tref,pad0,RAS1_TREF_PAD0)
+
+#define SC_RAS1_TREF_SET_TI1(line, ras1_tref,ti1) \
+	FAST_GPFLAGSET(line, ras1_tref,ti1,RAS1_TREF_TI1)
+
+#define SC_RAS1_TREF_SET_TC1(line, ras1_tref,tc1) \
+	FAST_GPFLAGSET(line, ras1_tref,tc1,RAS1_TREF_TC1)
+
+#define SC_RAS1_TREF_SET_TE1(line, ras1_tref,te1) \
+	FAST_GPFLAGSET(line, ras1_tref,te1,RAS1_TREF_TE1)
+
+#define SC_RAS1_TREF_SET_CC1(line, ras1_tref,cc1) \
+	FAST_GPFLAGSET(line, ras1_tref,cc1,RAS1_TREF_CC1)
+
+#define SC_RAS1_TREF_SET_PAD1(line, ras1_tref,pad1) \
+	FAST_GPFLAGSET(line, ras1_tref,pad1,RAS1_TREF_PAD1)
+
+#define SC_RAS1_TREF_SET_RID(line, ras1_tref,rid) \
+	FAST_GPFLAGSET(line, ras1_tref,rid,RAS1_TREF_RID)
+
+#define SC_RAS_PERF_SET_SELA(line, ras_perf,selA) \
+	FAST_GPFLAGSET(line, ras_perf,selA,RAS_PERF_SELA)
+
+#define SC_RAS_PERF_SET_SELB(line, ras_perf,selB) \
+	FAST_GPFLAGSET(line, ras_perf,selB,RAS_PERF_SELB)
+
+#define SC_RAS_PERF_SET_NTEV(line, ras_perf,ntev) \
+	FAST_GPFLAGSET(line, ras_perf,ntev,RAS_PERF_NTEV)
+
+#define SC_RAS_PERF_SET_NBMP(line, ras_perf,nbmp) \
+	FAST_GPFLAGSET(line, ras_perf,nbmp,RAS_PERF_NBMP)
+
+#define SC_RAS_PERF_SET_NBR(line, ras_perf,nbr) \
+	FAST_GPFLAGSET(line, ras_perf,nbr,RAS_PERF_NBR)
+
+#define SC_RAS_PERF_SET_PAD0(line, ras_perf,pad0) \
+	FAST_GPFLAGSET(line, ras_perf,pad0,RAS_PERF_PAD0)
+
+#define SC_RAS_PERF_SET_RID(line, ras_perf,rid) \
+	FAST_GPFLAGSET(line, ras_perf,rid,RAS_PERF_RID)
+
+
+#endif // RAS_REG
diff --git a/include/revolution/private/su_reg.h b/include/revolution/private/su_reg.h
new file mode 100644
index 0000000000..afe7c7ca3b
--- /dev/null
+++ b/include/revolution/private/su_reg.h
@@ -0,0 +1,387 @@
+#ifndef SU_REG_H
+#define SU_REG_H
+
+#define SU_LPSIZE_RID_SIZE	8
+#define SU_LPSIZE_RID_SHIFT	24
+#define SU_LPSIZE_RID_MASK	0xff000000
+#define SU_LPSIZE_GET_RID(su_lpsize) \
+	((((unsigned long)(su_lpsize)) & SU_LPSIZE_RID_MASK) >> SU_LPSIZE_RID_SHIFT)
+
+
+#define SU_TS0_RID_SIZE	8
+#define SU_TS0_RID_SHIFT	24
+#define SU_TS0_RID_MASK	0xff000000
+#define SU_TS0_GET_RID(su_ts0) \
+    ((((unsigned long)(su_ts0)) & SU_TS0_RID_MASK) >> SU_TS0_RID_SHIFT)
+
+#define SU_TS1_RID_SIZE	8
+#define SU_TS1_RID_SHIFT	24
+#define SU_TS1_RID_MASK	0xff000000
+#define SU_TS1_GET_RID(su_ts1) \
+    ((((unsigned long)(su_ts1)) & SU_TS1_RID_MASK) >> SU_TS1_RID_SHIFT)
+
+#define SU_SCIS0_RID_SIZE	8
+#define SU_SCIS0_RID_SHIFT	24
+#define SU_SCIS0_RID_MASK	0xff000000
+#define SU_SCIS0_GET_RID(su_scis0) \
+    ((((unsigned long)(su_scis0)) & SU_SCIS0_RID_MASK) >> SU_SCIS0_RID_SHIFT)
+
+#define SU_PERF_SELA_SIZE	3
+#define SU_PERF_SELA_SHIFT	0
+#define SU_PERF_SELA_MASK	0x00000007
+#define SU_PERF_GET_SELA(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_SELA_MASK) >> SU_PERF_SELA_SHIFT)
+
+#define SU_SCIS1_RID_SIZE	8
+#define SU_SCIS1_RID_SHIFT	24
+#define SU_SCIS1_RID_MASK	0xff000000
+#define SU_SCIS1_GET_RID(su_scis1) \
+    ((((unsigned long)(su_scis1)) & SU_SCIS1_RID_MASK) >> SU_SCIS1_RID_SHIFT)
+
+#define SU_PERF_NTEX_SIZE	4
+#define SU_PERF_NTEX_SHIFT	6
+#define SU_PERF_NTEX_MASK	0x000003c0
+#define SU_PERF_GET_NTEX(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_NTEX_MASK) >> SU_PERF_NTEX_SHIFT)
+
+#define SU_PERF_NCOL_SIZE	2
+#define SU_PERF_NCOL_SHIFT	10
+#define SU_PERF_NCOL_MASK	0x00000c00
+#define SU_PERF_GET_NCOL(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_NCOL_MASK) >> SU_PERF_NCOL_SHIFT)
+
+#define SU_PERF_SELB_SIZE	3
+#define SU_PERF_SELB_SHIFT	3
+#define SU_PERF_SELB_MASK	0x00000038
+#define SU_PERF_GET_SELB(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_SELB_MASK) >> SU_PERF_SELB_SHIFT)
+
+#define SU_PERF_REJF_SIZE	2
+#define SU_PERF_REJF_SHIFT	12
+#define SU_PERF_REJF_MASK	0x00003000
+#define SU_PERF_GET_REJF(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_REJF_MASK) >> SU_PERF_REJF_SHIFT)
+
+#define SU_PERF_REJS_SIZE	2
+#define SU_PERF_REJS_SHIFT	14
+#define SU_PERF_REJS_MASK	0x0000c000
+#define SU_PERF_GET_REJS(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_REJS_MASK) >> SU_PERF_REJS_SHIFT)
+
+#define SU_PERF_CMD_SIZE	2
+#define SU_PERF_CMD_SHIFT	16
+#define SU_PERF_CMD_MASK	0x00030000
+#define SU_PERF_GET_CMD(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_CMD_MASK) >> SU_PERF_CMD_SHIFT)
+
+#define SU_PERF_PAD0_SIZE	2
+#define SU_PERF_PAD0_SHIFT	18
+#define SU_PERF_PAD0_MASK	0x000c0000
+#define SU_PERF_GET_PAD0(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_PAD0_MASK) >> SU_PERF_PAD0_SHIFT)
+
+#define SU_PERF_EN_SIZE	2
+#define SU_PERF_EN_SHIFT	20
+#define SU_PERF_EN_MASK	0x00300000
+#define SU_PERF_GET_EN(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_EN_MASK) >> SU_PERF_EN_SHIFT)
+
+#define SU_PERF_PWR_EN_SIZE	2
+#define SU_PERF_PWR_EN_SHIFT	22
+#define SU_PERF_PWR_EN_MASK	0x00c00000
+#define SU_PERF_GET_PWR_EN(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_PWR_EN_MASK) >> SU_PERF_PWR_EN_SHIFT)
+
+#define SU_PERF_RID_SIZE	8
+#define SU_PERF_RID_SHIFT	24
+#define SU_PERF_RID_MASK	0xff000000
+#define SU_PERF_GET_RID(su_perf) \
+    ((((unsigned long)(su_perf)) & SU_PERF_RID_MASK) >> SU_PERF_RID_SHIFT)
+
+#define SU_PERF_TOTAL_SIZE	32
+#define SU_PERF(selA, selB, ntex, ncol, rejf, rejs, cmd, en, pwr_en, rid) \
+    ((((unsigned long)(selA)) << SU_PERF_SELA_SHIFT) | \
+        (((unsigned long)(selB)) << SU_PERF_SELB_SHIFT) | \
+        (((unsigned long)(ntex)) << SU_PERF_NTEX_SHIFT) | \
+        (((unsigned long)(ncol)) << SU_PERF_NCOL_SHIFT) | \
+        (((unsigned long)(rejf)) << SU_PERF_REJF_SHIFT) | \
+        (((unsigned long)(rejs)) << SU_PERF_REJS_SHIFT) | \
+        (((unsigned long)(cmd)) << SU_PERF_CMD_SHIFT) | \
+        (((unsigned long)(en)) << SU_PERF_EN_SHIFT) | \
+        (((unsigned long)(pwr_en)) << SU_PERF_PWR_EN_SHIFT) | \
+        (((unsigned long)(rid)) << SU_PERF_RID_SHIFT))
+
+#define SU_LPSIZE_LSIZE_SIZE	8
+#define SU_LPSIZE_LSIZE_SHIFT	0
+#define SU_LPSIZE_LSIZE_MASK	0x000000ff
+#define SU_LPSIZE_GET_LSIZE(su_lpsize) \
+    ((((unsigned long)(su_lpsize)) & SU_LPSIZE_LSIZE_MASK) >> SU_LPSIZE_LSIZE_SHIFT)
+
+#define SU_LPSIZE_PSIZE_SIZE	8
+#define SU_LPSIZE_PSIZE_SHIFT	8
+#define SU_LPSIZE_PSIZE_MASK	0x0000ff00
+#define SU_LPSIZE_GET_PSIZE(su_lpsize) \
+    ((((unsigned long)(su_lpsize)) & SU_LPSIZE_PSIZE_MASK) >> SU_LPSIZE_PSIZE_SHIFT)
+
+#define SU_LPSIZE_LTOFF_SIZE	3
+#define SU_LPSIZE_LTOFF_SHIFT	16
+#define SU_LPSIZE_LTOFF_MASK	0x00070000
+#define SU_LPSIZE_GET_LTOFF(su_lpsize) \
+    ((((unsigned long)(su_lpsize)) & SU_LPSIZE_LTOFF_MASK) >> SU_LPSIZE_LTOFF_SHIFT)
+
+#define SU_LPSIZE_PTOFF_SIZE	3
+#define SU_LPSIZE_PTOFF_SHIFT	19
+#define SU_LPSIZE_PTOFF_MASK	0x00380000
+#define SU_LPSIZE_GET_PTOFF(su_lpsize) \
+    ((((unsigned long)(su_lpsize)) & SU_LPSIZE_PTOFF_MASK) >> SU_LPSIZE_PTOFF_SHIFT)
+
+#define SU_LPSIZE_FIELDMODE_SIZE	1
+#define SU_LPSIZE_FIELDMODE_SHIFT	22
+#define SU_LPSIZE_FIELDMODE_MASK	0x00400000
+#define SU_LPSIZE_GET_FIELDMODE(su_lpsize) \
+    ((((unsigned long)(su_lpsize)) & SU_LPSIZE_FIELDMODE_MASK) >> SU_LPSIZE_FIELDMODE_SHIFT)
+
+#define SU_LPSIZE_PAD0_SIZE	1
+#define SU_LPSIZE_PAD0_SHIFT	23
+#define SU_LPSIZE_PAD0_MASK	0x00800000
+#define SU_LPSIZE_GET_PAD0(su_lpsize) \
+    ((((unsigned long)(su_lpsize)) & SU_LPSIZE_PAD0_MASK) >> SU_LPSIZE_PAD0_SHIFT)
+
+#define SU_LPSIZE_RID_SIZE	8
+#define SU_LPSIZE_RID_SHIFT	24
+#define SU_LPSIZE_RID_MASK	0xff000000
+#define SU_LPSIZE_GET_RID(su_lpsize) \
+    ((((unsigned long)(su_lpsize)) & SU_LPSIZE_RID_MASK) >> SU_LPSIZE_RID_SHIFT)
+
+#define SU_TS0_SSIZE_SIZE	16
+#define SU_TS0_SSIZE_SHIFT	0
+#define SU_TS0_SSIZE_MASK	0x0000ffff
+#define SU_TS0_GET_SSIZE(su_ts0) \
+    ((((unsigned long)(su_ts0)) & SU_TS0_SSIZE_MASK) >> SU_TS0_SSIZE_SHIFT)
+
+#define SU_TS0_BS_SIZE	1
+#define SU_TS0_BS_SHIFT	16
+#define SU_TS0_BS_MASK	0x00010000
+#define SU_TS0_GET_BS(su_ts0) \
+    ((((unsigned long)(su_ts0)) & SU_TS0_BS_MASK) >> SU_TS0_BS_SHIFT)
+
+#define SU_TS0_WS_SIZE	1
+#define SU_TS0_WS_SHIFT	17
+#define SU_TS0_WS_MASK	0x00020000
+#define SU_TS0_GET_WS(su_ts0) \
+    ((((unsigned long)(su_ts0)) & SU_TS0_WS_MASK) >> SU_TS0_WS_SHIFT)
+
+#define SU_TS0_LF_SIZE	1
+#define SU_TS0_LF_SHIFT	18
+#define SU_TS0_LF_MASK	0x00040000
+#define SU_TS0_GET_LF(su_ts0) \
+    ((((unsigned long)(su_ts0)) & SU_TS0_LF_MASK) >> SU_TS0_LF_SHIFT)
+
+#define SU_TS0_PF_SIZE	1
+#define SU_TS0_PF_SHIFT	19
+#define SU_TS0_PF_MASK	0x00080000
+#define SU_TS0_GET_PF(su_ts0) \
+    ((((unsigned long)(su_ts0)) & SU_TS0_PF_MASK) >> SU_TS0_PF_SHIFT)
+
+#define SU_TS0_PAD0_SIZE	4
+#define SU_TS0_PAD0_SHIFT	20
+#define SU_TS0_PAD0_MASK	0x00f00000
+#define SU_TS0_GET_PAD0(su_ts0) \
+    ((((unsigned long)(su_ts0)) & SU_TS0_PAD0_MASK) >> SU_TS0_PAD0_SHIFT)
+
+#define SU_TS0_RID_SIZE	8
+#define SU_TS0_RID_SHIFT	24
+#define SU_TS0_RID_MASK	0xff000000
+#define SU_TS0_GET_RID(su_ts0) \
+    ((((unsigned long)(su_ts0)) & SU_TS0_RID_MASK) >> SU_TS0_RID_SHIFT)
+
+#define SU_SSMASK_SSMASK_SIZE	24
+#define SU_SSMASK_SSMASK_SHIFT	0
+#define SU_SSMASK_SSMASK_MASK	0x00ffffff
+#define SU_SSMASK_GET_SSMASK(su_ssmask) \
+    ((((unsigned long)(su_ssmask)) & SU_SSMASK_SSMASK_MASK) >> SU_SSMASK_SSMASK_SHIFT)
+
+#define SU_SSMASK_RID_SIZE	8
+#define SU_SSMASK_RID_SHIFT	24
+#define SU_SSMASK_RID_MASK	0xff000000
+#define SU_SSMASK_GET_RID(su_ssmask) \
+    ((((unsigned long)(su_ssmask)) & SU_SSMASK_RID_MASK) >> SU_SSMASK_RID_SHIFT)
+
+#define SU_SSMASK_TOTAL_SIZE	32
+#define SU_SSMASK(ssmask, rid) \
+    ((((unsigned long)(ssmask)) << SU_SSMASK_SSMASK_SHIFT) | \
+        (((unsigned long)(rid)) << SU_SSMASK_RID_SHIFT))
+
+#define SU_SCIS0_SY0_SIZE	11
+#define SU_SCIS0_SY0_SHIFT	0
+#define SU_SCIS0_SY0_MASK	0x000007ff
+#define SU_SCIS0_GET_SY0(su_scis0) \
+	((((unsigned long)(su_scis0)) & SU_SCIS0_SY0_MASK) >> SU_SCIS0_SY0_SHIFT)
+#define SU_SCIS0_SET_SY0(su_scis0, sy0) { \
+	su_scis0 = (((unsigned long)(su_scis0)) & ~SU_SCIS0_SY0_MASK) | (((unsigned long)(sy0)) << SU_SCIS0_SY0_SHIFT);\
+}
+
+#define SU_SCIS0_SX0_SIZE	11
+#define SU_SCIS0_SX0_SHIFT	12
+#define SU_SCIS0_SX0_MASK	0x007ff000
+#define SU_SCIS0_GET_SX0(su_scis0) \
+	((((unsigned long)(su_scis0)) & SU_SCIS0_SX0_MASK) >> SU_SCIS0_SX0_SHIFT)
+#define SU_SCIS0_SET_SX0(su_scis0, sx0) { \
+	su_scis0 = (((unsigned long)(su_scis0)) & ~SU_SCIS0_SX0_MASK) | (((unsigned long)(sx0)) << SU_SCIS0_SX0_SHIFT);\
+}
+
+#define SU_SCIS0_PAD1_SIZE	1
+#define SU_SCIS0_PAD1_SHIFT	23
+#define SU_SCIS0_PAD1_MASK	0x00800000
+#define SU_SCIS0_GET_PAD1(su_scis0) \
+	((((unsigned long)(su_scis0)) & SU_SCIS0_PAD1_MASK) >> SU_SCIS0_PAD1_SHIFT)
+#define SU_SCIS0_SET_PAD1(su_scis0, pad1) { \
+	su_scis0 = (((unsigned long)(su_scis0)) & ~SU_SCIS0_PAD1_MASK) | (((unsigned long)(pad1)) << SU_SCIS0_PAD1_SHIFT);\
+}
+
+#define SU_SCIS1_SY1_SIZE	11
+#define SU_SCIS1_SY1_SHIFT	0
+#define SU_SCIS1_SY1_MASK	0x000007ff
+#define SU_SCIS1_GET_SY1(su_scis1) \
+	((((unsigned long)(su_scis1)) & SU_SCIS1_SY1_MASK) >> SU_SCIS1_SY1_SHIFT)
+#define SU_SCIS1_SET_SY1(su_scis1, sy1) { \
+	su_scis1 = (((unsigned long)(su_scis1)) & ~SU_SCIS1_SY1_MASK) | (((unsigned long)(sy1)) << SU_SCIS1_SY1_SHIFT);\
+}
+
+#define SU_SCIS1_SX1_SIZE	11
+#define SU_SCIS1_SX1_SHIFT	12
+#define SU_SCIS1_SX1_MASK	0x007ff000
+#define SU_SCIS1_GET_SX1(su_scis1) \
+	((((unsigned long)(su_scis1)) & SU_SCIS1_SX1_MASK) >> SU_SCIS1_SX1_SHIFT)
+#define SU_SCIS1_SET_SX1(su_scis1, sx1) { \
+	su_scis1 = (((unsigned long)(su_scis1)) & ~SU_SCIS1_SX1_MASK) | (((unsigned long)(sx1)) << SU_SCIS1_SX1_SHIFT);\
+}
+
+#define SC_SU_SCIS0_SET_SY0(line, su_scis0,sy0) \
+	FAST_GPFLAGSET(line, su_scis0,sy0,SU_SCIS0_SY0)
+
+#define SC_SU_SCIS0_SET_PAD0(line, su_scis0,pad0) \
+	FAST_GPFLAGSET(line, su_scis0,pad0,SU_SCIS0_PAD0)
+
+#define SC_SU_SCIS0_SET_SX0(line, su_scis0,sx0) \
+	FAST_GPFLAGSET(line, su_scis0,sx0,SU_SCIS0_SX0)
+
+#define SC_SU_SCIS0_SET_PAD1(line, su_scis0,pad1) \
+	FAST_GPFLAGSET(line, su_scis0,pad1,SU_SCIS0_PAD1)
+
+#define SC_SU_SCIS0_SET_RID(line, su_scis0,rid) \
+	FAST_GPFLAGSET(line, su_scis0,rid,SU_SCIS0_RID)
+
+#define SC_SU_SCIS1_SET_SY1(line, su_scis1,sy1) \
+	FAST_GPFLAGSET(line, su_scis1,sy1,SU_SCIS1_SY1)
+
+#define SC_SU_SCIS1_SET_PAD0(line, su_scis1,pad0) \
+	FAST_GPFLAGSET(line, su_scis1,pad0,SU_SCIS1_PAD0)
+
+#define SC_SU_SCIS1_SET_SX1(line, su_scis1,sx1) \
+	FAST_GPFLAGSET(line, su_scis1,sx1,SU_SCIS1_SX1)
+
+#define SC_SU_SCIS1_SET_PAD1(line, su_scis1,pad1) \
+	FAST_GPFLAGSET(line, su_scis1,pad1,SU_SCIS1_PAD1)
+
+#define SC_SU_SCIS1_SET_RID(line, su_scis1,rid) \
+	FAST_GPFLAGSET(line, su_scis1,rid,SU_SCIS1_RID)
+
+#define SC_SU_LPSIZE_SET_LSIZE(line, su_lpsize,lsize) \
+	FAST_GPFLAGSET(line, su_lpsize,lsize,SU_LPSIZE_LSIZE)
+
+#define SC_SU_LPSIZE_SET_PSIZE(line, su_lpsize,psize) \
+	FAST_GPFLAGSET(line, su_lpsize,psize,SU_LPSIZE_PSIZE)
+
+#define SC_SU_LPSIZE_SET_LTOFF(line, su_lpsize,ltoff) \
+	FAST_GPFLAGSET(line, su_lpsize,ltoff,SU_LPSIZE_LTOFF)
+
+#define SC_SU_LPSIZE_SET_PTOFF(line, su_lpsize,ptoff) \
+	FAST_GPFLAGSET(line, su_lpsize,ptoff,SU_LPSIZE_PTOFF)
+
+#define SC_SU_LPSIZE_SET_FIELDMODE(line, su_lpsize,fieldmode) \
+	FAST_GPFLAGSET(line, su_lpsize,fieldmode,SU_LPSIZE_FIELDMODE)
+
+#define SC_SU_LPSIZE_SET_PAD0(line, su_lpsize,pad0) \
+	FAST_GPFLAGSET(line, su_lpsize,pad0,SU_LPSIZE_PAD0)
+
+#define SC_SU_LPSIZE_SET_RID(line, su_lpsize,rid) \
+	FAST_GPFLAGSET(line, su_lpsize,rid,SU_LPSIZE_RID)
+
+#define SC_SU_TS0_SET_SSIZE(line, su_ts0,ssize) \
+	FAST_GPFLAGSET(line, su_ts0,ssize,SU_TS0_SSIZE)
+
+#define SC_SU_TS0_SET_BS(line, su_ts0,bs) \
+	FAST_GPFLAGSET(line, su_ts0,bs,SU_TS0_BS)
+
+#define SC_SU_TS0_SET_WS(line, su_ts0,ws) \
+	FAST_GPFLAGSET(line, su_ts0,ws,SU_TS0_WS)
+
+#define SC_SU_TS0_SET_LF(line, su_ts0,lf) \
+	FAST_GPFLAGSET(line, su_ts0,lf,SU_TS0_LF)
+
+#define SC_SU_TS0_SET_PF(line, su_ts0,pf) \
+	FAST_GPFLAGSET(line, su_ts0,pf,SU_TS0_PF)
+
+#define SC_SU_TS0_SET_PAD0(line, su_ts0,pad0) \
+	FAST_GPFLAGSET(line, su_ts0,pad0,SU_TS0_PAD0)
+
+#define SC_SU_TS0_SET_RID(line, su_ts0,rid) \
+	FAST_GPFLAGSET(line, su_ts0,rid,SU_TS0_RID)
+
+#define SC_SU_TS1_SET_TSIZE(line, su_ts1,tsize) \
+	FAST_GPFLAGSET(line, su_ts1,tsize,SU_TS1_TSIZE)
+
+#define SC_SU_TS1_SET_BT(line, su_ts1,bt) \
+	FAST_GPFLAGSET(line, su_ts1,bt,SU_TS1_BT)
+
+#define SC_SU_TS1_SET_WT(line, su_ts1,wt) \
+	FAST_GPFLAGSET(line, su_ts1,wt,SU_TS1_WT)
+
+#define SC_SU_TS1_SET_PAD0(line, su_ts1,pad0) \
+	FAST_GPFLAGSET(line, su_ts1,pad0,SU_TS1_PAD0)
+
+#define SC_SU_TS1_SET_RID(line, su_ts1,rid) \
+	FAST_GPFLAGSET(line, su_ts1,rid,SU_TS1_RID)
+
+#define SC_SU_PERF_SET_SELA(line, su_perf,selA) \
+	FAST_GPFLAGSET(line, su_perf,selA,SU_PERF_SELA)
+
+#define SC_SU_PERF_SET_SELB(line, su_perf,selB) \
+	FAST_GPFLAGSET(line, su_perf,selB,SU_PERF_SELB)
+
+#define SC_SU_PERF_SET_NTEX(line, su_perf,ntex) \
+	FAST_GPFLAGSET(line, su_perf,ntex,SU_PERF_NTEX)
+
+#define SC_SU_PERF_SET_NCOL(line, su_perf,ncol) \
+	FAST_GPFLAGSET(line, su_perf,ncol,SU_PERF_NCOL)
+
+#define SC_SU_PERF_SET_REJF(line, su_perf,rejf) \
+	FAST_GPFLAGSET(line, su_perf,rejf,SU_PERF_REJF)
+
+#define SC_SU_PERF_SET_REJS(line, su_perf,rejs) \
+	FAST_GPFLAGSET(line, su_perf,rejs,SU_PERF_REJS)
+
+#define SC_SU_PERF_SET_CMD(line, su_perf,cmd) \
+	FAST_GPFLAGSET(line, su_perf,cmd,SU_PERF_CMD)
+
+#define SC_SU_PERF_SET_PAD0(line, su_perf,pad0) \
+	FAST_GPFLAGSET(line, su_perf,pad0,SU_PERF_PAD0)
+
+#define SC_SU_PERF_SET_EN(line, su_perf,en) \
+	FAST_GPFLAGSET(line, su_perf,en,SU_PERF_EN)
+
+#define SC_SU_PERF_SET_PWR_EN(line, su_perf,pwr_en) \
+	FAST_GPFLAGSET(line, su_perf,pwr_en,SU_PERF_PWR_EN)
+
+#define SC_SU_PERF_SET_RID(line, su_perf,rid) \
+	FAST_GPFLAGSET(line, su_perf,rid,SU_PERF_RID)
+
+#define SC_SU_SSMASK_SET_SSMASK(line, su_ssmask,ssmask) \
+	FAST_GPFLAGSET(line, su_ssmask,ssmask,SU_SSMASK_SSMASK)
+
+#define SC_SU_SSMASK_SET_RID(line, su_ssmask,rid) \
+	FAST_GPFLAGSET(line, su_ssmask,rid,SU_SSMASK_RID)
+
+
+#endif // SU_REG_H
diff --git a/include/revolution/private/tev_reg.h b/include/revolution/private/tev_reg.h
new file mode 100644
index 0000000000..22898e798b
--- /dev/null
+++ b/include/revolution/private/tev_reg.h
@@ -0,0 +1,729 @@
+#ifndef TEV_REG_H
+#define TEV_REG_H
+
+#define TEV_COLOR_ENV_RID_SIZE	8
+#define TEV_COLOR_ENV_RID_SHIFT	24
+#define TEV_COLOR_ENV_RID_MASK	0xff000000
+#define TEV_COLOR_ENV_GET_RID(tev_color_env) \
+	((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_RID_MASK) >> TEV_COLOR_ENV_RID_SHIFT)
+
+#define TEV_ALPHA_ENV_RID_SIZE	8
+#define TEV_ALPHA_ENV_RID_SHIFT	24
+#define TEV_ALPHA_ENV_RID_MASK	0xff000000
+#define TEV_ALPHA_ENV_GET_RID(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_RID_MASK) >> TEV_ALPHA_ENV_RID_SHIFT)
+
+#define TEV_KSEL_RID_SIZE	8
+#define TEV_KSEL_RID_SHIFT	24
+#define TEV_KSEL_RID_MASK	0xff000000
+#define TEV_KSEL_GET_RID(tev_ksel) \
+    ((((unsigned long)(tev_ksel)) & TEV_KSEL_RID_MASK) >> TEV_KSEL_RID_SHIFT)
+
+#define TEV_ALPHA_ENV_SELD_SIZE	3
+#define TEV_ALPHA_ENV_SELD_SHIFT	4
+#define TEV_ALPHA_ENV_SELD_MASK	0x00000070
+#define TEV_ALPHA_ENV_GET_SELD(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SELD_MASK) >> TEV_ALPHA_ENV_SELD_SHIFT)
+
+#define TEV_ALPHA_ENV_SELC_SIZE	3
+#define TEV_ALPHA_ENV_SELC_SHIFT	7
+#define TEV_ALPHA_ENV_SELC_MASK	0x00000380
+#define TEV_ALPHA_ENV_GET_SELC(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SELC_MASK) >> TEV_ALPHA_ENV_SELC_SHIFT)
+
+#define TEV_ALPHA_ENV_SELB_SIZE	3
+#define TEV_ALPHA_ENV_SELB_SHIFT	10
+#define TEV_ALPHA_ENV_SELB_MASK	0x00001c00
+#define TEV_ALPHA_ENV_GET_SELB(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SELB_MASK) >> TEV_ALPHA_ENV_SELB_SHIFT)
+
+#define TEV_ALPHA_ENV_SELA_SIZE	3
+#define TEV_ALPHA_ENV_SELA_SHIFT	13
+#define TEV_ALPHA_ENV_SELA_MASK	0x0000e000
+#define TEV_ALPHA_ENV_GET_SELA(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SELA_MASK) >> TEV_ALPHA_ENV_SELA_SHIFT)
+
+#define TEV_COLOR_ENV_SELD_SIZE	4
+#define TEV_COLOR_ENV_SELD_SHIFT	0
+#define TEV_COLOR_ENV_SELD_MASK	0x0000000f
+#define TEV_COLOR_ENV_GET_SELD(tev_color_env) \
+    ((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_SELD_MASK) >> TEV_COLOR_ENV_SELD_SHIFT)
+
+#define TEV_COLOR_ENV_SELC_SIZE	4
+#define TEV_COLOR_ENV_SELC_SHIFT	4
+#define TEV_COLOR_ENV_SELC_MASK	0x000000f0
+#define TEV_COLOR_ENV_GET_SELC(tev_color_env) \
+    ((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_SELC_MASK) >> TEV_COLOR_ENV_SELC_SHIFT)
+
+#define TEV_COLOR_ENV_SELB_SIZE	4
+#define TEV_COLOR_ENV_SELB_SHIFT	8
+#define TEV_COLOR_ENV_SELB_MASK	0x00000f00
+#define TEV_COLOR_ENV_GET_SELB(tev_color_env) \
+    ((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_SELB_MASK) >> TEV_COLOR_ENV_SELB_SHIFT)
+
+#define TEV_COLOR_ENV_SELA_SIZE	4
+#define TEV_COLOR_ENV_SELA_SHIFT	12
+#define TEV_COLOR_ENV_SELA_MASK	0x0000f000
+#define TEV_COLOR_ENV_GET_SELA(tev_color_env) \
+    ((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_SELA_MASK) >> TEV_COLOR_ENV_SELA_SHIFT)
+
+#define TEV_COLOR_ENV_BIAS_SIZE	2
+#define TEV_COLOR_ENV_BIAS_SHIFT	16
+#define TEV_COLOR_ENV_BIAS_MASK	0x00030000
+#define TEV_COLOR_ENV_GET_BIAS(tev_color_env) \
+    ((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_BIAS_MASK) >> TEV_COLOR_ENV_BIAS_SHIFT)
+
+#define TEV_COLOR_ENV_SUB_SIZE	1
+#define TEV_COLOR_ENV_SUB_SHIFT	18
+#define TEV_COLOR_ENV_SUB_MASK	0x00040000
+#define TEV_COLOR_ENV_GET_SUB(tev_color_env) \
+    ((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_SUB_MASK) >> TEV_COLOR_ENV_SUB_SHIFT)
+
+#define TEV_COLOR_ENV_CLAMP_SIZE	1
+#define TEV_COLOR_ENV_CLAMP_SHIFT	19
+#define TEV_COLOR_ENV_CLAMP_MASK	0x00080000
+#define TEV_COLOR_ENV_GET_CLAMP(tev_color_env) \
+    ((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_CLAMP_MASK) >> TEV_COLOR_ENV_CLAMP_SHIFT)
+
+#define TEV_COLOR_ENV_SHIFT_SIZE	2
+#define TEV_COLOR_ENV_SHIFT_SHIFT	20
+#define TEV_COLOR_ENV_SHIFT_MASK	0x00300000
+#define TEV_COLOR_ENV_GET_SHIFT(tev_color_env) \
+    ((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_SHIFT_MASK) >> TEV_COLOR_ENV_SHIFT_SHIFT)
+
+#define TEV_COLOR_ENV_DEST_SIZE	2
+#define TEV_COLOR_ENV_DEST_SHIFT	22
+#define TEV_COLOR_ENV_DEST_MASK	0x00c00000
+#define TEV_COLOR_ENV_GET_DEST(tev_color_env) \
+    ((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_DEST_MASK) >> TEV_COLOR_ENV_DEST_SHIFT)
+
+#define TEV_COLOR_ENV_RID_SIZE	8
+#define TEV_COLOR_ENV_RID_SHIFT	24
+#define TEV_COLOR_ENV_RID_MASK	0xff000000
+#define TEV_COLOR_ENV_GET_RID(tev_color_env) \
+    ((((unsigned long)(tev_color_env)) & TEV_COLOR_ENV_RID_MASK) >> TEV_COLOR_ENV_RID_SHIFT)
+
+#define TEV_ALPHA_ENV_MODE_SIZE	2
+#define TEV_ALPHA_ENV_MODE_SHIFT	0
+#define TEV_ALPHA_ENV_MODE_MASK	0x00000003
+#define TEV_ALPHA_ENV_GET_MODE(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_MODE_MASK) >> TEV_ALPHA_ENV_MODE_SHIFT)
+
+#define TEV_ALPHA_ENV_SWAP_SIZE	2
+#define TEV_ALPHA_ENV_SWAP_SHIFT	2
+#define TEV_ALPHA_ENV_SWAP_MASK	0x0000000c
+#define TEV_ALPHA_ENV_GET_SWAP(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SWAP_MASK) >> TEV_ALPHA_ENV_SWAP_SHIFT)
+
+#define TEV_ALPHA_ENV_SELD_SIZE	3
+#define TEV_ALPHA_ENV_SELD_SHIFT	4
+#define TEV_ALPHA_ENV_SELD_MASK	0x00000070
+#define TEV_ALPHA_ENV_GET_SELD(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SELD_MASK) >> TEV_ALPHA_ENV_SELD_SHIFT)
+
+#define TEV_ALPHA_ENV_SELC_SIZE	3
+#define TEV_ALPHA_ENV_SELC_SHIFT	7
+#define TEV_ALPHA_ENV_SELC_MASK	0x00000380
+#define TEV_ALPHA_ENV_GET_SELC(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SELC_MASK) >> TEV_ALPHA_ENV_SELC_SHIFT)
+
+#define TEV_ALPHA_ENV_SELB_SIZE	3
+#define TEV_ALPHA_ENV_SELB_SHIFT	10
+#define TEV_ALPHA_ENV_SELB_MASK	0x00001c00
+#define TEV_ALPHA_ENV_GET_SELB(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SELB_MASK) >> TEV_ALPHA_ENV_SELB_SHIFT)
+
+#define TEV_ALPHA_ENV_SELA_SIZE	3
+#define TEV_ALPHA_ENV_SELA_SHIFT	13
+#define TEV_ALPHA_ENV_SELA_MASK	0x0000e000
+#define TEV_ALPHA_ENV_GET_SELA(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SELA_MASK) >> TEV_ALPHA_ENV_SELA_SHIFT)
+
+#define TEV_ALPHA_ENV_BIAS_SIZE	2
+#define TEV_ALPHA_ENV_BIAS_SHIFT	16
+#define TEV_ALPHA_ENV_BIAS_MASK	0x00030000
+#define TEV_ALPHA_ENV_GET_BIAS(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_BIAS_MASK) >> TEV_ALPHA_ENV_BIAS_SHIFT)
+
+#define TEV_ALPHA_ENV_SUB_SIZE	1
+#define TEV_ALPHA_ENV_SUB_SHIFT	18
+#define TEV_ALPHA_ENV_SUB_MASK	0x00040000
+#define TEV_ALPHA_ENV_GET_SUB(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SUB_MASK) >> TEV_ALPHA_ENV_SUB_SHIFT)
+
+#define TEV_ALPHA_ENV_CLAMP_SIZE	1
+#define TEV_ALPHA_ENV_CLAMP_SHIFT	19
+#define TEV_ALPHA_ENV_CLAMP_MASK	0x00080000
+#define TEV_ALPHA_ENV_GET_CLAMP(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_CLAMP_MASK) >> TEV_ALPHA_ENV_CLAMP_SHIFT)
+
+#define TEV_ALPHA_ENV_SHIFT_SIZE	2
+#define TEV_ALPHA_ENV_SHIFT_SHIFT	20
+#define TEV_ALPHA_ENV_SHIFT_MASK	0x00300000
+#define TEV_ALPHA_ENV_GET_SHIFT(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_SHIFT_MASK) >> TEV_ALPHA_ENV_SHIFT_SHIFT)
+
+#define TEV_ALPHA_ENV_DEST_SIZE	2
+#define TEV_ALPHA_ENV_DEST_SHIFT	22
+#define TEV_ALPHA_ENV_DEST_MASK	0x00c00000
+#define TEV_ALPHA_ENV_GET_DEST(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_DEST_MASK) >> TEV_ALPHA_ENV_DEST_SHIFT)
+
+#define TEV_ALPHA_ENV_RID_SIZE	8
+#define TEV_ALPHA_ENV_RID_SHIFT	24
+#define TEV_ALPHA_ENV_RID_MASK	0xff000000
+#define TEV_ALPHA_ENV_GET_RID(tev_alpha_env) \
+    ((((unsigned long)(tev_alpha_env)) & TEV_ALPHA_ENV_RID_MASK) >> TEV_ALPHA_ENV_RID_SHIFT)
+
+#define TEV_REGISTERL_R_SIZE	11
+#define TEV_REGISTERL_R_SHIFT	0
+#define TEV_REGISTERL_R_MASK	0x000007ff
+#define TEV_REGISTERL_GET_R(tev_registerl) \
+    ((((unsigned long)(tev_registerl)) & TEV_REGISTERL_R_MASK) >> TEV_REGISTERL_R_SHIFT)
+
+#define TEV_REGISTERL_PAD0_SIZE	1
+#define TEV_REGISTERL_PAD0_SHIFT	11
+#define TEV_REGISTERL_PAD0_MASK	0x00000800
+#define TEV_REGISTERL_GET_PAD0(tev_registerl) \
+    ((((unsigned long)(tev_registerl)) & TEV_REGISTERL_PAD0_MASK) >> TEV_REGISTERL_PAD0_SHIFT)
+
+#define TEV_REGISTERL_A_SIZE	11
+#define TEV_REGISTERL_A_SHIFT	12
+#define TEV_REGISTERL_A_MASK	0x007ff000
+#define TEV_REGISTERL_GET_A(tev_registerl) \
+    ((((unsigned long)(tev_registerl)) & TEV_REGISTERL_A_MASK) >> TEV_REGISTERL_A_SHIFT)
+
+#define TEV_REGISTERL_PAD1_SIZE	1
+#define TEV_REGISTERL_PAD1_SHIFT	23
+#define TEV_REGISTERL_PAD1_MASK	0x00800000
+#define TEV_REGISTERL_GET_PAD1(tev_registerl) \
+    ((((unsigned long)(tev_registerl)) & TEV_REGISTERL_PAD1_MASK) >> TEV_REGISTERL_PAD1_SHIFT)
+
+#define TEV_REGISTERL_RID_SIZE	8
+#define TEV_REGISTERL_RID_SHIFT	24
+#define TEV_REGISTERL_RID_MASK	0xff000000
+#define TEV_REGISTERL_GET_RID(tev_registerl) \
+    ((((unsigned long)(tev_registerl)) & TEV_REGISTERL_RID_MASK) >> TEV_REGISTERL_RID_SHIFT)
+
+#define TEV_REGISTERL_TOTAL_SIZE	32
+#define TEV_REGISTERL(r, a, rid) \
+    ((((unsigned long)(r)) << TEV_REGISTERL_R_SHIFT) | \
+        (((unsigned long)(a)) << TEV_REGISTERL_A_SHIFT) | \
+        (((unsigned long)(rid)) << TEV_REGISTERL_RID_SHIFT))
+
+#define TEV_KREGISTERL_R_SIZE	8
+#define TEV_KREGISTERL_R_SHIFT	0
+#define TEV_KREGISTERL_R_MASK	0x000000ff
+#define TEV_KREGISTERL_GET_R(tev_kregisterl) \
+    ((((unsigned long)(tev_kregisterl)) & TEV_KREGISTERL_R_MASK) >> TEV_KREGISTERL_R_SHIFT)
+
+#define TEV_KREGISTERL_PAD0_SIZE	4
+#define TEV_KREGISTERL_PAD0_SHIFT	8
+#define TEV_KREGISTERL_PAD0_MASK	0x00000f00
+#define TEV_KREGISTERL_GET_PAD0(tev_kregisterl) \
+    ((((unsigned long)(tev_kregisterl)) & TEV_KREGISTERL_PAD0_MASK) >> TEV_KREGISTERL_PAD0_SHIFT)
+
+#define TEV_KREGISTERL_A_SIZE	8
+#define TEV_KREGISTERL_A_SHIFT	12
+#define TEV_KREGISTERL_A_MASK	0x000ff000
+#define TEV_KREGISTERL_GET_A(tev_kregisterl) \
+    ((((unsigned long)(tev_kregisterl)) & TEV_KREGISTERL_A_MASK) >> TEV_KREGISTERL_A_SHIFT)
+
+#define TEV_KREGISTERL_PAD1_SIZE	4
+#define TEV_KREGISTERL_PAD1_SHIFT	20
+#define TEV_KREGISTERL_PAD1_MASK	0x00f00000
+#define TEV_KREGISTERL_GET_PAD1(tev_kregisterl) \
+    ((((unsigned long)(tev_kregisterl)) & TEV_KREGISTERL_PAD1_MASK) >> TEV_KREGISTERL_PAD1_SHIFT)
+
+#define TEV_KREGISTERL_RID_SIZE	8
+#define TEV_KREGISTERL_RID_SHIFT	24
+#define TEV_KREGISTERL_RID_MASK	0xff000000
+#define TEV_KREGISTERL_GET_RID(tev_kregisterl) \
+    ((((unsigned long)(tev_kregisterl)) & TEV_KREGISTERL_RID_MASK) >> TEV_KREGISTERL_RID_SHIFT)
+
+#define TEV_KREGISTERL_TOTAL_SIZE	32
+#define TEV_KREGISTERL(r, a, rid) \
+    ((((unsigned long)(r)) << TEV_KREGISTERL_R_SHIFT) | \
+        (((unsigned long)(a)) << TEV_KREGISTERL_A_SHIFT) | \
+        (((unsigned long)(rid)) << TEV_KREGISTERL_RID_SHIFT))
+
+#define TEV_REGISTERH_B_SIZE	11
+#define TEV_REGISTERH_B_SHIFT	0
+#define TEV_REGISTERH_B_MASK	0x000007ff
+#define TEV_REGISTERH_GET_B(tev_registerh) \
+    ((((unsigned long)(tev_registerh)) & TEV_REGISTERH_B_MASK) >> TEV_REGISTERH_B_SHIFT)
+
+#define TEV_REGISTERH_PAD0_SIZE	1
+#define TEV_REGISTERH_PAD0_SHIFT	11
+#define TEV_REGISTERH_PAD0_MASK	0x00000800
+#define TEV_REGISTERH_GET_PAD0(tev_registerh) \
+    ((((unsigned long)(tev_registerh)) & TEV_REGISTERH_PAD0_MASK) >> TEV_REGISTERH_PAD0_SHIFT)
+
+#define TEV_REGISTERH_G_SIZE	11
+#define TEV_REGISTERH_G_SHIFT	12
+#define TEV_REGISTERH_G_MASK	0x007ff000
+#define TEV_REGISTERH_GET_G(tev_registerh) \
+    ((((unsigned long)(tev_registerh)) & TEV_REGISTERH_G_MASK) >> TEV_REGISTERH_G_SHIFT)
+
+#define TEV_REGISTERH_PAD1_SIZE	1
+#define TEV_REGISTERH_PAD1_SHIFT	23
+#define TEV_REGISTERH_PAD1_MASK	0x00800000
+#define TEV_REGISTERH_GET_PAD1(tev_registerh) \
+    ((((unsigned long)(tev_registerh)) & TEV_REGISTERH_PAD1_MASK) >> TEV_REGISTERH_PAD1_SHIFT)
+
+#define TEV_REGISTERH_RID_SIZE	8
+#define TEV_REGISTERH_RID_SHIFT	24
+#define TEV_REGISTERH_RID_MASK	0xff000000
+#define TEV_REGISTERH_GET_RID(tev_registerh) \
+    ((((unsigned long)(tev_registerh)) & TEV_REGISTERH_RID_MASK) >> TEV_REGISTERH_RID_SHIFT)
+
+#define TEV_REGISTERH_TOTAL_SIZE	32
+#define TEV_REGISTERH(b, g, rid) \
+    ((((unsigned long)(b)) << TEV_REGISTERH_B_SHIFT) | \
+        (((unsigned long)(g)) << TEV_REGISTERH_G_SHIFT) | \
+        (((unsigned long)(rid)) << TEV_REGISTERH_RID_SHIFT))
+
+#define TEV_KREGISTERH_B_SIZE	8
+#define TEV_KREGISTERH_B_SHIFT	0
+#define TEV_KREGISTERH_B_MASK	0x000000ff
+#define TEV_KREGISTERH_GET_B(tev_kregisterh) \
+    ((((unsigned long)(tev_kregisterh)) & TEV_KREGISTERH_B_MASK) >> TEV_KREGISTERH_B_SHIFT)
+
+#define TEV_KREGISTERH_PAD0_SIZE	4
+#define TEV_KREGISTERH_PAD0_SHIFT	8
+#define TEV_KREGISTERH_PAD0_MASK	0x00000f00
+#define TEV_KREGISTERH_GET_PAD0(tev_kregisterh) \
+    ((((unsigned long)(tev_kregisterh)) & TEV_KREGISTERH_PAD0_MASK) >> TEV_KREGISTERH_PAD0_SHIFT)
+
+#define TEV_KREGISTERH_G_SIZE	8
+#define TEV_KREGISTERH_G_SHIFT	12
+#define TEV_KREGISTERH_G_MASK	0x000ff000
+#define TEV_KREGISTERH_GET_G(tev_kregisterh) \
+    ((((unsigned long)(tev_kregisterh)) & TEV_KREGISTERH_G_MASK) >> TEV_KREGISTERH_G_SHIFT)
+
+#define TEV_KREGISTERH_PAD1_SIZE	4
+#define TEV_KREGISTERH_PAD1_SHIFT	20
+#define TEV_KREGISTERH_PAD1_MASK	0x00f00000
+#define TEV_KREGISTERH_GET_PAD1(tev_kregisterh) \
+    ((((unsigned long)(tev_kregisterh)) & TEV_KREGISTERH_PAD1_MASK) >> TEV_KREGISTERH_PAD1_SHIFT)
+
+#define TEV_KREGISTERH_RID_SIZE	8
+#define TEV_KREGISTERH_RID_SHIFT	24
+#define TEV_KREGISTERH_RID_MASK	0xff000000
+#define TEV_KREGISTERH_GET_RID(tev_kregisterh) \
+    ((((unsigned long)(tev_kregisterh)) & TEV_KREGISTERH_RID_MASK) >> TEV_KREGISTERH_RID_SHIFT)
+
+#define TEV_KREGISTERH_TOTAL_SIZE	32
+#define TEV_KREGISTERH(b, g, rid) \
+    ((((unsigned long)(b)) << TEV_KREGISTERH_B_SHIFT) | \
+        (((unsigned long)(g)) << TEV_KREGISTERH_G_SHIFT) | \
+        (((unsigned long)(rid)) << TEV_KREGISTERH_RID_SHIFT))
+
+#define TEV_KSEL_XRB_SIZE	2
+#define TEV_KSEL_XRB_SHIFT	0
+#define TEV_KSEL_XRB_MASK	0x00000003
+#define TEV_KSEL_GET_XRB(tev_ksel) \
+    ((((unsigned long)(tev_ksel)) & TEV_KSEL_XRB_MASK) >> TEV_KSEL_XRB_SHIFT)
+
+#define TEV_KSEL_XGA_SIZE	2
+#define TEV_KSEL_XGA_SHIFT	2
+#define TEV_KSEL_XGA_MASK	0x0000000c
+#define TEV_KSEL_GET_XGA(tev_ksel) \
+    ((((unsigned long)(tev_ksel)) & TEV_KSEL_XGA_MASK) >> TEV_KSEL_XGA_SHIFT)
+
+#define TEV_KSEL_KCSEL0_SIZE	5
+#define TEV_KSEL_KCSEL0_SHIFT	4
+#define TEV_KSEL_KCSEL0_MASK	0x000001f0
+#define TEV_KSEL_GET_KCSEL0(tev_ksel) \
+    ((((unsigned long)(tev_ksel)) & TEV_KSEL_KCSEL0_MASK) >> TEV_KSEL_KCSEL0_SHIFT)
+
+#define TEV_KSEL_KASEL0_SIZE	5
+#define TEV_KSEL_KASEL0_SHIFT	9
+#define TEV_KSEL_KASEL0_MASK	0x00003e00
+#define TEV_KSEL_GET_KASEL0(tev_ksel) \
+    ((((unsigned long)(tev_ksel)) & TEV_KSEL_KASEL0_MASK) >> TEV_KSEL_KASEL0_SHIFT)
+
+#define TEV_KSEL_KCSEL1_SIZE	5
+#define TEV_KSEL_KCSEL1_SHIFT	14
+#define TEV_KSEL_KCSEL1_MASK	0x0007c000
+#define TEV_KSEL_GET_KCSEL1(tev_ksel) \
+    ((((unsigned long)(tev_ksel)) & TEV_KSEL_KCSEL1_MASK) >> TEV_KSEL_KCSEL1_SHIFT)
+
+#define TEV_KSEL_KASEL1_SIZE	5
+#define TEV_KSEL_KASEL1_SHIFT	19
+#define TEV_KSEL_KASEL1_MASK	0x00f80000
+#define TEV_KSEL_GET_KASEL1(tev_ksel) \
+    ((((unsigned long)(tev_ksel)) & TEV_KSEL_KASEL1_MASK) >> TEV_KSEL_KASEL1_SHIFT)
+
+#define TEV_KSEL_RID_SIZE	8
+#define TEV_KSEL_RID_SHIFT	24
+#define TEV_KSEL_RID_MASK	0xff000000
+#define TEV_KSEL_GET_RID(tev_ksel) \
+    ((((unsigned long)(tev_ksel)) & TEV_KSEL_RID_MASK) >> TEV_KSEL_RID_SHIFT)
+
+#define TEV_ALPHAFUNC_A0_SIZE	8
+#define TEV_ALPHAFUNC_A0_SHIFT	0
+#define TEV_ALPHAFUNC_A0_MASK	0x000000ff
+#define TEV_ALPHAFUNC_GET_A0(tev_alphafunc) \
+    ((((unsigned long)(tev_alphafunc)) & TEV_ALPHAFUNC_A0_MASK) >> TEV_ALPHAFUNC_A0_SHIFT)
+
+#define TEV_ALPHAFUNC_A1_SIZE	8
+#define TEV_ALPHAFUNC_A1_SHIFT	8
+#define TEV_ALPHAFUNC_A1_MASK	0x0000ff00
+#define TEV_ALPHAFUNC_GET_A1(tev_alphafunc) \
+    ((((unsigned long)(tev_alphafunc)) & TEV_ALPHAFUNC_A1_MASK) >> TEV_ALPHAFUNC_A1_SHIFT)
+
+#define TEV_ALPHAFUNC_OP0_SIZE	3
+#define TEV_ALPHAFUNC_OP0_SHIFT	16
+#define TEV_ALPHAFUNC_OP0_MASK	0x00070000
+#define TEV_ALPHAFUNC_GET_OP0(tev_alphafunc) \
+    ((((unsigned long)(tev_alphafunc)) & TEV_ALPHAFUNC_OP0_MASK) >> TEV_ALPHAFUNC_OP0_SHIFT)
+
+#define TEV_ALPHAFUNC_OP1_SIZE	3
+#define TEV_ALPHAFUNC_OP1_SHIFT	19
+#define TEV_ALPHAFUNC_OP1_MASK	0x00380000
+#define TEV_ALPHAFUNC_GET_OP1(tev_alphafunc) \
+    ((((unsigned long)(tev_alphafunc)) & TEV_ALPHAFUNC_OP1_MASK) >> TEV_ALPHAFUNC_OP1_SHIFT)
+
+#define TEV_ALPHAFUNC_LOGIC_SIZE	2
+#define TEV_ALPHAFUNC_LOGIC_SHIFT	22
+#define TEV_ALPHAFUNC_LOGIC_MASK	0x00c00000
+#define TEV_ALPHAFUNC_GET_LOGIC(tev_alphafunc) \
+    ((((unsigned long)(tev_alphafunc)) & TEV_ALPHAFUNC_LOGIC_MASK) >> TEV_ALPHAFUNC_LOGIC_SHIFT)
+
+#define TEV_ALPHAFUNC_RID_SIZE	8
+#define TEV_ALPHAFUNC_RID_SHIFT	24
+#define TEV_ALPHAFUNC_RID_MASK	0xff000000
+#define TEV_ALPHAFUNC_GET_RID(tev_alphafunc) \
+    ((((unsigned long)(tev_alphafunc)) & TEV_ALPHAFUNC_RID_MASK) >> TEV_ALPHAFUNC_RID_SHIFT)
+
+#define TEV_Z_ENV_0_ZOFF_SIZE	24
+#define TEV_Z_ENV_0_ZOFF_SHIFT	0
+#define TEV_Z_ENV_0_ZOFF_MASK	0x00ffffff
+#define TEV_Z_ENV_0_GET_ZOFF(tev_z_env_0) \
+    ((((unsigned long)(tev_z_env_0)) & TEV_Z_ENV_0_ZOFF_MASK) >> TEV_Z_ENV_0_ZOFF_SHIFT)
+
+#define TEV_Z_ENV_0_RID_SIZE	8
+#define TEV_Z_ENV_0_RID_SHIFT	24
+#define TEV_Z_ENV_0_RID_MASK	0xff000000
+#define TEV_Z_ENV_0_GET_RID(tev_z_env_0) \
+    ((((unsigned long)(tev_z_env_0)) & TEV_Z_ENV_0_RID_MASK) >> TEV_Z_ENV_0_RID_SHIFT)
+
+#define TEV_Z_ENV_1_TYPE_SIZE	2
+#define TEV_Z_ENV_1_TYPE_SHIFT	0
+#define TEV_Z_ENV_1_TYPE_MASK	0x00000003
+#define TEV_Z_ENV_1_GET_TYPE(tev_z_env_1) \
+    ((((unsigned long)(tev_z_env_1)) & TEV_Z_ENV_1_TYPE_MASK) >> TEV_Z_ENV_1_TYPE_SHIFT)
+
+#define TEV_Z_ENV_1_OP_SIZE	2
+#define TEV_Z_ENV_1_OP_SHIFT	2
+#define TEV_Z_ENV_1_OP_MASK	0x0000000c
+#define TEV_Z_ENV_1_GET_OP(tev_z_env_1) \
+    ((((unsigned long)(tev_z_env_1)) & TEV_Z_ENV_1_OP_MASK) >> TEV_Z_ENV_1_OP_SHIFT)
+
+#define TEV_Z_ENV_1_PAD0_SIZE	20
+#define TEV_Z_ENV_1_PAD0_SHIFT	4
+#define TEV_Z_ENV_1_PAD0_MASK	0x00fffff0
+#define TEV_Z_ENV_1_GET_PAD0(tev_z_env_1) \
+    ((((unsigned long)(tev_z_env_1)) & TEV_Z_ENV_1_PAD0_MASK) >> TEV_Z_ENV_1_PAD0_SHIFT)
+
+#define TEV_Z_ENV_1_RID_SIZE	8
+#define TEV_Z_ENV_1_RID_SHIFT	24
+#define TEV_Z_ENV_1_RID_MASK	0xff000000
+#define TEV_Z_ENV_1_GET_RID(tev_z_env_1) \
+    ((((unsigned long)(tev_z_env_1)) & TEV_Z_ENV_1_RID_MASK) >> TEV_Z_ENV_1_RID_SHIFT)
+
+typedef struct {
+    unsigned long rid : 8;
+    unsigned long dest : 2;
+    unsigned long shift : 2;
+    unsigned long clamp : 1;
+    unsigned long sub : 1;
+    unsigned long bias : 2;
+    unsigned long sela : 4;
+    unsigned long selb : 4;
+    unsigned long selc : 4;
+    unsigned long seld : 4;
+} tev_color_env_t;
+
+typedef struct {
+    unsigned long rid : 8;
+    unsigned long dest : 2;
+    unsigned long shift : 2;
+    unsigned long clamp : 1;
+    unsigned long sub : 1;
+    unsigned long bias : 2;
+    unsigned long sela : 3;
+    unsigned long selb : 3;
+    unsigned long selc : 3;
+    unsigned long seld : 3;
+    unsigned long swap : 2;
+    unsigned long mode : 2;
+} tev_alpha_env_t;
+
+#define SC_TEV_COLOR_ENV_SET_SELD(line, tev_color_env,seld) \
+	FAST_GPFLAGSET(line, tev_color_env,seld,TEV_COLOR_ENV_SELD)
+
+#define SC_TEV_COLOR_ENV_SET_SELC(line, tev_color_env,selc) \
+	FAST_GPFLAGSET(line, tev_color_env,selc,TEV_COLOR_ENV_SELC)
+
+#define SC_TEV_COLOR_ENV_SET_SELB(line, tev_color_env,selb) \
+	FAST_GPFLAGSET(line, tev_color_env,selb,TEV_COLOR_ENV_SELB)
+
+#define SC_TEV_COLOR_ENV_SET_SELA(line, tev_color_env,sela) \
+	FAST_GPFLAGSET(line, tev_color_env,sela,TEV_COLOR_ENV_SELA)
+
+#define SC_TEV_COLOR_ENV_SET_BIAS(line, tev_color_env,bias) \
+	FAST_GPFLAGSET(line, tev_color_env,bias,TEV_COLOR_ENV_BIAS)
+
+#define SC_TEV_COLOR_ENV_SET_SUB(line, tev_color_env,sub) \
+	FAST_GPFLAGSET(line, tev_color_env,sub,TEV_COLOR_ENV_SUB)
+
+#define SC_TEV_COLOR_ENV_SET_CLAMP(line, tev_color_env,clamp) \
+	FAST_GPFLAGSET(line, tev_color_env,clamp,TEV_COLOR_ENV_CLAMP)
+
+#define SC_TEV_COLOR_ENV_SET_SHIFT(line, tev_color_env,shift) \
+	FAST_GPFLAGSET(line, tev_color_env,shift,TEV_COLOR_ENV_SHIFT)
+
+#define SC_TEV_COLOR_ENV_SET_DEST(line, tev_color_env,dest) \
+	FAST_GPFLAGSET(line, tev_color_env,dest,TEV_COLOR_ENV_DEST)
+
+#define SC_TEV_COLOR_ENV_SET_RID(line, tev_color_env,rid) \
+	FAST_GPFLAGSET(line, tev_color_env,rid,TEV_COLOR_ENV_RID)
+
+#define SC_TEV_ALPHA_ENV_SET_MODE(line, tev_alpha_env,mode) \
+	FAST_GPFLAGSET(line, tev_alpha_env,mode,TEV_ALPHA_ENV_MODE)
+
+#define SC_TEV_ALPHA_ENV_SET_SWAP(line, tev_alpha_env,swap) \
+	FAST_GPFLAGSET(line, tev_alpha_env,swap,TEV_ALPHA_ENV_SWAP)
+
+#define SC_TEV_ALPHA_ENV_SET_SELD(line, tev_alpha_env,seld) \
+	FAST_GPFLAGSET(line, tev_alpha_env,seld,TEV_ALPHA_ENV_SELD)
+
+#define SC_TEV_ALPHA_ENV_SET_SELC(line, tev_alpha_env,selc) \
+	FAST_GPFLAGSET(line, tev_alpha_env,selc,TEV_ALPHA_ENV_SELC)
+
+#define SC_TEV_ALPHA_ENV_SET_SELB(line, tev_alpha_env,selb) \
+	FAST_GPFLAGSET(line, tev_alpha_env,selb,TEV_ALPHA_ENV_SELB)
+
+#define SC_TEV_ALPHA_ENV_SET_SELA(line, tev_alpha_env,sela) \
+	FAST_GPFLAGSET(line, tev_alpha_env,sela,TEV_ALPHA_ENV_SELA)
+
+#define SC_TEV_ALPHA_ENV_SET_BIAS(line, tev_alpha_env,bias) \
+	FAST_GPFLAGSET(line, tev_alpha_env,bias,TEV_ALPHA_ENV_BIAS)
+
+#define SC_TEV_ALPHA_ENV_SET_SUB(line, tev_alpha_env,sub) \
+	FAST_GPFLAGSET(line, tev_alpha_env,sub,TEV_ALPHA_ENV_SUB)
+
+#define SC_TEV_ALPHA_ENV_SET_CLAMP(line, tev_alpha_env,clamp) \
+	FAST_GPFLAGSET(line, tev_alpha_env,clamp,TEV_ALPHA_ENV_CLAMP)
+
+#define SC_TEV_ALPHA_ENV_SET_SHIFT(line, tev_alpha_env,shift) \
+	FAST_GPFLAGSET(line, tev_alpha_env,shift,TEV_ALPHA_ENV_SHIFT)
+
+#define SC_TEV_ALPHA_ENV_SET_DEST(line, tev_alpha_env,dest) \
+	FAST_GPFLAGSET(line, tev_alpha_env,dest,TEV_ALPHA_ENV_DEST)
+
+#define SC_TEV_ALPHA_ENV_SET_RID(line, tev_alpha_env,rid) \
+	FAST_GPFLAGSET(line, tev_alpha_env,rid,TEV_ALPHA_ENV_RID)
+
+#define SC_TEV_REGISTERL_SET_R(line, tev_registerl,r) \
+	FAST_GPFLAGSET(line, tev_registerl,r,TEV_REGISTERL_R)
+
+#define SC_TEV_REGISTERL_SET_PAD0(line, tev_registerl,pad0) \
+	FAST_GPFLAGSET(line, tev_registerl,pad0,TEV_REGISTERL_PAD0)
+
+#define SC_TEV_REGISTERL_SET_A(line, tev_registerl,a) \
+	FAST_GPFLAGSET(line, tev_registerl,a,TEV_REGISTERL_A)
+
+#define SC_TEV_REGISTERL_SET_PAD1(line, tev_registerl,pad1) \
+	FAST_GPFLAGSET(line, tev_registerl,pad1,TEV_REGISTERL_PAD1)
+
+#define SC_TEV_REGISTERL_SET_RID(line, tev_registerl,rid) \
+	FAST_GPFLAGSET(line, tev_registerl,rid,TEV_REGISTERL_RID)
+
+#define SC_TEV_REGISTERH_SET_B(line, tev_registerh,b) \
+	FAST_GPFLAGSET(line, tev_registerh,b,TEV_REGISTERH_B)
+
+#define SC_TEV_REGISTERH_SET_PAD0(line, tev_registerh,pad0) \
+	FAST_GPFLAGSET(line, tev_registerh,pad0,TEV_REGISTERH_PAD0)
+
+#define SC_TEV_REGISTERH_SET_G(line, tev_registerh,g) \
+	FAST_GPFLAGSET(line, tev_registerh,g,TEV_REGISTERH_G)
+
+#define SC_TEV_REGISTERH_SET_PAD1(line, tev_registerh,pad1) \
+	FAST_GPFLAGSET(line, tev_registerh,pad1,TEV_REGISTERH_PAD1)
+
+#define SC_TEV_REGISTERH_SET_RID(line, tev_registerh,rid) \
+	FAST_GPFLAGSET(line, tev_registerh,rid,TEV_REGISTERH_RID)
+
+#define SC_TEV_KREGISTERL_SET_R(line, tev_kregisterl,r) \
+	FAST_GPFLAGSET(line, tev_kregisterl,r,TEV_KREGISTERL_R)
+
+#define SC_TEV_KREGISTERL_SET_PAD0(line, tev_kregisterl,pad0) \
+	FAST_GPFLAGSET(line, tev_kregisterl,pad0,TEV_KREGISTERL_PAD0)
+
+#define SC_TEV_KREGISTERL_SET_A(line, tev_kregisterl,a) \
+	FAST_GPFLAGSET(line, tev_kregisterl,a,TEV_KREGISTERL_A)
+
+#define SC_TEV_KREGISTERL_SET_PAD1(line, tev_kregisterl,pad1) \
+	FAST_GPFLAGSET(line, tev_kregisterl,pad1,TEV_KREGISTERL_PAD1)
+
+#define SC_TEV_KREGISTERL_SET_RID(line, tev_kregisterl,rid) \
+	FAST_GPFLAGSET(line, tev_kregisterl,rid,TEV_KREGISTERL_RID)
+
+#define SC_TEV_KREGISTERH_SET_B(line, tev_kregisterh,b) \
+	FAST_GPFLAGSET(line, tev_kregisterh,b,TEV_KREGISTERH_B)
+
+#define SC_TEV_KREGISTERH_SET_PAD0(line, tev_kregisterh,pad0) \
+	FAST_GPFLAGSET(line, tev_kregisterh,pad0,TEV_KREGISTERH_PAD0)
+
+#define SC_TEV_KREGISTERH_SET_G(line, tev_kregisterh,g) \
+	FAST_GPFLAGSET(line, tev_kregisterh,g,TEV_KREGISTERH_G)
+
+#define SC_TEV_KREGISTERH_SET_PAD1(line, tev_kregisterh,pad1) \
+	FAST_GPFLAGSET(line, tev_kregisterh,pad1,TEV_KREGISTERH_PAD1)
+
+#define SC_TEV_KREGISTERH_SET_RID(line, tev_kregisterh,rid) \
+	FAST_GPFLAGSET(line, tev_kregisterh,rid,TEV_KREGISTERH_RID)
+
+#define SC_TEV_FOG_PARAM_0_SET_A_MANT(line, tev_fog_param_0,a_mant) \
+	FAST_GPFLAGSET(line, tev_fog_param_0,a_mant,TEV_FOG_PARAM_0_A_MANT)
+
+#define SC_TEV_FOG_PARAM_0_SET_A_EXPN(line, tev_fog_param_0,a_expn) \
+	FAST_GPFLAGSET(line, tev_fog_param_0,a_expn,TEV_FOG_PARAM_0_A_EXPN)
+
+#define SC_TEV_FOG_PARAM_0_SET_A_SIGN(line, tev_fog_param_0,a_sign) \
+	FAST_GPFLAGSET(line, tev_fog_param_0,a_sign,TEV_FOG_PARAM_0_A_SIGN)
+
+#define SC_TEV_FOG_PARAM_0_SET_PAD0(line, tev_fog_param_0,pad0) \
+	FAST_GPFLAGSET(line, tev_fog_param_0,pad0,TEV_FOG_PARAM_0_PAD0)
+
+#define SC_TEV_FOG_PARAM_0_SET_RID(line, tev_fog_param_0,rid) \
+	FAST_GPFLAGSET(line, tev_fog_param_0,rid,TEV_FOG_PARAM_0_RID)
+
+#define SC_TEV_FOG_PARAM_1_SET_B_MAG(line, tev_fog_param_1,b_mag) \
+	FAST_GPFLAGSET(line, tev_fog_param_1,b_mag,TEV_FOG_PARAM_1_B_MAG)
+
+#define SC_TEV_FOG_PARAM_1_SET_RID(line, tev_fog_param_1,rid) \
+	FAST_GPFLAGSET(line, tev_fog_param_1,rid,TEV_FOG_PARAM_1_RID)
+
+#define SC_TEV_FOG_PARAM_2_SET_B_SHF(line, tev_fog_param_2,b_shf) \
+	FAST_GPFLAGSET(line, tev_fog_param_2,b_shf,TEV_FOG_PARAM_2_B_SHF)
+
+#define SC_TEV_FOG_PARAM_2_SET_PAD0(line, tev_fog_param_2,pad0) \
+	FAST_GPFLAGSET(line, tev_fog_param_2,pad0,TEV_FOG_PARAM_2_PAD0)
+
+#define SC_TEV_FOG_PARAM_2_SET_RID(line, tev_fog_param_2,rid) \
+	FAST_GPFLAGSET(line, tev_fog_param_2,rid,TEV_FOG_PARAM_2_RID)
+
+#define SC_TEV_FOG_PARAM_3_SET_C_MANT(line, tev_fog_param_3,c_mant) \
+	FAST_GPFLAGSET(line, tev_fog_param_3,c_mant,TEV_FOG_PARAM_3_C_MANT)
+
+#define SC_TEV_FOG_PARAM_3_SET_C_EXPN(line, tev_fog_param_3,c_expn) \
+	FAST_GPFLAGSET(line, tev_fog_param_3,c_expn,TEV_FOG_PARAM_3_C_EXPN)
+
+#define SC_TEV_FOG_PARAM_3_SET_C_SIGN(line, tev_fog_param_3,c_sign) \
+	FAST_GPFLAGSET(line, tev_fog_param_3,c_sign,TEV_FOG_PARAM_3_C_SIGN)
+
+#define SC_TEV_FOG_PARAM_3_SET_PROJ(line, tev_fog_param_3,proj) \
+	FAST_GPFLAGSET(line, tev_fog_param_3,proj,TEV_FOG_PARAM_3_PROJ)
+
+#define SC_TEV_FOG_PARAM_3_SET_FSEL(line, tev_fog_param_3,fsel) \
+	FAST_GPFLAGSET(line, tev_fog_param_3,fsel,TEV_FOG_PARAM_3_FSEL)
+
+#define SC_TEV_FOG_PARAM_3_SET_RID(line, tev_fog_param_3,rid) \
+	FAST_GPFLAGSET(line, tev_fog_param_3,rid,TEV_FOG_PARAM_3_RID)
+
+#define SC_TEV_RANGE_ADJ_C_SET_CENTER(line, tev_range_adj_c,center) \
+	FAST_GPFLAGSET(line, tev_range_adj_c,center,TEV_RANGE_ADJ_C_CENTER)
+
+#define SC_TEV_RANGE_ADJ_C_SET_ENB(line, tev_range_adj_c,enb) \
+	FAST_GPFLAGSET(line, tev_range_adj_c,enb,TEV_RANGE_ADJ_C_ENB)
+
+#define SC_TEV_RANGE_ADJ_C_SET_PAD0(line, tev_range_adj_c,pad0) \
+	FAST_GPFLAGSET(line, tev_range_adj_c,pad0,TEV_RANGE_ADJ_C_PAD0)
+
+#define SC_TEV_RANGE_ADJ_C_SET_RID(line, tev_range_adj_c,rid) \
+	FAST_GPFLAGSET(line, tev_range_adj_c,rid,TEV_RANGE_ADJ_C_RID)
+
+#define SC_TEV_RANGE_ADJ_SET_R0(line, tev_range_adj,r0) \
+	FAST_GPFLAGSET(line, tev_range_adj,r0,TEV_RANGE_ADJ_R0)
+
+#define SC_TEV_RANGE_ADJ_SET_R1(line, tev_range_adj,r1) \
+	FAST_GPFLAGSET(line, tev_range_adj,r1,TEV_RANGE_ADJ_R1)
+
+#define SC_TEV_RANGE_ADJ_SET_RID(line, tev_range_adj,rid) \
+	FAST_GPFLAGSET(line, tev_range_adj,rid,TEV_RANGE_ADJ_RID)
+
+#define SC_TEV_FOG_COLOR_SET_B(line, tev_fog_color,b) \
+	FAST_GPFLAGSET(line, tev_fog_color,b,TEV_FOG_COLOR_B)
+
+#define SC_TEV_FOG_COLOR_SET_G(line, tev_fog_color,g) \
+	FAST_GPFLAGSET(line, tev_fog_color,g,TEV_FOG_COLOR_G)
+
+#define SC_TEV_FOG_COLOR_SET_R(line, tev_fog_color,r) \
+	FAST_GPFLAGSET(line, tev_fog_color,r,TEV_FOG_COLOR_R)
+
+#define SC_TEV_FOG_COLOR_SET_RID(line, tev_fog_color,rid) \
+	FAST_GPFLAGSET(line, tev_fog_color,rid,TEV_FOG_COLOR_RID)
+
+#define SC_TEV_ALPHAFUNC_SET_A0(line, tev_alphafunc,a0) \
+	FAST_GPFLAGSET(line, tev_alphafunc,a0,TEV_ALPHAFUNC_A0)
+
+#define SC_TEV_ALPHAFUNC_SET_A1(line, tev_alphafunc,a1) \
+	FAST_GPFLAGSET(line, tev_alphafunc,a1,TEV_ALPHAFUNC_A1)
+
+#define SC_TEV_ALPHAFUNC_SET_OP0(line, tev_alphafunc,op0) \
+	FAST_GPFLAGSET(line, tev_alphafunc,op0,TEV_ALPHAFUNC_OP0)
+
+#define SC_TEV_ALPHAFUNC_SET_OP1(line, tev_alphafunc,op1) \
+	FAST_GPFLAGSET(line, tev_alphafunc,op1,TEV_ALPHAFUNC_OP1)
+
+#define SC_TEV_ALPHAFUNC_SET_LOGIC(line, tev_alphafunc,logic) \
+	FAST_GPFLAGSET(line, tev_alphafunc,logic,TEV_ALPHAFUNC_LOGIC)
+
+#define SC_TEV_ALPHAFUNC_SET_RID(line, tev_alphafunc,rid) \
+	FAST_GPFLAGSET(line, tev_alphafunc,rid,TEV_ALPHAFUNC_RID)
+
+#define SC_TEV_Z_ENV_0_SET_ZOFF(line, tev_z_env_0,zoff) \
+	FAST_GPFLAGSET(line, tev_z_env_0,zoff,TEV_Z_ENV_0_ZOFF)
+
+#define SC_TEV_Z_ENV_0_SET_RID(line, tev_z_env_0,rid) \
+	FAST_GPFLAGSET(line, tev_z_env_0,rid,TEV_Z_ENV_0_RID)
+
+#define SC_TEV_Z_ENV_1_SET_TYPE(line, tev_z_env_1,type) \
+	FAST_GPFLAGSET(line, tev_z_env_1,type,TEV_Z_ENV_1_TYPE)
+
+#define SC_TEV_Z_ENV_1_SET_OP(line, tev_z_env_1,op) \
+	FAST_GPFLAGSET(line, tev_z_env_1,op,TEV_Z_ENV_1_OP)
+
+#define SC_TEV_Z_ENV_1_SET_PAD0(line, tev_z_env_1,pad0) \
+	FAST_GPFLAGSET(line, tev_z_env_1,pad0,TEV_Z_ENV_1_PAD0)
+
+#define SC_TEV_Z_ENV_1_SET_RID(line, tev_z_env_1,rid) \
+	FAST_GPFLAGSET(line, tev_z_env_1,rid,TEV_Z_ENV_1_RID)
+
+#define SC_TEV_KSEL_SET_XRB(line, tev_ksel,xrb) \
+	FAST_GPFLAGSET(line, tev_ksel,xrb,TEV_KSEL_XRB)
+
+#define SC_TEV_KSEL_SET_XGA(line, tev_ksel,xga) \
+	FAST_GPFLAGSET(line, tev_ksel,xga,TEV_KSEL_XGA)
+
+#define SC_TEV_KSEL_SET_KCSEL0(line, tev_ksel,kcsel0) \
+	FAST_GPFLAGSET(line, tev_ksel,kcsel0,TEV_KSEL_KCSEL0)
+
+#define SC_TEV_KSEL_SET_KASEL0(line, tev_ksel,kasel0) \
+	FAST_GPFLAGSET(line, tev_ksel,kasel0,TEV_KSEL_KASEL0)
+
+#define SC_TEV_KSEL_SET_KCSEL1(line, tev_ksel,kcsel1) \
+	FAST_GPFLAGSET(line, tev_ksel,kcsel1,TEV_KSEL_KCSEL1)
+
+#define SC_TEV_KSEL_SET_KASEL1(line, tev_ksel,kasel1) \
+	FAST_GPFLAGSET(line, tev_ksel,kasel1,TEV_KSEL_KASEL1)
+
+#define SC_TEV_KSEL_SET_RID(line, tev_ksel,rid) \
+	FAST_GPFLAGSET(line, tev_ksel,rid,TEV_KSEL_RID)
+
+
+#endif // TEV_REG_H
diff --git a/include/revolution/private/tx_reg.h b/include/revolution/private/tx_reg.h
new file mode 100644
index 0000000000..cf61cd1ac2
--- /dev/null
+++ b/include/revolution/private/tx_reg.h
@@ -0,0 +1,125 @@
+#ifndef TX_REG_H
+#define TX_REG_H
+
+#define TX_REFRESH_INTERVAL_SIZE        10
+#define TX_REFRESH_INTERVAL_SHIFT       0
+#define TX_REFRESH_INTERVAL_MASK        0x000003ff
+#define TX_REFRESH_GET_INTERVAL(tx_refresh) \
+        ((((unsigned long)(tx_refresh)) & TX_REFRESH_INTERVAL_MASK) >> TX_REFRESH_INTERVAL_SHIFT)
+
+#define TX_REFRESH_ENABLE_SIZE  1
+#define TX_REFRESH_ENABLE_SHIFT 10
+#define TX_REFRESH_ENABLE_MASK  0x00000400
+#define TX_REFRESH_GET_ENABLE(tx_refresh) \
+        ((((unsigned long)(tx_refresh)) & TX_REFRESH_ENABLE_MASK) >> TX_REFRESH_ENABLE_SHIFT)
+
+#define TX_REFRESH_PAD0_SIZE    13
+#define TX_REFRESH_PAD0_SHIFT   11
+#define TX_REFRESH_PAD0_MASK    0x00fff800
+#define TX_REFRESH_GET_PAD0(tx_refresh) \
+        ((((unsigned long)(tx_refresh)) & TX_REFRESH_PAD0_MASK) >> TX_REFRESH_PAD0_SHIFT)
+#define TX_REFRESH_SET_PAD0(tx_refresh, pad0) { \
+        FDL_ASSERT(!((pad0) & ~((1 << TX_REFRESH_PAD0_SIZE)-1))); \
+        tx_refresh = (((unsigned long)(tx_refresh)) & ~TX_REFRESH_PAD0_MASK) | (((unsigned long)(pad0)) << TX_REFRESH_PAD0_SHIFT);\
+}
+#define TX_REFRESH_RID_SIZE     8
+#define TX_REFRESH_RID_SHIFT    24
+#define TX_REFRESH_RID_MASK     0xff000000
+#define TX_REFRESH_GET_RID(tx_refresh) \
+        ((((unsigned long)(tx_refresh)) & TX_REFRESH_RID_MASK) >> TX_REFRESH_RID_SHIFT)
+#define TX_REFRESH_SET_RID(tx_refresh, rid) { \
+        FDL_ASSERT(!((rid) & ~((1 << TX_REFRESH_RID_SIZE)-1))); \
+        tx_refresh = (((unsigned long)(tx_refresh)) & ~TX_REFRESH_RID_MASK) | (((unsigned long)(rid)) << TX_REFRESH_RID_SHIFT);\
+}
+#define TX_REFRESH_TOTAL_SIZE   32
+#define TX_REFRESH(interval, enable, rid) \
+        ((((unsigned long)(interval)) << TX_REFRESH_INTERVAL_SHIFT) | \
+         (((unsigned long)(enable)) << TX_REFRESH_ENABLE_SHIFT) | \
+         (((unsigned long)(rid)) << TX_REFRESH_RID_SHIFT))
+
+#define TX_PERFMODE_SEL3_SIZE   5
+#define TX_PERFMODE_SEL3_SHIFT  0
+#define TX_PERFMODE_SEL3_MASK   0x0000001f
+#define TX_PERFMODE_GET_SEL3(tx_perfmode) \
+        ((((unsigned long)(tx_perfmode)) & TX_PERFMODE_SEL3_MASK) >> TX_PERFMODE_SEL3_SHIFT)
+
+#define TX_PERFMODE_SEL2_SIZE   5
+#define TX_PERFMODE_SEL2_SHIFT  5
+#define TX_PERFMODE_SEL2_MASK   0x000003e0
+#define TX_PERFMODE_GET_SEL2(tx_perfmode) \
+        ((((unsigned long)(tx_perfmode)) & TX_PERFMODE_SEL2_MASK) >> TX_PERFMODE_SEL2_SHIFT)
+
+#define TX_PERFMODE_SEL1_SIZE   5
+#define TX_PERFMODE_SEL1_SHIFT  10
+#define TX_PERFMODE_SEL1_MASK   0x00007c00
+#define TX_PERFMODE_GET_SEL1(tx_perfmode) \
+        ((((unsigned long)(tx_perfmode)) & TX_PERFMODE_SEL1_MASK) >> TX_PERFMODE_SEL1_SHIFT)
+
+#define TX_PERFMODE_SEL0_SIZE   5
+#define TX_PERFMODE_SEL0_SHIFT  15
+#define TX_PERFMODE_SEL0_MASK   0x000f8000
+#define TX_PERFMODE_GET_SEL0(tx_perfmode) \
+        ((((unsigned long)(tx_perfmode)) & TX_PERFMODE_SEL0_MASK) >> TX_PERFMODE_SEL0_SHIFT)
+
+#define TX_PERFMODE_PAD0_SIZE   4
+#define TX_PERFMODE_PAD0_SHIFT  20
+#define TX_PERFMODE_PAD0_MASK   0x00f00000
+#define TX_PERFMODE_GET_PAD0(tx_perfmode) \
+        ((((unsigned long)(tx_perfmode)) & TX_PERFMODE_PAD0_MASK) >> TX_PERFMODE_PAD0_SHIFT)
+
+#define TX_PERFMODE_RID_SIZE    8
+#define TX_PERFMODE_RID_SHIFT   24
+#define TX_PERFMODE_RID_MASK    0xff000000
+#define TX_PERFMODE_GET_RID(tx_perfmode) \
+        ((((unsigned long)(tx_perfmode)) & TX_PERFMODE_RID_MASK) >> TX_PERFMODE_RID_SHIFT)
+
+#define TX_PERFMODE_TOTAL_SIZE  32
+#define TX_PERFMODE(sel3, sel2, sel1, sel0, rid) \
+        ((((unsigned long)(sel3)) << TX_PERFMODE_SEL3_SHIFT) | \
+        (((unsigned long)(sel2)) << TX_PERFMODE_SEL2_SHIFT) | \
+        (((unsigned long)(sel1)) << TX_PERFMODE_SEL1_SHIFT) | \
+        (((unsigned long)(sel0)) << TX_PERFMODE_SEL0_SHIFT) | \
+        (((unsigned long)(rid)) << TX_PERFMODE_RID_SHIFT))
+
+#define TX_LOADBLOCK3_COUNT_SIZE        15
+#define TX_LOADBLOCK3_COUNT_SHIFT       0
+#define TX_LOADBLOCK3_COUNT_MASK        0x00007fff
+#define TX_LOADBLOCK3_GET_COUNT(tx_loadblock3) \
+        ((((unsigned long)(tx_loadblock3)) & TX_LOADBLOCK3_COUNT_MASK) >> TX_LOADBLOCK3_COUNT_SHIFT)
+#define TX_LOADBLOCK3_SET_COUNT(tx_loadblock3, count) { \
+        FDL_ASSERT(!((count) & ~((1 << TX_LOADBLOCK3_COUNT_SIZE)-1))); \
+        tx_loadblock3 = (((unsigned long)(tx_loadblock3)) & ~TX_LOADBLOCK3_COUNT_MASK) | (((unsigned long)(count)) << TX_LOADBLOCK3_COUNT_SHIFT);\
+}
+#define TX_LOADBLOCK3_FORMAT_SIZE       2
+#define TX_LOADBLOCK3_FORMAT_SHIFT      15
+#define TX_LOADBLOCK3_FORMAT_MASK       0x00018000
+#define TX_LOADBLOCK3_GET_FORMAT(tx_loadblock3) \
+        ((((unsigned long)(tx_loadblock3)) & TX_LOADBLOCK3_FORMAT_MASK) >> TX_LOADBLOCK3_FORMAT_SHIFT)
+#define TX_LOADBLOCK3_SET_FORMAT(tx_loadblock3, format) { \
+        FDL_ASSERT(!((format) & ~((1 << TX_LOADBLOCK3_FORMAT_SIZE)-1))); \
+        tx_loadblock3 = (((unsigned long)(tx_loadblock3)) & ~TX_LOADBLOCK3_FORMAT_MASK) | (((unsigned long)(format)) << TX_LOADBLOCK3_FORMAT_SHIFT);\
+}
+#define TX_LOADBLOCK3_PAD0_SIZE 7
+#define TX_LOADBLOCK3_PAD0_SHIFT        17
+#define TX_LOADBLOCK3_PAD0_MASK 0x00fe0000
+#define TX_LOADBLOCK3_GET_PAD0(tx_loadblock3) \
+        ((((unsigned long)(tx_loadblock3)) & TX_LOADBLOCK3_PAD0_MASK) >> TX_LOADBLOCK3_PAD0_SHIFT)
+#define TX_LOADBLOCK3_SET_PAD0(tx_loadblock3, pad0) { \
+        FDL_ASSERT(!((pad0) & ~((1 << TX_LOADBLOCK3_PAD0_SIZE)-1))); \
+        tx_loadblock3 = (((unsigned long)(tx_loadblock3)) & ~TX_LOADBLOCK3_PAD0_MASK) | (((unsigned long)(pad0)) << TX_LOADBLOCK3_PAD0_SHIFT);\
+}
+#define TX_LOADBLOCK3_RID_SIZE  8
+#define TX_LOADBLOCK3_RID_SHIFT 24
+#define TX_LOADBLOCK3_RID_MASK  0xff000000
+#define TX_LOADBLOCK3_GET_RID(tx_loadblock3) \
+        ((((unsigned long)(tx_loadblock3)) & TX_LOADBLOCK3_RID_MASK) >> TX_LOADBLOCK3_RID_SHIFT)
+#define TX_LOADBLOCK3_SET_RID(tx_loadblock3, rid) { \
+        FDL_ASSERT(!((rid) & ~((1 << TX_LOADBLOCK3_RID_SIZE)-1))); \
+        tx_loadblock3 = (((unsigned long)(tx_loadblock3)) & ~TX_LOADBLOCK3_RID_MASK) | (((unsigned long)(rid)) << TX_LOADBLOCK3_RID_SHIFT);\
+}
+#define TX_LOADBLOCK3_TOTAL_SIZE        32
+#define TX_LOADBLOCK3(count, format, rid) \
+        ((((unsigned long)(count)) << TX_LOADBLOCK3_COUNT_SHIFT) | \
+         (((unsigned long)(format)) << TX_LOADBLOCK3_FORMAT_SHIFT) | \
+         (((unsigned long)(rid)) << TX_LOADBLOCK3_RID_SHIFT))
+#endif // TX_REG_H
diff --git a/include/revolution/private/xf_mem.h b/include/revolution/private/xf_mem.h
new file mode 100644
index 0000000000..cf708e8646
--- /dev/null
+++ b/include/revolution/private/xf_mem.h
@@ -0,0 +1,749 @@
+#ifndef XF_MEM_H
+#define XF_MEM_H
+
+#define XF_TEXGEN_REGULAR	0x00000000
+#define XF_TEXGEN_BUMP_MAP	0x00000001
+#define XF_TEXGEN_COLOR_STRGBC0	0x00000002
+#define XF_TEXGEN_COLOR_STRGBC1	0x00000003
+#define XF_TEX_TEXGEN_TYPE_F_UNUSED_4	0x00000004
+#define XF_TEX_TEXGEN_TYPE_F_UNUSED_5	0x00000005
+#define XF_TEX_TEXGEN_TYPE_F_UNUSED_6	0x00000006
+#define XF_TEX_TEXGEN_TYPE_F_UNUSED_7	0x00000007
+
+#define XF_ERROR_F_CTEX_BUG_ENABLE_SIZE	1
+#define XF_ERROR_F_CTEX_BUG_ENABLE_SHIFT	0
+#define XF_ERROR_F_CTEX_BUG_ENABLE_MASK	0x00000001
+#define XF_ERROR_F_GET_CTEX_BUG_ENABLE(xf_error_f) \
+	((((unsigned long)(xf_error_f)) & XF_ERROR_F_CTEX_BUG_ENABLE_MASK) >> XF_ERROR_F_CTEX_BUG_ENABLE_SHIFT)
+
+#define XF_ERROR_F_TFAN4_BUG_ENABLE_SIZE	1
+#define XF_ERROR_F_TFAN4_BUG_ENABLE_SHIFT	1
+#define XF_ERROR_F_TFAN4_BUG_ENABLE_MASK	0x00000002
+#define XF_ERROR_F_GET_TFAN4_BUG_ENABLE(xf_error_f) \
+	((((unsigned long)(xf_error_f)) & XF_ERROR_F_TFAN4_BUG_ENABLE_MASK) >> XF_ERROR_F_TFAN4_BUG_ENABLE_SHIFT)
+
+#define XF_ERROR_F_TFAN16_BUG_ENABLE_SIZE	1
+#define XF_ERROR_F_TFAN16_BUG_ENABLE_SHIFT	2
+#define XF_ERROR_F_TFAN16_BUG_ENABLE_MASK	0x00000004
+#define XF_ERROR_F_GET_TFAN16_BUG_ENABLE(xf_error_f) \
+    ((((unsigned long)(xf_error_f)) & XF_ERROR_F_TFAN16_BUG_ENABLE_MASK) >> XF_ERROR_F_TFAN16_BUG_ENABLE_SHIFT)
+
+#define XF_ERROR_F_DUALTRAN_REG_ENABLE_SIZE	1
+#define XF_ERROR_F_DUALTRAN_REG_ENABLE_SHIFT	3
+#define XF_ERROR_F_DUALTRAN_REG_ENABLE_MASK	0x00000008
+#define XF_ERROR_F_GET_DUALTRAN_REG_ENABLE(xf_error_f) \
+    ((((unsigned long)(xf_error_f)) & XF_ERROR_F_DUALTRAN_REG_ENABLE_MASK) >> XF_ERROR_F_DUALTRAN_REG_ENABLE_SHIFT)
+
+#define XF_ERROR_F_BYPASS_BUG_ENABLE_SIZE	1
+#define XF_ERROR_F_BYPASS_BUG_ENABLE_SHIFT	4
+#define XF_ERROR_F_BYPASS_BUG_ENABLE_MASK	0x00000010
+#define XF_ERROR_F_GET_BYPASS_BUG_ENABLE(xf_error_f) \
+    ((((unsigned long)(xf_error_f)) & XF_ERROR_F_BYPASS_BUG_ENABLE_MASK) >> XF_ERROR_F_BYPASS_BUG_ENABLE_SHIFT)
+
+#define XF_ERROR_F_FAST_MATRIX_ENABLE_SIZE	1
+#define XF_ERROR_F_FAST_MATRIX_ENABLE_SHIFT	5
+#define XF_ERROR_F_FAST_MATRIX_ENABLE_MASK	0x00000020
+#define XF_ERROR_F_GET_FAST_MATRIX_ENABLE(xf_error_f) \
+    ((((unsigned long)(xf_error_f)) & XF_ERROR_F_FAST_MATRIX_ENABLE_MASK) >> XF_ERROR_F_FAST_MATRIX_ENABLE_SHIFT)
+
+#define XF_DUALTEXTRAN_F_DUALTEXTRAN_ENABLE_SIZE	1
+#define XF_DUALTEXTRAN_F_DUALTEXTRAN_ENABLE_SHIFT	0
+#define XF_DUALTEXTRAN_F_DUALTEXTRAN_ENABLE_MASK	0x00000001
+#define XF_DUALTEXTRAN_F_GET_DUALTEXTRAN_ENABLE(xf_dualtextran_f) \
+    ((((unsigned long)(xf_dualtextran_f)) & XF_DUALTEXTRAN_F_DUALTEXTRAN_ENABLE_MASK) >> XF_DUALTEXTRAN_F_DUALTEXTRAN_ENABLE_SHIFT)
+
+#define XF_PERF0_F(perf_a, perf_b, perf_c, perf_d) \
+((((unsigned long)(perf_a)) << XF_PERF0_F_PERF_A_SHIFT) | \
+    (((unsigned long)(perf_b)) << XF_PERF0_F_PERF_B_SHIFT) | \
+    (((unsigned long)(perf_c)) << XF_PERF0_F_PERF_C_SHIFT) | \
+    (((unsigned long)(perf_d)) << XF_PERF0_F_PERF_D_SHIFT))
+
+#define XF_INVERTEXSPEC_F_HOST_COLORS_SIZE	2
+#define XF_INVERTEXSPEC_F_HOST_COLORS_SHIFT	0
+#define XF_INVERTEXSPEC_F_HOST_COLORS_MASK	0x00000003
+#define XF_INVERTEXSPEC_F_GET_HOST_COLORS(xf_invertexspec_f) \
+    ((((unsigned long)(xf_invertexspec_f)) & XF_INVERTEXSPEC_F_HOST_COLORS_MASK) >> XF_INVERTEXSPEC_F_HOST_COLORS_SHIFT)
+
+#define XF_INVERTEXSPEC_F_HOST_NORMAL_SIZE	2
+#define XF_INVERTEXSPEC_F_HOST_NORMAL_SHIFT	2
+#define XF_INVERTEXSPEC_F_HOST_NORMAL_MASK	0x0000000c
+#define XF_INVERTEXSPEC_F_GET_HOST_NORMAL(xf_invertexspec_f) \
+    ((((unsigned long)(xf_invertexspec_f)) & XF_INVERTEXSPEC_F_HOST_NORMAL_MASK) >> XF_INVERTEXSPEC_F_HOST_NORMAL_SHIFT)
+
+#define XF_INVERTEXSPEC_F_HOST_TEXTURES_SIZE	4
+#define XF_INVERTEXSPEC_F_HOST_TEXTURES_SHIFT	4
+#define XF_INVERTEXSPEC_F_HOST_TEXTURES_MASK	0x000000f0
+#define XF_INVERTEXSPEC_F_GET_HOST_TEXTURES(xf_invertexspec_f) \
+    ((((unsigned long)(xf_invertexspec_f)) & XF_INVERTEXSPEC_F_HOST_TEXTURES_MASK) >> XF_INVERTEXSPEC_F_HOST_TEXTURES_SHIFT)
+
+#define XF_INVERTEXSPEC_F_TOTAL_SIZE	8
+#define XF_INVERTEXSPEC_F_UNUSED_SIZE	24
+
+#define XF_INVERTEXSPEC_F(host_colors, host_normal, host_textures) \
+    ((((unsigned long)(host_colors)) << XF_INVERTEXSPEC_F_HOST_COLORS_SHIFT) | \
+    (((unsigned long)(host_normal)) << XF_INVERTEXSPEC_F_HOST_NORMAL_SHIFT) | \
+    (((unsigned long)(host_textures)) << XF_INVERTEXSPEC_F_HOST_TEXTURES_SHIFT))
+             
+#define XF_TEX_RESERVED0_SIZE	1
+#define XF_TEX_RESERVED0_SHIFT	0
+#define XF_TEX_RESERVED0_MASK	0x00000001
+#define XF_TEX_GET_RESERVED0(xf_tex) \
+    ((((unsigned long)(xf_tex)) & XF_TEX_RESERVED0_MASK) >> XF_TEX_RESERVED0_SHIFT)
+
+#define XF_TEX_PROJECTION_SIZE	1
+#define XF_TEX_PROJECTION_SHIFT	1
+#define XF_TEX_PROJECTION_MASK	0x00000002
+#define XF_TEX_GET_PROJECTION(xf_tex) \
+    ((((unsigned long)(xf_tex)) & XF_TEX_PROJECTION_MASK) >> XF_TEX_PROJECTION_SHIFT)
+
+#define XF_TEX_INPUT_FORM_SIZE	1
+#define XF_TEX_INPUT_FORM_SHIFT	2
+#define XF_TEX_INPUT_FORM_MASK	0x00000004
+#define XF_TEX_GET_INPUT_FORM(xf_tex) \
+    ((((unsigned long)(xf_tex)) & XF_TEX_INPUT_FORM_MASK) >> XF_TEX_INPUT_FORM_SHIFT)
+
+#define XF_TEX_RESERVED1_SIZE	1
+#define XF_TEX_RESERVED1_SHIFT	3
+#define XF_TEX_RESERVED1_MASK	0x00000008
+#define XF_TEX_GET_RESERVED1(xf_tex) \
+    ((((unsigned long)(xf_tex)) & XF_TEX_RESERVED1_MASK) >> XF_TEX_RESERVED1_SHIFT)
+
+#define XF_TEX_TEXGEN_TYPE_SIZE	3
+#define XF_TEX_TEXGEN_TYPE_SHIFT	4
+#define XF_TEX_TEXGEN_TYPE_MASK	0x00000070
+#define XF_TEX_GET_TEXGEN_TYPE(xf_tex) \
+    ((((unsigned long)(xf_tex)) & XF_TEX_TEXGEN_TYPE_MASK) >> XF_TEX_TEXGEN_TYPE_SHIFT)
+
+#define XF_TEX_SOURCE_ROW_SIZE	5
+#define XF_TEX_SOURCE_ROW_SHIFT	7
+#define XF_TEX_SOURCE_ROW_MASK	0x00000f80
+#define XF_TEX_GET_SOURCE_ROW(xf_tex) \
+    ((((unsigned long)(xf_tex)) & XF_TEX_SOURCE_ROW_MASK) >> XF_TEX_SOURCE_ROW_SHIFT)
+
+#define XF_TEX_BUMP_MAP_SOURCE_SIZE	3
+#define XF_TEX_BUMP_MAP_SOURCE_SHIFT	12
+#define XF_TEX_BUMP_MAP_SOURCE_MASK	0x00007000
+#define XF_TEX_GET_BUMP_MAP_SOURCE(xf_tex) \
+    ((((unsigned long)(xf_tex)) & XF_TEX_BUMP_MAP_SOURCE_MASK) >> XF_TEX_BUMP_MAP_SOURCE_SHIFT)
+
+#define XF_TEX_BUMP_MAP_LIGHT_SIZE	3
+#define XF_TEX_BUMP_MAP_LIGHT_SHIFT	15
+#define XF_TEX_BUMP_MAP_LIGHT_MASK	0x00038000
+#define XF_TEX_GET_BUMP_MAP_LIGHT(xf_tex) \
+    ((((unsigned long)(xf_tex)) & XF_TEX_BUMP_MAP_LIGHT_MASK) >> XF_TEX_BUMP_MAP_LIGHT_SHIFT)
+
+#define XF_TEX_TOTAL_SIZE	18
+#define XF_TEX_UNUSED_SIZE	14
+
+#define XF_TEX(reserved0, projection, input_form, reserved1, texgen_type, source_row, bump_map_source, bump_map_light) \
+    ((((unsigned long)(reserved0)) << XF_TEX_RESERVED0_SHIFT) | \
+        (((unsigned long)(projection)) << XF_TEX_PROJECTION_SHIFT) | \
+        (((unsigned long)(input_form)) << XF_TEX_INPUT_FORM_SHIFT) | \
+        (((unsigned long)(reserved1)) << XF_TEX_RESERVED1_SHIFT) | \
+        (((unsigned long)(texgen_type)) << XF_TEX_TEXGEN_TYPE_SHIFT) | \
+        (((unsigned long)(source_row)) << XF_TEX_SOURCE_ROW_SHIFT) | \
+        (((unsigned long)(bump_map_source)) << XF_TEX_BUMP_MAP_SOURCE_SHIFT) | \
+        (((unsigned long)(bump_map_light)) << XF_TEX_BUMP_MAP_LIGHT_SHIFT))
+    
+#define XF_DUALTEX_F_DUALMATRIX_ADRS_SIZE	6
+#define XF_DUALTEX_F_DUALMATRIX_ADRS_SHIFT	0
+#define XF_DUALTEX_F_DUALMATRIX_ADRS_MASK	0x0000003f
+#define XF_DUALTEX_F_GET_DUALMATRIX_ADRS(xf_dualtex_f) \
+    ((((unsigned long)(xf_dualtex_f)) & XF_DUALTEX_F_DUALMATRIX_ADRS_MASK) >> XF_DUALTEX_F_DUALMATRIX_ADRS_SHIFT)
+
+#define XF_DUALTEX_F_RESERVED0_SIZE	2
+#define XF_DUALTEX_F_RESERVED0_SHIFT	6
+#define XF_DUALTEX_F_RESERVED0_MASK	0x000000c0
+#define XF_DUALTEX_F_GET_RESERVED0(xf_dualtex_f) \
+    ((((unsigned long)(xf_dualtex_f)) & XF_DUALTEX_F_RESERVED0_MASK) >> XF_DUALTEX_F_RESERVED0_SHIFT)
+
+#define XF_DUALTEX_F_NORMAL_ENABLE_SIZE	1
+#define XF_DUALTEX_F_NORMAL_ENABLE_SHIFT	8
+#define XF_DUALTEX_F_NORMAL_ENABLE_MASK	0x00000100
+#define XF_DUALTEX_F_GET_NORMAL_ENABLE(xf_dualtex_f) \
+    ((((unsigned long)(xf_dualtex_f)) & XF_DUALTEX_F_NORMAL_ENABLE_MASK) >> XF_DUALTEX_F_NORMAL_ENABLE_SHIFT)
+
+#define XF_DUALTEX_F_TOTAL_SIZE	9
+#define XF_DUALTEX_F_UNUSED_SIZE	23
+
+#define XF_DUALTEX_F(dualmatrix_adrs, reserved0, normal_enable) \
+    ((((unsigned long)(dualmatrix_adrs)) << XF_DUALTEX_F_DUALMATRIX_ADRS_SHIFT) | \
+        (((unsigned long)(reserved0)) << XF_DUALTEX_F_RESERVED0_SHIFT) | \
+        (((unsigned long)(normal_enable)) << XF_DUALTEX_F_NORMAL_ENABLE_SHIFT))
+
+#define XF_PERF0_F_PERF_A_SIZE	5
+#define XF_PERF0_F_PERF_A_SHIFT	0
+#define XF_PERF0_F_PERF_A_MASK	0x0000001f
+#define XF_PERF0_F_GET_PERF_A(xf_perf0_f) \
+    ((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_A_MASK) >> XF_PERF0_F_PERF_A_SHIFT)
+
+#define XF_PERF0_F_PERF_B_SIZE	5
+#define XF_PERF0_F_PERF_B_SHIFT	5
+#define XF_PERF0_F_PERF_B_MASK	0x000003e0
+#define XF_PERF0_F_GET_PERF_B(xf_perf0_f) \
+    ((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_B_MASK) >> XF_PERF0_F_PERF_B_SHIFT)
+
+#define XF_PERF0_F_PERF_C_SIZE	5
+#define XF_PERF0_F_PERF_C_SHIFT	10
+#define XF_PERF0_F_PERF_C_MASK	0x00007c00
+#define XF_PERF0_F_GET_PERF_C(xf_perf0_f) \
+    ((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_C_MASK) >> XF_PERF0_F_PERF_C_SHIFT)
+
+#define XF_PERF0_F_PERF_D_SIZE	5
+#define XF_PERF0_F_PERF_D_SHIFT	15
+#define XF_PERF0_F_PERF_D_MASK	0x000f8000
+#define XF_PERF0_F_GET_PERF_D(xf_perf0_f) \
+    ((((unsigned long)(xf_perf0_f)) & XF_PERF0_F_PERF_D_MASK) >> XF_PERF0_F_PERF_D_SHIFT)
+
+#define XF_PERF0_F_TOTAL_SIZE	20
+#define XF_PERF0_F_UNUSED_SIZE	12
+
+#define XF_PERF0_F(perf_a, perf_b, perf_c, perf_d) \
+    ((((unsigned long)(perf_a)) << XF_PERF0_F_PERF_A_SHIFT) | \
+        (((unsigned long)(perf_b)) << XF_PERF0_F_PERF_B_SHIFT) | \
+        (((unsigned long)(perf_c)) << XF_PERF0_F_PERF_C_SHIFT) | \
+        (((unsigned long)(perf_d)) << XF_PERF0_F_PERF_D_SHIFT))
+
+#define XF_PERF1_F_PERF_TARGET_SIZE	7
+#define XF_PERF1_F_PERF_TARGET_SHIFT	0
+#define XF_PERF1_F_PERF_TARGET_MASK	0x0000007f
+#define XF_PERF1_F_GET_PERF_TARGET(xf_perf1_f) \
+    ((((unsigned long)(xf_perf1_f)) & XF_PERF1_F_PERF_TARGET_MASK) >> XF_PERF1_F_PERF_TARGET_SHIFT)
+
+#define XF_PERF1_F_TOTAL_SIZE	7
+#define XF_PERF1_F_UNUSED_SIZE	25
+
+#define XF_PERF1_F(perf_target) \
+    ((((unsigned long)(perf_target)) << XF_PERF1_F_PERF_TARGET_SHIFT))
+
+#define XF_MATERIAL0_F_ALPHA_SIZE	8
+#define XF_MATERIAL0_F_ALPHA_SHIFT	0
+#define XF_MATERIAL0_F_ALPHA_MASK	0x000000ff
+#define XF_MATERIAL0_F_GET_ALPHA(xf_material0_f) \
+	((((unsigned long)(xf_material0_f)) & XF_MATERIAL0_F_ALPHA_MASK) >> XF_MATERIAL0_F_ALPHA_SHIFT)
+#define XF_MATERIAL0_F_SET_ALPHA(xf_material0_f, alpha) { \
+	xf_material0_f = (((unsigned long)(xf_material0_f)) & ~XF_MATERIAL0_F_ALPHA_MASK) | (((unsigned long)(alpha)) << XF_MATERIAL0_F_ALPHA_SHIFT);\
+}
+#define XF_MATERIAL0_F_BLUE_SIZE	8
+#define XF_MATERIAL0_F_BLUE_SHIFT	8
+#define XF_MATERIAL0_F_BLUE_MASK	0x0000ff00
+#define XF_MATERIAL0_F_GET_BLUE(xf_material0_f) \
+	((((unsigned long)(xf_material0_f)) & XF_MATERIAL0_F_BLUE_MASK) >> XF_MATERIAL0_F_BLUE_SHIFT)
+#define XF_MATERIAL0_F_SET_BLUE(xf_material0_f, blue) { \
+	xf_material0_f = (((unsigned long)(xf_material0_f)) & ~XF_MATERIAL0_F_BLUE_MASK) | (((unsigned long)(blue)) << XF_MATERIAL0_F_BLUE_SHIFT);\
+
+#define XF_MATERIAL0_F_GREEN_SIZE	8
+#define XF_MATERIAL0_F_GREEN_SHIFT	16
+#define XF_MATERIAL0_F_GREEN_MASK	0x00ff0000
+#define XF_MATERIAL0_F_GET_GREEN(xf_material0_f) \
+	((((unsigned long)(xf_material0_f)) & XF_MATERIAL0_F_GREEN_MASK) >> XF_MATERIAL0_F_GREEN_SHIFT)
+#define XF_MATERIAL0_F_SET_GREEN(xf_material0_f, green) { \
+	xf_material0_f = (((unsigned long)(xf_material0_f)) & ~XF_MATERIAL0_F_GREEN_MASK) | (((unsigned long)(green)) << XF_MATERIAL0_F_GREEN_SHIFT);\
+}
+
+#define XF_MATERIAL0_F_RED_SIZE	8
+#define XF_MATERIAL0_F_RED_SHIFT	24
+#define XF_MATERIAL0_F_RED_MASK	0xff000000
+#define XF_MATERIAL0_F_GET_RED(xf_material0_f) \
+	((((unsigned long)(xf_material0_f)) & XF_MATERIAL0_F_RED_MASK) >> XF_MATERIAL0_F_RED_SHIFT)
+#define XF_MATERIAL0_F_SET_RED(xf_material0_f, red) { \
+	xf_material0_f = (((unsigned long)(xf_material0_f)) & ~XF_MATERIAL0_F_RED_MASK) | (((unsigned long)(red)) << XF_MATERIAL0_F_RED_SHIFT);\
+}
+#define XF_MATERIAL0_F_TOTAL_SIZE	32
+#define XF_MATERIAL0_F(alpha, blue, green, red) \
+	((((unsigned long)(alpha)) << XF_MATERIAL0_F_ALPHA_SHIFT) | \
+	 (((unsigned long)(blue)) << XF_MATERIAL0_F_BLUE_SHIFT) | \
+	 (((unsigned long)(green)) << XF_MATERIAL0_F_GREEN_SHIFT) | \
+	 (((unsigned long)(red)) << XF_MATERIAL0_F_RED_SHIFT))
+
+#define XF_MATERIAL1_F_ALPHA_SIZE	8
+#define XF_MATERIAL1_F_ALPHA_SHIFT	0
+#define XF_MATERIAL1_F_ALPHA_MASK	0x000000ff
+#define XF_MATERIAL1_F_GET_ALPHA(xf_material1_f) \
+	((((unsigned long)(xf_material1_f)) & XF_MATERIAL1_F_ALPHA_MASK) >> XF_MATERIAL1_F_ALPHA_SHIFT)
+#define XF_MATERIAL1_F_SET_ALPHA(xf_material1_f, alpha) { \
+	xf_material1_f = (((unsigned long)(xf_material1_f)) & ~XF_MATERIAL1_F_ALPHA_MASK) | (((unsigned long)(alpha)) << XF_MATERIAL1_F_ALPHA_SHIFT);\
+}
+#define XF_MATERIAL1_F_BLUE_SIZE	8
+#define XF_MATERIAL1_F_BLUE_SHIFT	8
+#define XF_MATERIAL1_F_BLUE_MASK	0x0000ff00
+#define XF_MATERIAL1_F_GET_BLUE(xf_material1_f) \
+	((((unsigned long)(xf_material1_f)) & XF_MATERIAL1_F_BLUE_MASK) >> XF_MATERIAL1_F_BLUE_SHIFT)
+#define XF_MATERIAL1_F_SET_BLUE(xf_material1_f, blue) { \
+	xf_material1_f = (((unsigned long)(xf_material1_f)) & ~XF_MATERIAL1_F_BLUE_MASK) | (((unsigned long)(blue)) << XF_MATERIAL1_F_BLUE_SHIFT);\
+}
+#define XF_MATERIAL1_F_GREEN_SIZE	8
+#define XF_MATERIAL1_F_GREEN_SHIFT	16
+#define XF_MATERIAL1_F_GREEN_MASK	0x00ff0000
+#define XF_MATERIAL1_F_GET_GREEN(xf_material1_f) \
+	((((unsigned long)(xf_material1_f)) & XF_MATERIAL1_F_GREEN_MASK) >> XF_MATERIAL1_F_GREEN_SHIFT)
+#define XF_MATERIAL1_F_SET_GREEN(xf_material1_f, green) { \
+	xf_material1_f = (((unsigned long)(xf_material1_f)) & ~XF_MATERIAL1_F_GREEN_MASK) | (((unsigned long)(green)) << XF_MATERIAL1_F_GREEN_SHIFT);\
+}
+#define XF_MATERIAL1_F_RED_SIZE	8
+#define XF_MATERIAL1_F_RED_SHIFT	24
+#define XF_MATERIAL1_F_RED_MASK	0xff000000
+#define XF_MATERIAL1_F_GET_RED(xf_material1_f) \
+	((((unsigned long)(xf_material1_f)) & XF_MATERIAL1_F_RED_MASK) >> XF_MATERIAL1_F_RED_SHIFT)
+#define XF_MATERIAL1_F_SET_RED(xf_material1_f, red) { \
+	xf_material1_f = (((unsigned long)(xf_material1_f)) & ~XF_MATERIAL1_F_RED_MASK) | (((unsigned long)(red)) << XF_MATERIAL1_F_RED_SHIFT);\
+}
+#define XF_MATERIAL1_F_TOTAL_SIZE	32
+#define XF_MATERIAL1_F(alpha, blue, green, red) \
+	((((unsigned long)(alpha)) << XF_MATERIAL1_F_ALPHA_SHIFT) | \
+	 (((unsigned long)(blue)) << XF_MATERIAL1_F_BLUE_SHIFT) | \
+	 (((unsigned long)(green)) << XF_MATERIAL1_F_GREEN_SHIFT) | \
+	 (((unsigned long)(red)) << XF_MATERIAL1_F_RED_SHIFT))
+
+#define XF_COLOR0CNTRL_F_MATERIAL_SRC_SIZE	1
+#define XF_COLOR0CNTRL_F_MATERIAL_SRC_SHIFT	0
+#define XF_COLOR0CNTRL_F_MATERIAL_SRC_MASK	0x00000001
+#define XF_COLOR0CNTRL_F_GET_MATERIAL_SRC(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_MATERIAL_SRC_MASK) >> XF_COLOR0CNTRL_F_MATERIAL_SRC_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_MATERIAL_SRC(xf_color0cntrl_f, material_src) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_MATERIAL_SRC_MASK) | (((unsigned long)(material_src)) << XF_COLOR0CNTRL_F_MATERIAL_SRC_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_LIGHTFUNC_SIZE	1
+#define XF_COLOR0CNTRL_F_LIGHTFUNC_SHIFT	1
+#define XF_COLOR0CNTRL_F_LIGHTFUNC_MASK	0x00000002
+#define XF_COLOR0CNTRL_F_GET_LIGHTFUNC(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_LIGHTFUNC_MASK) >> XF_COLOR0CNTRL_F_LIGHTFUNC_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_LIGHTFUNC(xf_color0cntrl_f, lightfunc) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_LIGHTFUNC_MASK) | (((unsigned long)(lightfunc)) << XF_COLOR0CNTRL_F_LIGHTFUNC_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_AMBIENT_SRC_SIZE	1
+#define XF_COLOR0CNTRL_F_AMBIENT_SRC_SHIFT	6
+#define XF_COLOR0CNTRL_F_AMBIENT_SRC_MASK	0x00000040
+#define XF_COLOR0CNTRL_F_GET_AMBIENT_SRC(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_AMBIENT_SRC_MASK) >> XF_COLOR0CNTRL_F_AMBIENT_SRC_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_AMBIENT_SRC(xf_color0cntrl_f, ambient_src) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_AMBIENT_SRC_MASK) | (((unsigned long)(ambient_src)) << XF_COLOR0CNTRL_F_AMBIENT_SRC_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_DIFFUSEATTEN_SIZE	2
+#define XF_COLOR0CNTRL_F_DIFFUSEATTEN_SHIFT	7
+#define XF_COLOR0CNTRL_F_DIFFUSEATTEN_MASK	0x00000180
+#define XF_COLOR0CNTRL_F_GET_DIFFUSEATTEN(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_DIFFUSEATTEN_MASK) >> XF_COLOR0CNTRL_F_DIFFUSEATTEN_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_DIFFUSEATTEN(xf_color0cntrl_f, diffuseatten) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_DIFFUSEATTEN_MASK) | (((unsigned long)(diffuseatten)) << XF_COLOR0CNTRL_F_DIFFUSEATTEN_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_LIGHT0_SIZE	1
+#define XF_COLOR0CNTRL_F_LIGHT0_SHIFT	2
+#define XF_COLOR0CNTRL_F_LIGHT0_MASK	0x00000004
+#define XF_COLOR0CNTRL_F_GET_LIGHT0(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_LIGHT0_MASK) >> XF_COLOR0CNTRL_F_LIGHT0_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_LIGHT0(xf_color0cntrl_f, light0) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_LIGHT0_MASK) | (((unsigned long)(light0)) << XF_COLOR0CNTRL_F_LIGHT0_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_LIGHT1_SIZE	1
+#define XF_COLOR0CNTRL_F_LIGHT1_SHIFT	3
+#define XF_COLOR0CNTRL_F_LIGHT1_MASK	0x00000008
+#define XF_COLOR0CNTRL_F_GET_LIGHT1(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_LIGHT1_MASK) >> XF_COLOR0CNTRL_F_LIGHT1_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_LIGHT1(xf_color0cntrl_f, light1) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_LIGHT1_MASK) | (((unsigned long)(light1)) << XF_COLOR0CNTRL_F_LIGHT1_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_LIGHT2_SIZE	1
+#define XF_COLOR0CNTRL_F_LIGHT2_SHIFT	4
+#define XF_COLOR0CNTRL_F_LIGHT2_MASK	0x00000010
+#define XF_COLOR0CNTRL_F_GET_LIGHT2(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_LIGHT2_MASK) >> XF_COLOR0CNTRL_F_LIGHT2_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_LIGHT2(xf_color0cntrl_f, light2) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_LIGHT2_MASK) | (((unsigned long)(light2)) << XF_COLOR0CNTRL_F_LIGHT2_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_LIGHT3_SIZE	1
+#define XF_COLOR0CNTRL_F_LIGHT3_SHIFT	5
+#define XF_COLOR0CNTRL_F_LIGHT3_MASK	0x00000020
+#define XF_COLOR0CNTRL_F_GET_LIGHT3(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_LIGHT3_MASK) >> XF_COLOR0CNTRL_F_LIGHT3_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_LIGHT3(xf_color0cntrl_f, light3) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_LIGHT3_MASK) | (((unsigned long)(light3)) << XF_COLOR0CNTRL_F_LIGHT3_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_LIGHT4_SIZE	1
+#define XF_COLOR0CNTRL_F_LIGHT4_SHIFT	11
+#define XF_COLOR0CNTRL_F_LIGHT4_MASK	0x00000800
+#define XF_COLOR0CNTRL_F_GET_LIGHT4(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_LIGHT4_MASK) >> XF_COLOR0CNTRL_F_LIGHT4_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_LIGHT4(xf_color0cntrl_f, light4) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_LIGHT4_MASK) | (((unsigned long)(light4)) << XF_COLOR0CNTRL_F_LIGHT4_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_LIGHT5_SIZE	1
+#define XF_COLOR0CNTRL_F_LIGHT5_SHIFT	12
+#define XF_COLOR0CNTRL_F_LIGHT5_MASK	0x00001000
+#define XF_COLOR0CNTRL_F_GET_LIGHT5(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_LIGHT5_MASK) >> XF_COLOR0CNTRL_F_LIGHT5_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_LIGHT5(xf_color0cntrl_f, light5) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_LIGHT5_MASK) | (((unsigned long)(light5)) << XF_COLOR0CNTRL_F_LIGHT5_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_LIGHT6_SIZE	1
+#define XF_COLOR0CNTRL_F_LIGHT6_SHIFT	13
+#define XF_COLOR0CNTRL_F_LIGHT6_MASK	0x00002000
+#define XF_COLOR0CNTRL_F_GET_LIGHT6(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_LIGHT6_MASK) >> XF_COLOR0CNTRL_F_LIGHT6_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_LIGHT6(xf_color0cntrl_f, light6) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_LIGHT6_MASK) | (((unsigned long)(light6)) << XF_COLOR0CNTRL_F_LIGHT6_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_LIGHT7_SIZE	1
+#define XF_COLOR0CNTRL_F_LIGHT7_SHIFT	14
+#define XF_COLOR0CNTRL_F_LIGHT7_MASK	0x00004000
+#define XF_COLOR0CNTRL_F_GET_LIGHT7(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_LIGHT7_MASK) >> XF_COLOR0CNTRL_F_LIGHT7_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_LIGHT7(xf_color0cntrl_f, light7) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_LIGHT7_MASK) | (((unsigned long)(light7)) << XF_COLOR0CNTRL_F_LIGHT7_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_ATTENENABLE_SIZE	1
+#define XF_COLOR0CNTRL_F_ATTENENABLE_SHIFT	9
+#define XF_COLOR0CNTRL_F_ATTENENABLE_MASK	0x00000200
+#define XF_COLOR0CNTRL_F_GET_ATTENENABLE(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_ATTENENABLE_MASK) >> XF_COLOR0CNTRL_F_ATTENENABLE_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_ATTENENABLE(xf_color0cntrl_f, attenenable) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_ATTENENABLE_MASK) | (((unsigned long)(attenenable)) << XF_COLOR0CNTRL_F_ATTENENABLE_SHIFT);\
+}
+
+#define XF_COLOR0CNTRL_F_ATTENSELECT_SIZE	1
+#define XF_COLOR0CNTRL_F_ATTENSELECT_SHIFT	10
+#define XF_COLOR0CNTRL_F_ATTENSELECT_MASK	0x00000400
+#define XF_COLOR0CNTRL_F_GET_ATTENSELECT(xf_color0cntrl_f) \
+	((((unsigned long)(xf_color0cntrl_f)) & XF_COLOR0CNTRL_F_ATTENSELECT_MASK) >> XF_COLOR0CNTRL_F_ATTENSELECT_SHIFT)
+#define XF_COLOR0CNTRL_F_SET_ATTENSELECT(xf_color0cntrl_f, attenselect) { \
+	xf_color0cntrl_f = (((unsigned long)(xf_color0cntrl_f)) & ~XF_COLOR0CNTRL_F_ATTENSELECT_MASK) | (((unsigned long)(attenselect)) << XF_COLOR0CNTRL_F_ATTENSELECT_SHIFT);\
+}
+
+#define SC_XF_AMBIENT0_F_SET_ALPHA(line, xf_ambient0_f,alpha) \
+	FAST_GPFLAGSET(line, xf_ambient0_f,alpha,XF_AMBIENT0_F_ALPHA)
+
+#define SC_XF_AMBIENT0_F_SET_BLUE(line, xf_ambient0_f,blue) \
+	FAST_GPFLAGSET(line, xf_ambient0_f,blue,XF_AMBIENT0_F_BLUE)
+
+#define SC_XF_AMBIENT0_F_SET_GREEN(line, xf_ambient0_f,green) \
+	FAST_GPFLAGSET(line, xf_ambient0_f,green,XF_AMBIENT0_F_GREEN)
+
+#define SC_XF_AMBIENT0_F_SET_RED(line, xf_ambient0_f,red) \
+	FAST_GPFLAGSET(line, xf_ambient0_f,red,XF_AMBIENT0_F_RED)
+
+#define SC_XF_AMBIENT1_F_SET_ALPHA(line, xf_ambient1_f,alpha) \
+	FAST_GPFLAGSET(line, xf_ambient1_f,alpha,XF_AMBIENT1_F_ALPHA)
+
+#define SC_XF_AMBIENT1_F_SET_BLUE(line, xf_ambient1_f,blue) \
+	FAST_GPFLAGSET(line, xf_ambient1_f,blue,XF_AMBIENT1_F_BLUE)
+
+#define SC_XF_AMBIENT1_F_SET_GREEN(line, xf_ambient1_f,green) \
+	FAST_GPFLAGSET(line, xf_ambient1_f,green,XF_AMBIENT1_F_GREEN)
+
+#define SC_XF_AMBIENT1_F_SET_RED(line, xf_ambient1_f,red) \
+	FAST_GPFLAGSET(line, xf_ambient1_f,red,XF_AMBIENT1_F_RED)
+
+#define SC_XF_MATERIAL0_F_SET_ALPHA(line, xf_material0_f,alpha) \
+	FAST_GPFLAGSET(line, xf_material0_f,alpha,XF_MATERIAL0_F_ALPHA)
+
+#define SC_XF_MATERIAL0_F_SET_BLUE(line, xf_material0_f,blue) \
+	FAST_GPFLAGSET(line, xf_material0_f,blue,XF_MATERIAL0_F_BLUE)
+
+#define SC_XF_MATERIAL0_F_SET_GREEN(line, xf_material0_f,green) \
+	FAST_GPFLAGSET(line, xf_material0_f,green,XF_MATERIAL0_F_GREEN)
+
+#define SC_XF_MATERIAL0_F_SET_RED(line, xf_material0_f,red) \
+	FAST_GPFLAGSET(line, xf_material0_f,red,XF_MATERIAL0_F_RED)
+
+#define SC_XF_MATERIAL1_F_SET_ALPHA(line, xf_material1_f,alpha) \
+	FAST_GPFLAGSET(line, xf_material1_f,alpha,XF_MATERIAL1_F_ALPHA)
+
+#define SC_XF_MATERIAL1_F_SET_BLUE(line, xf_material1_f,blue) \
+	FAST_GPFLAGSET(line, xf_material1_f,blue,XF_MATERIAL1_F_BLUE)
+
+#define SC_XF_MATERIAL1_F_SET_GREEN(line, xf_material1_f,green) \
+	FAST_GPFLAGSET(line, xf_material1_f,green,XF_MATERIAL1_F_GREEN)
+
+#define SC_XF_MATERIAL1_F_SET_RED(line, xf_material1_f,red) \
+	FAST_GPFLAGSET(line, xf_material1_f,red,XF_MATERIAL1_F_RED)
+
+#define SC_XF_MATRIXINDEX0_F_SET_GEOM(line, xf_matrixindex0_f,geom) \
+	FAST_GPFLAGSET(line, xf_matrixindex0_f,geom,XF_MATRIXINDEX0_F_GEOM)
+
+#define SC_XF_MATRIXINDEX0_F_SET_TEX0(line, xf_matrixindex0_f,tex0) \
+	FAST_GPFLAGSET(line, xf_matrixindex0_f,tex0,XF_MATRIXINDEX0_F_TEX0)
+
+#define SC_XF_MATRIXINDEX0_F_SET_TEX1(line, xf_matrixindex0_f,tex1) \
+	FAST_GPFLAGSET(line, xf_matrixindex0_f,tex1,XF_MATRIXINDEX0_F_TEX1)
+
+#define SC_XF_MATRIXINDEX0_F_SET_TEX2(line, xf_matrixindex0_f,tex2) \
+	FAST_GPFLAGSET(line, xf_matrixindex0_f,tex2,XF_MATRIXINDEX0_F_TEX2)
+
+#define SC_XF_MATRIXINDEX0_F_SET_TEX3(line, xf_matrixindex0_f,tex3) \
+	FAST_GPFLAGSET(line, xf_matrixindex0_f,tex3,XF_MATRIXINDEX0_F_TEX3)
+
+#define SC_XF_MATRIXINDEX1_F_SET_TEX4(line, xf_matrixindex1_f,tex4) \
+	FAST_GPFLAGSET(line, xf_matrixindex1_f,tex4,XF_MATRIXINDEX1_F_TEX4)
+
+#define SC_XF_MATRIXINDEX1_F_SET_TEX5(line, xf_matrixindex1_f,tex5) \
+	FAST_GPFLAGSET(line, xf_matrixindex1_f,tex5,XF_MATRIXINDEX1_F_TEX5)
+
+#define SC_XF_MATRIXINDEX1_F_SET_TEX6(line, xf_matrixindex1_f,tex6) \
+	FAST_GPFLAGSET(line, xf_matrixindex1_f,tex6,XF_MATRIXINDEX1_F_TEX6)
+
+#define SC_XF_MATRIXINDEX1_F_SET_TEX7(line, xf_matrixindex1_f,tex7) \
+	FAST_GPFLAGSET(line, xf_matrixindex1_f,tex7,XF_MATRIXINDEX1_F_TEX7)
+
+#define SC_XF_INVERTEXSPEC_F_SET_HOST_COLORS(line, xf_invertexspec_f,host_colors) \
+	FAST_GPFLAGSET(line, xf_invertexspec_f,host_colors,XF_INVERTEXSPEC_F_HOST_COLORS)
+
+#define SC_XF_INVERTEXSPEC_F_SET_HOST_NORMAL(line, xf_invertexspec_f,host_normal) \
+	FAST_GPFLAGSET(line, xf_invertexspec_f,host_normal,XF_INVERTEXSPEC_F_HOST_NORMAL)
+
+#define SC_XF_INVERTEXSPEC_F_SET_HOST_TEXTURES(line, xf_invertexspec_f,host_textures) \
+	FAST_GPFLAGSET(line, xf_invertexspec_f,host_textures,XF_INVERTEXSPEC_F_HOST_TEXTURES)
+
+#define SC_XF_NUMCOLORS_F_SET_GEN_NUMCOLORS(line, xf_numcolors_f,gen_numcolors) \
+	FAST_GPFLAGSET(line, xf_numcolors_f,gen_numcolors,XF_NUMCOLORS_F_GEN_NUMCOLORS)
+
+#define SC_XF_COLOR0CNTRL_F_SET_MATERIAL_SRC(line, xf_color0cntrl_f,material_src) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,material_src,XF_COLOR0CNTRL_F_MATERIAL_SRC)
+
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHTFUNC(line, xf_color0cntrl_f,lightfunc) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,lightfunc,XF_COLOR0CNTRL_F_LIGHTFUNC)
+
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHT0(line, xf_color0cntrl_f,light0) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,light0,XF_COLOR0CNTRL_F_LIGHT0)
+
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHT1(line, xf_color0cntrl_f,light1) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,light1,XF_COLOR0CNTRL_F_LIGHT1)
+
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHT2(line, xf_color0cntrl_f,light2) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,light2,XF_COLOR0CNTRL_F_LIGHT2)
+
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHT3(line, xf_color0cntrl_f,light3) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,light3,XF_COLOR0CNTRL_F_LIGHT3)
+
+#define SC_XF_COLOR0CNTRL_F_SET_AMBIENT_SRC(line, xf_color0cntrl_f,ambient_src) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,ambient_src,XF_COLOR0CNTRL_F_AMBIENT_SRC)
+
+#define SC_XF_COLOR0CNTRL_F_SET_DIFFUSEATTEN(line, xf_color0cntrl_f,diffuseatten) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,diffuseatten,XF_COLOR0CNTRL_F_DIFFUSEATTEN)
+
+#define SC_XF_COLOR0CNTRL_F_SET_ATTENENABLE(line, xf_color0cntrl_f,attenenable) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,attenenable,XF_COLOR0CNTRL_F_ATTENENABLE)
+
+#define SC_XF_COLOR0CNTRL_F_SET_ATTENSELECT(line, xf_color0cntrl_f,attenselect) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,attenselect,XF_COLOR0CNTRL_F_ATTENSELECT)
+
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHT4(line, xf_color0cntrl_f,light4) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,light4,XF_COLOR0CNTRL_F_LIGHT4)
+
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHT5(line, xf_color0cntrl_f,light5) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,light5,XF_COLOR0CNTRL_F_LIGHT5)
+
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHT6(line, xf_color0cntrl_f,light6) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,light6,XF_COLOR0CNTRL_F_LIGHT6)
+
+#define SC_XF_COLOR0CNTRL_F_SET_LIGHT7(line, xf_color0cntrl_f,light7) \
+	FAST_GPFLAGSET(line, xf_color0cntrl_f,light7,XF_COLOR0CNTRL_F_LIGHT7)
+
+#define SC_XF_COLOR1CNTRL_F_SET_MATERIAL_SRC(line, xf_color1cntrl_f,material_src) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,material_src,XF_COLOR1CNTRL_F_MATERIAL_SRC)
+
+#define SC_XF_COLOR1CNTRL_F_SET_LIGHTFUNC(line, xf_color1cntrl_f,lightfunc) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,lightfunc,XF_COLOR1CNTRL_F_LIGHTFUNC)
+
+#define SC_XF_COLOR1CNTRL_F_SET_LIGHT0(line, xf_color1cntrl_f,light0) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,light0,XF_COLOR1CNTRL_F_LIGHT0)
+
+#define SC_XF_COLOR1CNTRL_F_SET_LIGHT1(line, xf_color1cntrl_f,light1) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,light1,XF_COLOR1CNTRL_F_LIGHT1)
+
+#define SC_XF_COLOR1CNTRL_F_SET_LIGHT2(line, xf_color1cntrl_f,light2) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,light2,XF_COLOR1CNTRL_F_LIGHT2)
+
+#define SC_XF_COLOR1CNTRL_F_SET_LIGHT3(line, xf_color1cntrl_f,light3) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,light3,XF_COLOR1CNTRL_F_LIGHT3)
+
+#define SC_XF_COLOR1CNTRL_F_SET_AMBIENT_SRC(line, xf_color1cntrl_f,ambient_src) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,ambient_src,XF_COLOR1CNTRL_F_AMBIENT_SRC)
+
+#define SC_XF_COLOR1CNTRL_F_SET_DIFFUSEATTEN(line, xf_color1cntrl_f,diffuseatten) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,diffuseatten,XF_COLOR1CNTRL_F_DIFFUSEATTEN)
+
+#define SC_XF_COLOR1CNTRL_F_SET_ATTENENABLE(line, xf_color1cntrl_f,attenenable) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,attenenable,XF_COLOR1CNTRL_F_ATTENENABLE)
+
+#define SC_XF_COLOR1CNTRL_F_SET_ATTENSELECT(line, xf_color1cntrl_f,attenselect) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,attenselect,XF_COLOR1CNTRL_F_ATTENSELECT)
+
+#define SC_XF_COLOR1CNTRL_F_SET_LIGHT4(line, xf_color1cntrl_f,light4) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,light4,XF_COLOR1CNTRL_F_LIGHT4)
+
+#define SC_XF_COLOR1CNTRL_F_SET_LIGHT5(line, xf_color1cntrl_f,light5) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,light5,XF_COLOR1CNTRL_F_LIGHT5)
+
+#define SC_XF_COLOR1CNTRL_F_SET_LIGHT6(line, xf_color1cntrl_f,light6) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,light6,XF_COLOR1CNTRL_F_LIGHT6)
+
+#define SC_XF_COLOR1CNTRL_F_SET_LIGHT7(line, xf_color1cntrl_f,light7) \
+	FAST_GPFLAGSET(line, xf_color1cntrl_f,light7,XF_COLOR1CNTRL_F_LIGHT7)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_MATERIAL_SRC(line, xf_alpha0cntrl_f,material_src) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,material_src,XF_ALPHA0CNTRL_F_MATERIAL_SRC)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_LIGHTFUNC(line, xf_alpha0cntrl_f,lightfunc) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,lightfunc,XF_ALPHA0CNTRL_F_LIGHTFUNC)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_LIGHT0(line, xf_alpha0cntrl_f,light0) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,light0,XF_ALPHA0CNTRL_F_LIGHT0)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_LIGHT1(line, xf_alpha0cntrl_f,light1) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,light1,XF_ALPHA0CNTRL_F_LIGHT1)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_LIGHT2(line, xf_alpha0cntrl_f,light2) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,light2,XF_ALPHA0CNTRL_F_LIGHT2)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_LIGHT3(line, xf_alpha0cntrl_f,light3) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,light3,XF_ALPHA0CNTRL_F_LIGHT3)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_AMBIENT_SRC(line, xf_alpha0cntrl_f,ambient_src) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,ambient_src,XF_ALPHA0CNTRL_F_AMBIENT_SRC)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_DIFFUSEATTEN(line, xf_alpha0cntrl_f,diffuseatten) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,diffuseatten,XF_ALPHA0CNTRL_F_DIFFUSEATTEN)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_ATTENENABLE(line, xf_alpha0cntrl_f,attenenable) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,attenenable,XF_ALPHA0CNTRL_F_ATTENENABLE)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_ATTENSELECT(line, xf_alpha0cntrl_f,attenselect) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,attenselect,XF_ALPHA0CNTRL_F_ATTENSELECT)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_LIGHT4(line, xf_alpha0cntrl_f,light4) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,light4,XF_ALPHA0CNTRL_F_LIGHT4)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_LIGHT5(line, xf_alpha0cntrl_f,light5) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,light5,XF_ALPHA0CNTRL_F_LIGHT5)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_LIGHT6(line, xf_alpha0cntrl_f,light6) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,light6,XF_ALPHA0CNTRL_F_LIGHT6)
+
+#define SC_XF_ALPHA0CNTRL_F_SET_LIGHT7(line, xf_alpha0cntrl_f,light7) \
+	FAST_GPFLAGSET(line, xf_alpha0cntrl_f,light7,XF_ALPHA0CNTRL_F_LIGHT7)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_MATERIAL_SRC(line, xf_alpha1cntrl_f,material_src) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,material_src,XF_ALPHA1CNTRL_F_MATERIAL_SRC)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_LIGHTFUNC(line, xf_alpha1cntrl_f,lightfunc) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,lightfunc,XF_ALPHA1CNTRL_F_LIGHTFUNC)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_LIGHT0(line, xf_alpha1cntrl_f,light0) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,light0,XF_ALPHA1CNTRL_F_LIGHT0)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_LIGHT1(line, xf_alpha1cntrl_f,light1) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,light1,XF_ALPHA1CNTRL_F_LIGHT1)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_LIGHT2(line, xf_alpha1cntrl_f,light2) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,light2,XF_ALPHA1CNTRL_F_LIGHT2)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_LIGHT3(line, xf_alpha1cntrl_f,light3) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,light3,XF_ALPHA1CNTRL_F_LIGHT3)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_AMBIENT_SRC(line, xf_alpha1cntrl_f,ambient_src) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,ambient_src,XF_ALPHA1CNTRL_F_AMBIENT_SRC)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_DIFFUSEATTEN(line, xf_alpha1cntrl_f,diffuseatten) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,diffuseatten,XF_ALPHA1CNTRL_F_DIFFUSEATTEN)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_ATTENENABLE(line, xf_alpha1cntrl_f,attenenable) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,attenenable,XF_ALPHA1CNTRL_F_ATTENENABLE)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_ATTENSELECT(line, xf_alpha1cntrl_f,attenselect) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,attenselect,XF_ALPHA1CNTRL_F_ATTENSELECT)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_LIGHT4(line, xf_alpha1cntrl_f,light4) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,light4,XF_ALPHA1CNTRL_F_LIGHT4)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_LIGHT5(line, xf_alpha1cntrl_f,light5) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,light5,XF_ALPHA1CNTRL_F_LIGHT5)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_LIGHT6(line, xf_alpha1cntrl_f,light6) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,light6,XF_ALPHA1CNTRL_F_LIGHT6)
+
+#define SC_XF_ALPHA1CNTRL_F_SET_LIGHT7(line, xf_alpha1cntrl_f,light7) \
+	FAST_GPFLAGSET(line, xf_alpha1cntrl_f,light7,XF_ALPHA1CNTRL_F_LIGHT7)
+
+#define SC_XF_TEX_SET_RESERVED0(line, xf_tex,reserved0) \
+	FAST_GPFLAGSET(line, xf_tex,reserved0,XF_TEX_RESERVED0)
+
+#define SC_XF_TEX_SET_PROJECTION(line, xf_tex,projection) \
+	FAST_GPFLAGSET(line, xf_tex,projection,XF_TEX_PROJECTION)
+
+#define SC_XF_TEX_SET_INPUT_FORM(line, xf_tex,input_form) \
+	FAST_GPFLAGSET(line, xf_tex,input_form,XF_TEX_INPUT_FORM)
+
+#define SC_XF_TEX_SET_RESERVED1(line, xf_tex,reserved1) \
+	FAST_GPFLAGSET(line, xf_tex,reserved1,XF_TEX_RESERVED1)
+
+#define SC_XF_TEX_SET_TEXGEN_TYPE(line, xf_tex,texgen_type) \
+	FAST_GPFLAGSET(line, xf_tex,texgen_type,XF_TEX_TEXGEN_TYPE)
+
+#define SC_XF_TEX_SET_SOURCE_ROW(line, xf_tex,source_row) \
+	FAST_GPFLAGSET(line, xf_tex,source_row,XF_TEX_SOURCE_ROW)
+
+#define SC_XF_TEX_SET_BUMP_MAP_SOURCE(line, xf_tex,bump_map_source) \
+	FAST_GPFLAGSET(line, xf_tex,bump_map_source,XF_TEX_BUMP_MAP_SOURCE)
+
+#define SC_XF_TEX_SET_BUMP_MAP_LIGHT(line, xf_tex,bump_map_light) \
+	FAST_GPFLAGSET(line, xf_tex,bump_map_light,XF_TEX_BUMP_MAP_LIGHT)
+
+#define SC_XF_PERF0_F_SET_PERF_A(line, xf_perf0_f,perf_a) \
+	FAST_GPFLAGSET(line, xf_perf0_f,perf_a,XF_PERF0_F_PERF_A)
+
+#define SC_XF_PERF0_F_SET_PERF_B(line, xf_perf0_f,perf_b) \
+	FAST_GPFLAGSET(line, xf_perf0_f,perf_b,XF_PERF0_F_PERF_B)
+
+#define SC_XF_PERF0_F_SET_PERF_C(line, xf_perf0_f,perf_c) \
+	FAST_GPFLAGSET(line, xf_perf0_f,perf_c,XF_PERF0_F_PERF_C)
+
+#define SC_XF_PERF0_F_SET_PERF_D(line, xf_perf0_f,perf_d) \
+	FAST_GPFLAGSET(line, xf_perf0_f,perf_d,XF_PERF0_F_PERF_D)
+
+#define SC_XF_PERF1_F_SET_PERF_TARGET(line, xf_perf1_f,perf_target) \
+	FAST_GPFLAGSET(line, xf_perf1_f,perf_target,XF_PERF1_F_PERF_TARGET)
+
+#define SC_XF_ERROR_F_SET_CTEX_BUG_ENABLE(line, xf_error_f,ctex_bug_enable) \
+	FAST_GPFLAGSET(line, xf_error_f,ctex_bug_enable,XF_ERROR_F_CTEX_BUG_ENABLE)
+
+#define SC_XF_ERROR_F_SET_TFAN4_BUG_ENABLE(line, xf_error_f,tfan4_bug_enable) \
+	FAST_GPFLAGSET(line, xf_error_f,tfan4_bug_enable,XF_ERROR_F_TFAN4_BUG_ENABLE)
+
+#define SC_XF_ERROR_F_SET_TFAN16_BUG_ENABLE(line, xf_error_f,tfan16_bug_enable) \
+	FAST_GPFLAGSET(line, xf_error_f,tfan16_bug_enable,XF_ERROR_F_TFAN16_BUG_ENABLE)
+
+#define SC_XF_ERROR_F_SET_DUALTRAN_REG_ENABLE(line, xf_error_f,dualtran_reg_enable) \
+	FAST_GPFLAGSET(line, xf_error_f,dualtran_reg_enable,XF_ERROR_F_DUALTRAN_REG_ENABLE)
+
+#define SC_XF_ERROR_F_SET_BYPASS_BUG_ENABLE(line, xf_error_f,bypass_bug_enable) \
+	FAST_GPFLAGSET(line, xf_error_f,bypass_bug_enable,XF_ERROR_F_BYPASS_BUG_ENABLE)
+
+#define SC_XF_ERROR_F_SET_FAST_MATRIX_ENABLE(line, xf_error_f,fast_matrix_enable) \
+	FAST_GPFLAGSET(line, xf_error_f,fast_matrix_enable,XF_ERROR_F_FAST_MATRIX_ENABLE)
+
+#define SC_XF_DUALTEXTRAN_F_SET_DUALTEXTRAN_ENABLE(line, xf_dualtextran_f,dualtextran_enable) \
+	FAST_GPFLAGSET(line, xf_dualtextran_f,dualtextran_enable,XF_DUALTEXTRAN_F_DUALTEXTRAN_ENABLE)
+
+#define SC_XF_DUALTEX_F_SET_DUALMATRIX_ADRS(line, xf_dualtex_f,dualmatrix_adrs) \
+	FAST_GPFLAGSET(line, xf_dualtex_f,dualmatrix_adrs,XF_DUALTEX_F_DUALMATRIX_ADRS)
+
+#define SC_XF_DUALTEX_F_SET_RESERVED0(line, xf_dualtex_f,reserved0) \
+	FAST_GPFLAGSET(line, xf_dualtex_f,reserved0,XF_DUALTEX_F_RESERVED0)
+
+#define SC_XF_DUALTEX_F_SET_NORMAL_ENABLE(line, xf_dualtex_f,normal_enable) \
+	FAST_GPFLAGSET(line, xf_dualtex_f,normal_enable,XF_DUALTEX_F_NORMAL_ENABLE)
+
+
+#endif // XF_MEM_H
diff --git a/include/revolution/sc.h b/include/revolution/sc.h
index 7a8da096d2..ef8bc2c636 100644
--- a/include/revolution/sc.h
+++ b/include/revolution/sc.h
@@ -77,34 +77,35 @@ typedef enum {
     SC_ITEM_ID_BT_SENSOR_BAR_POSITION,
     SC_ITEM_ID_DVD_CONFIG,
     SC_ITEM_ID_WWW_RESTRICTION,
+    SC_ITEM_ID_MOTION_PLUS_MOVIE,
+    SC_ITEM_ID_TEMPORARY_TITLE_ID,
+
     SC_ITEM_ID_MAX_PLUS1
 } SCItemID;
 
 typedef struct {
-        OSThreadQueue threadQueue;
-        NANDFileInfo nandFileInfo;
-        NANDCommandBlock nandCommandBlock;
-
-        union {
-            u8 nandType;
-            NANDStatus nandStatus;
-        } u;
-
-        u8 nandStep;
-        u8 nandNeedClose;
-        u8 reloadFileCount;
-        SCReloadConfFileCallback reloadCallback;
-        s32 reloadResult;
-        const char* reloadFileName[2];
-        u8* reloadBufp[2];
-        u32 reloadSizeExpected[2];
-        u32 reloadedSize[2];
-        SCFlushCallback flushCallback;
-        u32 flushResult;
-        u32 flushSize;
-} SCControl;
-
+    OSThreadQueue threadQueue;
+    NANDFileInfo nandFileInfo;
+    NANDCommandBlock nandCommandBlock;
 
+    union {
+        u8 nandType;
+        NANDStatus nandStatus;
+    } u;
+
+    u8 nandStep;
+    u8 nandNeedClose;
+    u8 reloadFileCount;
+    SCReloadConfFileCallback reloadCallback;
+    s32 reloadResult;
+    const char* reloadFileName[2];
+    u8* reloadBufp[2];
+    u32 reloadSizeExpected[2];
+    u32 reloadedSize[2];
+    SCFlushCallback flushCallback;
+    u32 flushResult;
+    u32 flushSize;
+} SCControl;
 
 #define SC_LANG_JAPANESE 0u
 #define SC_LANG_ENGLISH 1u
@@ -117,26 +118,35 @@ typedef struct {
 #define SC_LANG_TRAD_CHINESE 8u
 #define SC_LANG_KOREAN 9u
 
-void SCInit(void);
-u32 SCCheckStatus(void);
-s32 SCReloadConfFileAsync(u8* bufp, u32 bufSize, SCReloadConfFileCallback);
-BOOL SCFindByteArrayItem(void* data, u32, SCItemID itemID);
-BOOL SCFindIntegerItem(int* data, SCItemID itemID, u8 type);
-BOOL SCFindU8Item(u8* data, SCItemID itemID);
-BOOL SCFindS8Item(s8* data, SCItemID itemID);
-BOOL SCFindU32Item(u32* data, SCItemID itemID);
+// scapi
 u8 SCGetAspectRatio(void);
 s8 SCGetDisplayOffsetH(void);
+u8 SCGetEuRgb60Mode(void);
 BOOL SCGetIdleMode(SCIdleModeInfo* data);
 u8 SCGetLanguage(void);
 u8 SCGetProgressiveMode(void);
 u8 SCGetScreenSaverMode(void);
 u8 SCGetSoundMode(void);
 u32 SCGetCounterBias(void);
-BOOL SCGetProductAreaString(const char*, int);
+
+// scapi_prdinfo
+BOOL SCGetProductAreaString(char* buf, u32 bufSize);
 s8 SCGetProductArea(void);
 s8 SCGetProductGameRegion(void);
 
+// scsystem
+void SCInit(void);
+BOOL SCFindByteArrayItem(void* data, u32 size, SCItemID id);
+BOOL SCReplaceByteArrayItem(const void* data, u32 size, SCItemID id);
+BOOL SCFindIntegerItem(void* data, SCItemID id, SCType type);
+BOOL SCReplaceIntegerItem(const void* data, SCItemID id, SCType type);
+BOOL SCFindU8Item(u8* data, SCItemID id);
+BOOL SCFindS8Item(s8* data, SCItemID id);
+BOOL SCFindU32Item(u32* data, SCItemID id);
+BOOL SCReplaceU8Item(u8 data, SCItemID id);
+u32 SCCheckStatus(void);
+s32 SCReloadConfFileAsync(u8* bufp, u32 bufSize, SCReloadConfFileCallback callback);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/revolution/vi/vifuncs.h b/include/revolution/vi/vifuncs.h
index f2ed7ef6ca..b3cea5622d 100644
--- a/include/revolution/vi/vifuncs.h
+++ b/include/revolution/vi/vifuncs.h
@@ -30,8 +30,10 @@ u32 VIGetScanMode(void);
 u32 VIGetDTVStatus(void);
 
 void VISetTrapFilter(u8);
-void VIEnableDimming(BOOL);
-void VISetGamma(int);
+BOOL VIEnableDimming(BOOL);
+void VISetGamma(VIGamma);
+void VISetRGBModeImm(void);
+BOOL VIEnableDVDStopMotor(BOOL enable);
 
 #ifdef __cplusplus
 }
diff --git a/include/revolution/vi/vitypes.h b/include/revolution/vi/vitypes.h
index d042cad2c3..728b5404cc 100644
--- a/include/revolution/vi/vitypes.h
+++ b/include/revolution/vi/vitypes.h
@@ -13,8 +13,18 @@
 #define VI_PAL       1
 #define VI_MPAL      2
 #define VI_DEBUG     3
+#define VI_3D        3
 #define VI_DEBUG_PAL 4
 #define VI_EURGB60   5
+#define VI_GCA       6
+#define VI_EXTRA     7
+#define VI_HD720     8
+
+typedef u8 VIBool;
+#define VI_FALSE ((VIBool)0)
+#define VI_TRUE ((VIBool)1)
+#define VI_DISABLE ((VIBool)0)
+#define VI_ENABLE ((VIBool)1)
 
 typedef enum {
     VI_TVMODE_NTSC_INT      = VI_TVMODE(VI_NTSC,        VI_INTERLACE),
@@ -27,9 +37,18 @@ typedef enum {
     VI_TVMODE_EURGB60_PROG  = VI_TVMODE(VI_EURGB60,     VI_PROGRESSIVE),
     VI_TVMODE_MPAL_INT      = VI_TVMODE(VI_MPAL,        VI_INTERLACE),
     VI_TVMODE_MPAL_DS       = VI_TVMODE(VI_MPAL,        VI_NON_INTERLACE),
+    VI_TVMODE_MPAL_PROG     = VI_TVMODE(VI_MPAL,        VI_PROGRESSIVE),
     VI_TVMODE_DEBUG_INT     = VI_TVMODE(VI_DEBUG,       VI_INTERLACE),
     VI_TVMODE_DEBUG_PAL_INT = VI_TVMODE(VI_DEBUG_PAL,   VI_INTERLACE),
-    VI_TVMODE_DEBUG_PAL_DS  = VI_TVMODE(VI_DEBUG_PAL,   VI_NON_INTERLACE)
+    VI_TVMODE_DEBUG_PAL_DS  = VI_TVMODE(VI_DEBUG_PAL,   VI_NON_INTERLACE),
+    VI_TVMODE_NTSC_3D       = VI_TVMODE(VI_NTSC,        VI_3D),
+    VI_TVMODE_GCA_INT       = VI_TVMODE(VI_GCA,         VI_INTERLACE),
+    VI_TVMODE_GCA_PROG      = VI_TVMODE(VI_GCA,         VI_PROGRESSIVE),
+    VI_TVMODE_PAL_PROG      = 6,
+    VI_TVMODE_EXTRA_INT     = VI_TVMODE(VI_EXTRA,       VI_INTERLACE),
+    VI_TVMODE_EXTRA_DS      = VI_TVMODE(VI_EXTRA,       VI_NON_INTERLACE),
+    VI_TVMODE_EXTRA_PROG    = VI_TVMODE(VI_EXTRA,       VI_PROGRESSIVE),
+    VI_TVMODE_HD720_PROG    = VI_TVMODE(VI_HD720,       VI_PROGRESSIVE)
 } VITVMode;
 
 typedef enum {
@@ -37,6 +56,83 @@ typedef enum {
     VI_XFBMODE_DF
 } VIXFBMode;
 
+typedef enum _VITimeToDIM {
+    VI_DM_DEFAULT = 0,
+    VI_DM_10M,
+    VI_DM_15M
+} VITimeToDIM;
+
+typedef enum _VIVideo {
+    VI_VMODE_NTSC = 0,
+    VI_VMODE_MPAL = 1,
+    VI_VMODE_PAL = 2,
+    VI_VMODE_RGB = 3
+} VIVideo;
+
+typedef enum _VIACPType {
+    VI_ACP_OFF = 1,
+    VI_ACP_TYPE1 = 2,
+    VI_ACP_TYPE2 = 3,
+    VI_ACP_TYPE3 = 4
+} VIACPType;
+
+typedef enum _VIGamma {
+    VI_GM_0_1 = 1,
+    VI_GM_0_2,
+    VI_GM_0_3,
+    VI_GM_0_4,
+    VI_GM_0_5,
+    VI_GM_0_6,
+    VI_GM_0_7,
+    VI_GM_0_8,
+    VI_GM_0_9,
+    VI_GM_1_0,
+    VI_GM_1_1,
+    VI_GM_1_2,
+    VI_GM_1_3,
+    VI_GM_1_4,
+    VI_GM_1_5,
+    VI_GM_1_6,
+    VI_GM_1_7,
+    VI_GM_1_8,
+    VI_GM_1_9,
+    VI_GM_2_0,
+    VI_GM_2_1,
+    VI_GM_2_2,
+    VI_GM_2_3,
+    VI_GM_2_4,
+    VI_GM_2_5,
+    VI_GM_2_6,
+    VI_GM_2_7,
+    VI_GM_2_8,
+    VI_GM_2_9,
+    VI_GM_3_0
+} VIGamma;
+
+typedef enum _VITiming {
+    VI_TMG_GAME = 0,
+    VI_TMG_DVD  = 1
+} VITiming;
+
+typedef enum _VIOverDrive {
+	VI_ODV_L1 = 0,
+    VI_ODV_L2 = 1,
+    VI_ODV_L3 = 2,
+    VI_ODV_L4 = 3,
+    VI_ODV_L5 = 4,
+    VI_ODV_L6 = 5
+} VIOverDrive;
+
 typedef void (*VIRetraceCallback)(u32 retraceCount);
 
+typedef struct VIGammaObj {
+    u16 a[6];     
+    u8 yin[7];
+    u16 yout[7];
+} VIGammaObj;
+
+typedef struct VIMacroVisionObj {
+    u8 m[26];
+} VIMacroVisionObj;
+
 #endif
diff --git a/include/revolution/wenc.h b/include/revolution/wenc.h
new file mode 100644
index 0000000000..39b9180977
--- /dev/null
+++ b/include/revolution/wenc.h
@@ -0,0 +1,30 @@
+#ifndef _REVOLUTION_WENC_H_
+#define _REVOLUTION_WENC_H_
+
+#include <revolution/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    WENC_FLAG_USER_INFO = (1 << 0),
+} WENCFlag;
+
+typedef struct WENCInfo {
+    /* 0x00 */ s32 xn;
+    /* 0x04 */ s32 dl;
+    /* 0x08 */ s32 qn;
+    /* 0x0C */ s32 dn;
+    /* 0x10 */ s32 dlh;
+    /* 0x14 */ s32 dlq;
+    /* 0x18 */ u8 padding[8];
+} WENCInfo;
+
+s32 WENCGetEncodeData(WENCInfo* info, u32 flag, const s16* pcmData, s32 samples, u8* adpcmData);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/revolution/wpad.h b/include/revolution/wpad.h
index 59b27ac5f7..2e7456e3e6 100644
--- a/include/revolution/wpad.h
+++ b/include/revolution/wpad.h
@@ -21,23 +21,209 @@ extern "C" {
 #define WPAD_BUTTON_C      0x4000
 #define WPAD_BUTTON_HOME   0x8000
 
-typedef s32 WPADResult;
-typedef s32 WPADChannel;
-typedef u32 WPADDeviceType;
+#define WPAD_MAX_DPD_OBJECTS 4
 
-typedef void WPADExtensionCallback(WPADChannel chan, s32 devType);
+#define WPAD_CHAN0 0
+#define WPAD_CHAN1 1
+#define WPAD_CHAN2 2
+#define WPAD_CHAN3 3
+#define WPAD_CHAN_INVALID -1
 
-// for ease of use in for loops
-enum WPADChannel_et {
-    WPAD_CHAN0,
-    WPAD_CHAN1,
-    WPAD_CHAN2,
-    WPAD_CHAN3,
+#define WPAD_MAX_CONTROLLERS 4
 
-    WPAD_MAX_CONTROLLERS,
-    WPAD_CHAN_INVALID = -1,
+enum WPADResult_et {
+    WPAD_ERR_OK = 0,
+
+    WPAD_ERR_NO_CONTROLLER = -1,
+    WPAD_ERR_BUSY = -2,
+    WPAD_ERR_TRANSFER = -3,
+    WPAD_ERR_INVALID = -4,
+    WPAD_ERR_5 = -5,
+    WPAD_ERR_6 = -6,
+    WPAD_ERR_CORRUPTED = -7,
 };
 
+#define WPAD_ESUCCESS WPAD_ERR_OK
+#define WPAD_ENODEV WPAD_ERR_NO_CONTROLLER
+#define WPAD_EBUSY WPAD_ERR_BUSY
+#define WPAD_ETRANSFER WPAD_ERR_TRANSFER  // I don't know what the POSIX equivalent is
+#define WPAD_EINVAL WPAD_ERR_INVALID
+#define WPAD_E5 WPAD_ERR_5
+#define WPAD_E6 WPAD_ERR_6
+#define WPAD_EBADE WPAD_ERR_CORRUPTED
+
+// apparently enum vs constant is a thing. cool
+#define WPAD_CESUCCESS (WPAD_ESUCCESS + 0)
+#define WPAD_CENODEV (WPAD_ENODEV + 0)
+#define WPAD_CEBUSY (WPAD_EBUSY + 0)
+#define WPAD_CETRANSFER (WPAD_ETRANSFER + 0)
+#define WPAD_CEINVAL (WPAD_EINVAL + 0)
+#define WPAD_CE5 (WPAD_E5 + 0)
+#define WPAD_CE6 (WPAD_E6 + 0)
+#define WPAD_CEBADE (WPAD_EBADE + 0)
+
+typedef void WPADInitFunc(void);
+typedef void WPADCallback(s32 chan, s32 result);
+typedef void WPADExtensionCallback(s32 chan, s32 devType);
+typedef void WPADSamplingCallback(s32 chan);
+typedef void WPADConnectCallback(s32 chan, s32 result);
+
+typedef struct DPDObject {
+    /* 0x00 */ s16 x;
+    /* 0x02 */ s16 y;
+    /* 0x04 */ u16 size;
+    /* 0x06 */ u8 traceId;
+} DPDObject;
+
+typedef struct WPADStatus {
+    /* 0x00 */ u16 button;
+    /* 0x02 */ s16 accX;
+    /* 0x04 */ s16 accY;
+    /* 0x06 */ s16 accZ;
+    /* 0x08 */ DPDObject obj[WPAD_MAX_DPD_OBJECTS];
+    /* 0x28 */ u8 dev;
+    /* 0x29 */ s8 err;
+} WPADStatus;
+
+typedef struct DPDObjEx {
+    /* 0x00 */ s16 range_x1;
+    /* 0x02 */ s16 range_y1;
+    /* 0x04 */ s16 range_x2;
+    /* 0x06 */ s16 range_y2;
+    /* 0x08 */ u16 pixel;
+    /* 0x0A */ s8 radius;
+} DPDObjEx;
+
+typedef struct WPADStatusEx {
+    /* 0x00 */ u16 button;
+    /* 0x02 */ s16 accX;
+    /* 0x04 */ s16 accY;
+    /* 0x06 */ s16 accZ;
+    /* 0x08 */ DPDObject obj[WPAD_MAX_DPD_OBJECTS];
+    /* 0x28 */ u8 dev;
+    /* 0x29 */ s8 err;
+    /* 0x2a */ DPDObjEx exp[WPAD_MAX_DPD_OBJECTS];
+} WPADStatusEx;
+
+typedef struct WPADFSStatus {
+    /* 0x00 */ u16 button;
+    /* 0x02 */ s16 accX;
+    /* 0x04 */ s16 accY;
+    /* 0x06 */ s16 accZ;
+    /* 0x08 */ DPDObject obj[WPAD_MAX_DPD_OBJECTS];
+    /* 0x28 */ u8 dev;
+    /* 0x29 */ s8 err;
+    /* 0x2a */ s16 fsAccX;
+    /* 0x2c */ s16 fsAccY;
+    /* 0x2e */ s16 fsAccZ;
+    /* 0x30 */ s8 fsStickX;
+    /* 0x31 */ s8 fsStickY;
+} WPADFSStatus;
+
+typedef struct WPADCLStatus {
+    /* 0x00 */ u16 button;
+    /* 0x02 */ s16 accX;
+    /* 0x04 */ s16 accY;
+    /* 0x06 */ s16 accZ;
+    /* 0x08 */ DPDObject obj[WPAD_MAX_DPD_OBJECTS];
+    /* 0x28 */ u8 dev;
+    /* 0x29 */ s8 err;
+    /* 0x2a */ u16 clButton;
+    /* 0x2c */ s16 clLStickX;
+    /* 0x2e */ s16 clLStickY;
+    /* 0x30 */ s16 clRStickX;
+    /* 0x32 */ s16 clRStickY;
+    /* 0x34 */ u8 clTriggerL;
+    /* 0x35 */ u8 clTriggerR;
+} WPADCLStatus;
+
+typedef struct WPADBKStatus {
+    /* 0x00 */ u16 button;
+    /* 0x02 */ s16 accX;
+    /* 0x04 */ s16 accY;
+    /* 0x06 */ s16 accZ;
+    /* 0x08 */ DPDObject obj[WPAD_MAX_DPD_OBJECTS];
+    /* 0x28 */ u8 dev;
+    /* 0x29 */ s8 err;
+    /* 0x2a */ u8 bulk[21];
+    /* 0x3f */ u8 padding[1];
+} WPADBKStatus;
+
+typedef struct WPADTRStatus {
+    /* 0x00 */ u16 button;
+    /* 0x02 */ s16 accX;
+    /* 0x04 */ s16 accY;
+    /* 0x06 */ s16 accZ;
+    /* 0x08 */ DPDObject obj[WPAD_MAX_DPD_OBJECTS];
+    /* 0x28 */ u8 dev;
+    /* 0x29 */ s8 err;
+    /* 0x2a */ u16 trButton;
+    /* 0x2c */ u8 brake;
+    /* 0x2d */ u8 mascon;
+} WPADTRStatus;
+
+typedef struct WPADVSStatus {
+    /* 0x00 */ u16 button;
+    /* 0x02 */ s16 accX;
+    /* 0x04 */ s16 accY;
+    /* 0x06 */ s16 accZ;
+    /* 0x08 */ DPDObject obj[WPAD_MAX_DPD_OBJECTS];
+    /* 0x28 */ u8 dev;
+    /* 0x29 */ s8 err;
+    /* 0x2a */ u16 at_0x2a[5];
+    /* 0x34 */ u8 at_0x34;
+    /* 0x36 */ u16 at_0x36[5];
+    /* 0x40 */ u8 at_0x40;
+    /* 0x42 */ u16 at_0x42;
+    /* 0x44 */ u8 at_0x44;
+} WPADVSStatus;
+
+typedef struct WPADMPStatus {
+    /* 0x00 */ u16 button;
+    /* 0x02 */ s16 accX;
+    /* 0x04 */ s16 accY;
+    /* 0x06 */ s16 accZ;
+    /* 0x08 */ DPDObject obj[WPAD_MAX_DPD_OBJECTS];
+    /* 0x28 */ u8 dev;
+    /* 0x29 */ s8 err;
+    union {
+        struct {
+            /* 0x00 */ s16 fsAccX;
+            /* 0x02 */ s16 fsAccY;
+            /* 0x04 */ s16 fsAccZ;
+            /* 0x06 */ s8 fsStickX;
+            /* 0x07 */ s8 fsStickY;
+        } fs;
+        struct {
+            /* 0x00 */ u16 clButton;
+            /* 0x02 */ s16 clLStickX;
+            /* 0x04 */ s16 clLStickY;
+            /* 0x06 */ s16 clRStickX;
+            /* 0x08 */ s16 clRStickY;
+            /* 0x0a */ u8 clTriggerL;
+            /* 0x0b */ u8 clTriggerR;
+        } cl;
+    } ext;
+    /* 0x36 */ u8 stat;
+    /* 0x37 */ u8 reserved;
+    /* 0x38 */ s16 pitch;
+    /* 0x3a */ s16 yaw;
+    /* 0x3c */ s16 roll;
+} WPADMPStatus;
+
+typedef struct WPADBLStatus {
+    /* 0x00 */ u16 button;
+    /* 0x02 */ s16 accX;
+    /* 0x04 */ s16 accY;
+    /* 0x06 */ s16 accZ;
+    /* 0x08 */ DPDObject obj[WPAD_MAX_DPD_OBJECTS];
+    /* 0x28 */ u8 dev;
+    /* 0x29 */ s8 err;
+    /* 0x2a */ u16 press[4];
+    /* 0x32 */ s8 temp;
+    /* 0x33 */ u8 battery;
+} WPADBLStatus;
+
 typedef struct WPADInfo {
     /* 0x00 */ BOOL dpd;
     /* 0x04 */ BOOL speaker;
@@ -48,11 +234,44 @@ typedef struct WPADInfo {
     /* 0x15 */ u8 led;
     /* 0x16 */ u8 protocol;
     /* 0x17 */ u8 firmware;
-} WPADInfo;  // size 0x18
+} WPADInfo;
+
+#define WPAD_FMT_CORE_BTN              0
+#define WPAD_FMT_CORE_BTN_ACC          1
+#define WPAD_FMT_CORE_BTN_ACC_DPD      2
+#define WPAD_FMT_FS_BTN                3
+#define WPAD_FMT_FS_BTN_ACC            4
+#define WPAD_FMT_FS_BTN_ACC_DPD        5
+#define WPAD_FMT_CLASSIC_BTN           6
+#define WPAD_FMT_CLASSIC_BTN_ACC       7
+#define WPAD_FMT_CLASSIC_BTN_ACC_DPD   8
+#define WPAD_FMT_BTN_ACC_DPD_EXTENDED  9
+// extensions
+#define WPAD_FMT_TRAIN                 10
+#define WPAD_FMT_GUITAR                11
+#define WPAD_FMT_BALANCE_CHECKER       12
+#define WPAD_FMT_VSM                   13
+#define WPAD_FMT_DRUM                  15
+#define WPAD_FMT_MOTION_PLUS           16
+#define WPAD_FMT_TAIKO                 17
+#define WPAD_FMT_TURNTABLE             18
+#define WPAD_FMT_BULK                  19
+
+#define WPAD_SPEAKER_DISABLE  0
+#define WPAD_SPEAKER_ENABLE   1  // might be ON? see HBMRemoteSpk.cpp
+#define WPAD_SPEAKER_MUTE     2
+#define WPAD_SPEAKER_UNMUTE   3
+#define WPAD_SPEAKER_PLAY     4
+#define WPAD_SPEAKER_CMD_05   5  // does the same thing as ENABLE? unless i'm missing something. not used so i don't know the context
 
-WPADResult WPADProbe(WPADChannel chan, WPADDeviceType* devType);
+s32 WPADProbe(s32 chan, u32* devType);
+u8 WPADGetRadioSensitivity(s32 chan);
+void WPADRead(s32 chan, WPADStatus* status);
+BOOL WPADIsSpeakerEnabled(s32 chan);
+s32 WPADControlSpeaker(s32 chan, u32 command, WPADCallback* cb);
+s32 WPADSendStreamData(s32 chan, void* p_buf, u16 len);
 
-WPADExtensionCallback* WPADSetExtensionCallback(WPADChannel chan, WPADExtensionCallback* cb);
+WPADExtensionCallback* WPADSetExtensionCallback(s32 chan, WPADExtensionCallback* cb);
 
 #ifdef __cplusplus
 }
diff --git a/include/revolution/wpad/bte.h b/include/revolution/wpad/bte.h
new file mode 100644
index 0000000000..1751d8998b
--- /dev/null
+++ b/include/revolution/wpad/bte.h
@@ -0,0 +1,1044 @@
+#ifndef CONTEXT_BTE_H
+#define CONTEXT_BTE_H
+
+#include <stdint.h>
+
+// taken from https://github.com/doldecomp/sdk_2009-12-11/blob/main/include/context_bte.h
+
+/* Contains the context of the BTE library that the WPAD library needs to
+ * compile.
+ *
+ * This is not the full context; the other half of the context is in
+ * <context_rvl.h>.
+ *
+ * Most of this code is copyright (C) 2003-2012 Broadcom Corporation under the
+ * Apache 2.0 License <http://www.apache.org/licenses/LICENSE-2.0>. The original
+ * source can be found at
+ * <https://android.googlesource.com/platform/external/bluetooth/bluedroid>;
+ * specifically, I used the earliest commit available (late 2012, commit hash
+ * 5738f83aeb59361a0a2eda2460113f6dc9194271).
+ */
+
+/* License redistribution conditions
+ *
+ * a. You may obtain a copy of the License at
+ *    <http://www.apache.org/licenses/LICENSE-2.0>.
+ * b. Some of the code is modified. Comments will be marked with my name
+ *    (muff1n) to show what I modified and where.
+ * c. See the following comment block, which is copied verbatim from bluedroid
+ *    source.
+ * d. No NOTICE file is present in the commit that I used.
+ */
+
+/******************************************************************************
+ *
+ *  Copyright (C) 2003-2012 Broadcom Corporation
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at:
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ ******************************************************************************/
+
+// from bluedroid source
+
+typedef uint8_t UINT8;
+typedef uint16_t UINT16;
+typedef uint32_t UINT32;
+
+typedef int8_t INT8;
+
+typedef unsigned char BOOLEAN;
+
+/* muff1n: It seems like BTE_TRACE_LEVEL_VERBOSE did not exist at the time. Or
+ * maybe it was a different logging level. At the very least, one logging level
+ * is missing.
+ */
+#define MAX_TRACE_LEVEL 5
+
+#define BD_ADDR_LEN     6                   /* Device address length */
+typedef UINT8 BD_ADDR[BD_ADDR_LEN];         /* Device address */
+typedef UINT8 *BD_ADDR_PTR;                 /* Pointer to Device Address */
+
+#define LINK_KEY_LEN    16
+typedef UINT8 LINK_KEY[LINK_KEY_LEN];       /* Link Key */
+
+#define DEV_CLASS_LEN   3
+typedef UINT8 DEV_CLASS[DEV_CLASS_LEN];     /* Device class */
+typedef UINT8 *DEV_CLASS_PTR;               /* Pointer to Device class */
+
+/* muff1n: TODO: bta_dm_pin_cback looks mostly the same except that BD_NAME_LEN
+ * is 33 (or it was 32 and BD_NAME_LEN was not decreased by 1 in BCM_STRNCPY_S
+ * calls)?
+ * confirm this
+ *
+ * UPDATE: there is a case where it is 248
+ */
+#define BD_NAME_LEN     248
+typedef UINT8 BD_NAME[BD_NAME_LEN];         /* Device name */
+typedef UINT8 *BD_NAME_PTR;                 /* Pointer to Device name */
+
+#define BD_FEATURES_LEN 8
+typedef UINT8 BD_FEATURES[BD_FEATURES_LEN]; /* LMP features supported by device */
+
+#define BT_DEVICE_TYPE_BREDR   0x01
+#define BT_DEVICE_TYPE_BLE     0x02
+#define BT_DEVICE_TYPE_DUMO    0x03
+typedef UINT8 tBT_DEVICE_TYPE;
+
+/* Maximum UUID size - 16 bytes, and structure to hold any type of UUID. */
+#define MAX_UUID_SIZE              16
+typedef struct
+{
+#define LEN_UUID_16     2
+#define LEN_UUID_32     4
+#define LEN_UUID_128    16
+
+    UINT16          len;
+
+    union
+    {
+        UINT16      uuid16;
+        UINT32      uuid32;
+        UINT8       uuid128[MAX_UUID_SIZE];
+    } uu;
+
+} tBT_UUID;
+
+/* Status Return Value */
+#define BTA_SUCCESS             0           /* Successful operation. */
+#define BTA_FAILURE             1           /* Generic failure. */
+#define BTA_PENDING             2           /* API cannot be completed right now */
+#define BTA_BUSY                3
+#define BTA_NO_RESOURCES        4
+#define BTA_WRONG_MODE          5
+
+typedef UINT8 tBTA_STATUS;
+
+/*
+ * Service ID
+ *
+ * NOTES: When you add a new Service ID for BTA AND require to change the value of BTA_MAX_SERVICE_ID,
+ *        make sure that the correct security ID of the new service from Security service definitions (btm_api.h)
+ *        should be added to bta_service_id_to_btm_srv_id_lkup_tbl table in bta_dm_act.c.
+ */
+
+#define BTA_RES_SERVICE_ID      0           /* Reserved */
+#define BTA_SPP_SERVICE_ID      1           /* Serial port profile. */
+#define BTA_DUN_SERVICE_ID      2           /* Dial-up networking profile. */
+#define BTA_A2DP_SOURCE_SERVICE_ID      3   /* A2DP Source profile. */
+#define BTA_LAP_SERVICE_ID      4           /* LAN access profile. */
+#define BTA_HSP_SERVICE_ID      5           /* Headset profile. */
+#define BTA_HFP_SERVICE_ID      6           /* Hands-free profile. */
+#define BTA_OPP_SERVICE_ID      7           /* Object push  */
+#define BTA_FTP_SERVICE_ID      8           /* File transfer */
+#define BTA_CTP_SERVICE_ID      9           /* Cordless Terminal */
+#define BTA_ICP_SERVICE_ID      10          /* Intercom Terminal */
+#define BTA_SYNC_SERVICE_ID     11          /* Synchronization */
+#define BTA_BPP_SERVICE_ID      12          /* Basic printing profile */
+#define BTA_BIP_SERVICE_ID      13          /* Basic Imaging profile */
+#define BTA_PANU_SERVICE_ID     14          /* PAN User */
+#define BTA_NAP_SERVICE_ID      15          /* PAN Network access point */
+#define BTA_GN_SERVICE_ID       16          /* PAN Group Ad-hoc networks */
+#define BTA_SAP_SERVICE_ID      17          /* SIM Access profile */
+#define BTA_A2DP_SERVICE_ID     18          /* A2DP Sink */
+#define BTA_AVRCP_SERVICE_ID    19          /* A/V remote control */
+#define BTA_HID_SERVICE_ID      20          /* HID */
+#define BTA_VDP_SERVICE_ID      21          /* Video distribution */
+#define BTA_PBAP_SERVICE_ID     22          /* PhoneBook Access Server*/
+#define BTA_HSP_HS_SERVICE_ID   23          /* HFP HS role */
+#define BTA_HFP_HS_SERVICE_ID   24          /* HSP HS role */
+#define BTA_MAP_SERVICE_ID      25          /* Message Access Profile */
+#define BTA_MN_SERVICE_ID       26          /* Message Notification Service */
+#define BTA_HDP_SERVICE_ID      27          /* Health Device Profile */
+#define BTA_PCE_SERVICE_ID      28          /* PhoneBook Access Client*/
+
+#define BTA_USER_SERVICE_ID     29          /* User requested UUID */
+#define BTA_MAX_SERVICE_ID      30
+
+/* service IDs (BTM_SEC_SERVICE_FIRST_EMPTY + 1) to (BTM_SEC_MAX_SERVICES - 1)
+ * are used by BTA JV */
+#define BTA_FIRST_JV_SERVICE_ID     (BTM_SEC_SERVICE_FIRST_EMPTY + 1)
+#define BTA_LAST_JV_SERVICE_ID      (BTM_SEC_MAX_SERVICES - 1)
+
+typedef UINT8 tBTA_SERVICE_ID;
+
+/* Service ID Mask */
+#define BTA_RES_SERVICE_MASK        0x00000001  /* Reserved */
+#define BTA_SPP_SERVICE_MASK        0x00000002  /* Serial port profile. */
+#define BTA_DUN_SERVICE_MASK        0x00000004  /* Dial-up networking profile. */
+#define BTA_FAX_SERVICE_MASK        0x00000008  /* Fax profile. */
+#define BTA_LAP_SERVICE_MASK        0x00000010  /* LAN access profile. */
+#define BTA_HSP_SERVICE_MASK        0x00000020  /* HSP AG role. */
+#define BTA_HFP_SERVICE_MASK        0x00000040  /* HFP AG role */
+#define BTA_OPP_SERVICE_MASK        0x00000080  /* Object push  */
+#define BTA_FTP_SERVICE_MASK        0x00000100  /* File transfer */
+#define BTA_CTP_SERVICE_MASK        0x00000200  /* Cordless Terminal */
+#define BTA_ICP_SERVICE_MASK        0x00000400  /* Intercom Terminal */
+#define BTA_SYNC_SERVICE_MASK       0x00000800  /* Synchronization */
+#define BTA_BPP_SERVICE_MASK        0x00001000  /* Print server */
+#define BTA_BIP_SERVICE_MASK        0x00002000  /* Basic Imaging */
+#define BTA_PANU_SERVICE_MASK       0x00004000  /* PAN User */
+#define BTA_NAP_SERVICE_MASK        0x00008000  /* PAN Network access point */
+#define BTA_GN_SERVICE_MASK         0x00010000  /* PAN Group Ad-hoc networks */
+#define BTA_SAP_SERVICE_MASK        0x00020000  /* PAN Group Ad-hoc networks */
+#define BTA_A2DP_SERVICE_MASK       0x00040000  /* Advanced audio distribution */
+#define BTA_AVRCP_SERVICE_MASK      0x00080000  /* A/V remote control */
+#define BTA_HID_SERVICE_MASK        0x00100000  /* HID */
+#define BTA_VDP_SERVICE_MASK        0x00200000  /* Video distribution */
+#define BTA_PBAP_SERVICE_MASK       0x00400000  /* Phone Book Server */
+#define BTA_HSP_HS_SERVICE_MASK     0x00800000  /* HFP HS role */
+#define BTA_HFP_HS_SERVICE_MASK     0x01000000  /* HSP HS role */
+#define BTA_MAS_SERVICE_MASK        0x02000000  /* Message Access Profile */
+#define BTA_MN_SERVICE_MASK         0x04000000  /* Message Notification Profile */
+#define BTA_HL_SERVICE_MASK         0x08000000  /* Health Device Profile */
+#define BTA_PCE_SERVICE_MASK        0x10000000  /* Phone Book Client */
+
+// btla-specific ++
+#define BTA_USER_SERVICE_MASK       0x20000000  /* Message Notification Profile */
+// btla-specific --
+
+#define BTA_ALL_SERVICE_MASK        0x1FFFFFFF  /* All services supported by BTA. */
+
+typedef UINT32 tBTA_SERVICE_MASK;
+
+/* SW sub-systems */
+#define BTA_ID_SYS          0            /* system manager */
+/* BLUETOOTH PART - from 0 to BTA_ID_BLUETOOTH_MAX */
+#define BTA_ID_DM           1            /* device manager */
+#define BTA_ID_DM_SEARCH    2            /* device manager search */
+#define BTA_ID_DM_SEC       3            /* device manager security */
+#define BTA_ID_DG           4            /* data gateway */
+#define BTA_ID_AG           5            /* audio gateway */
+#define BTA_ID_OPC          6            /* object push client */
+#define BTA_ID_OPS          7            /* object push server */
+#define BTA_ID_FTS          8            /* file transfer server */
+#define BTA_ID_CT           9            /* cordless telephony terminal */
+#define BTA_ID_FTC          10           /* file transfer client */
+#define BTA_ID_SS           11           /* synchronization server */
+#define BTA_ID_PR           12           /* Printer client */
+#define BTA_ID_BIC          13           /* Basic Imaging Client */
+#define BTA_ID_PAN          14           /* Personal Area Networking */
+#define BTA_ID_BIS          15           /* Basic Imaging Server */
+#define BTA_ID_ACC          16           /* Advanced Camera Client */
+#define BTA_ID_SC           17           /* SIM Card Access server */
+#define BTA_ID_AV           18           /* Advanced audio/video */
+#define BTA_ID_AVK          19           /* Audio/video sink */
+#define BTA_ID_HD           20           /* HID Device */
+#define BTA_ID_CG           21           /* Cordless Gateway */
+#define BTA_ID_BP           22           /* Basic Printing Client */
+#define BTA_ID_HH           23           /* Human Interface Device Host */
+#define BTA_ID_PBS          24           /* Phone Book Access Server */
+#define BTA_ID_PBC          25           /* Phone Book Access Client */
+#define BTA_ID_JV           26           /* Java */
+#define BTA_ID_HS           27           /* Headset */
+#define BTA_ID_MSE          28           /* Message Server Equipment */
+#define BTA_ID_MCE          29           /* Message Client Equipment */
+#define BTA_ID_HL           30           /* Health Device Profile*/
+#define BTA_ID_GATTC        31           /* GATT Client */
+#define BTA_ID_GATTS        32           /* GATT Client */
+#define BTA_ID_BLUETOOTH_MAX   33        /* last BT profile */
+
+/* FM */
+#define BTA_ID_FM           34           /* FM  */
+#define BTA_ID_FMTX         35           /* FM TX */
+
+/* SENSOR */
+#define BTA_ID_SSR          36           /* Sensor  */
+
+/* GPS */
+#define BTA_ID_GPS          37           /* GPS  */
+
+/* GENERIC */
+#define BTA_ID_PRM          38
+#define BTA_ID_SYSTEM       39           /* platform-specific */
+#define BTA_ID_SWRAP        40           /* Insight script wrapper */
+#define BTA_ID_MIP          41           /* Multicase Individual Polling */
+#define BTA_ID_RT           42           /* Audio Routing module: This module is always on. */
+
+/* JV */
+#define BTA_ID_JV1          43           /* JV1 */
+#define BTA_ID_JV2          44           /* JV2 */
+
+#define BTA_ID_MAX          (43 + BTA_DM_NUM_JV_ID)
+
+typedef UINT8 tBTA_SYS_ID;
+
+enum
+{
+    BTM_SUCCESS = 0,                    /* 0  Command succeeded                 */
+    BTM_CMD_STARTED,                    /* 1  Command started OK.               */
+    BTM_BUSY,                           /* 2  Device busy with another command  */
+    BTM_NO_RESOURCES,                   /* 3  No resources to issue command     */
+    BTM_MODE_UNSUPPORTED,               /* 4  Request for 1 or more unsupported modes */
+    BTM_ILLEGAL_VALUE,                  /* 5  Illegal parameter value           */
+    BTM_WRONG_MODE,                     /* 6  Device in wrong mode for request  */
+    BTM_UNKNOWN_ADDR,                   /* 7  Unknown remote BD address         */
+    BTM_DEVICE_TIMEOUT,                 /* 8  Device timeout                    */
+    BTM_BAD_VALUE_RET,                  /* 9  A bad value was received from HCI */
+    BTM_ERR_PROCESSING,                 /* 10 Generic error                     */
+    BTM_NOT_AUTHORIZED,                 /* 11 Authorization failed              */
+    BTM_DEV_RESET,                      /* 12 Device has been reset             */
+    BTM_CMD_STORED,                     /* 13 request is stored in control block */
+    BTM_ILLEGAL_ACTION,                 /* 14 state machine gets illegal command */
+    BTM_DELAY_CHECK,                    /* 15 delay the check on encryption */
+    BTM_SCO_BAD_LENGTH,                 /* 16 Bad SCO over HCI data length */
+    BTM_SUCCESS_NO_SECURITY,            /* 17 security passed, no security set  */
+    BTM_FAILED_ON_SECURITY ,             /* 18 security failed                   */
+    BTM_REPEATED_ATTEMPTS               /* 19 repeated attempts for LE security requests */
+};
+typedef UINT8 tBTM_STATUS;
+
+typedef struct
+{
+    UINT16          event;
+    UINT16          len;
+    UINT16          offset;
+    UINT16          layer_specific;
+} BT_HDR;
+
+#define BT_HDR_SIZE (sizeof (BT_HDR))
+
+/* Security Service Levels [bit mask] (BTM_SetSecurityLevel)
+** Encryption should not be used without authentication
+*/
+#define BTM_SEC_NONE               0x0000 /* Nothing required */
+#define BTM_SEC_IN_AUTHORIZE       0x0001 /* Inbound call requires authorization */
+#define BTM_SEC_IN_AUTHENTICATE    0x0002 /* Inbound call requires authentication */
+#define BTM_SEC_IN_ENCRYPT         0x0004 /* Inbound call requires encryption */
+#define BTM_SEC_OUT_AUTHORIZE      0x0008 /* Outbound call requires authorization */
+#define BTM_SEC_OUT_AUTHENTICATE   0x0010 /* Outbound call requires authentication */
+#define BTM_SEC_OUT_ENCRYPT        0x0020 /* Outbound call requires encryption */
+#define BTM_SEC_BOND               0x0040 /* Bonding */
+#define BTM_SEC_BOND_CONN          0x0080 /* bond_created_connection */
+#define BTM_SEC_FORCE_MASTER       0x0100 /* Need to switch connection to be master */
+#define BTM_SEC_ATTEMPT_MASTER     0x0200 /* Try to switch connection to be master */
+#define BTM_SEC_FORCE_SLAVE        0x0400 /* Need to switch connection to be master */
+#define BTM_SEC_ATTEMPT_SLAVE      0x0800 /* Try to switch connection to be slave */
+#define BTM_SEC_IN_MITM            0x1000 /* inbound Do man in the middle protection */
+#define BTM_SEC_OUT_MITM           0x2000 /* outbound Do man in the middle protection */
+
+/* Security Setting Mask */
+#define BTA_SEC_NONE            BTM_SEC_NONE                                         /* No security. */
+#define BTA_SEC_AUTHORIZE       (BTM_SEC_IN_AUTHORIZE )                              /* Authorization required (only needed for out going connection )*/
+#define BTA_SEC_AUTHENTICATE    (BTM_SEC_IN_AUTHENTICATE | BTM_SEC_OUT_AUTHENTICATE) /* Authentication required. */
+#define BTA_SEC_ENCRYPT         (BTM_SEC_IN_ENCRYPT | BTM_SEC_OUT_ENCRYPT)           /* Encryption required. */
+
+typedef UINT8 tBTA_SEC;
+
+/* Pairable Modes */
+#define BTA_DM_PAIRABLE         1
+#define BTA_DM_NON_PAIRABLE     0
+
+/* Connectable Paired Only Mode */
+#define BTA_DM_CONN_ALL         0
+#define BTA_DM_CONN_PAIRED      1
+
+/* Inquiry modes
+ * Note: These modes are associated with the inquiry active values (BTM_*ACTIVE) */
+#define BTM_GENERAL_INQUIRY         0
+#define BTM_LIMITED_INQUIRY         1
+#define BTM_BR_INQUIRY_MASK         0x0f
+/* high byte of inquiry mode for BLE inquiry mode */
+#define BTM_BLE_INQUIRY_NONE         0x00
+#define BTM_BLE_GENERAL_INQUIRY      0x10
+#define BTM_BLE_LIMITED_INQUIRY      0x20
+#define BTM_BLE_INQUIRY_MASK         (BTM_BLE_GENERAL_INQUIRY|BTM_BLE_LIMITED_INQUIRY)
+
+#define BTA_BLE_INQUIRY_NONE    BTM_BLE_INQUIRY_NONE
+#define BTA_BLE_GENERAL_INQUIRY BTM_BLE_GENERAL_INQUIRY      /* Perform LE general inquiry. */
+#define BTA_BLE_LIMITED_INQUIRY BTM_BLE_LIMITED_INQUIRY      /* Perform LE limited inquiry. */
+typedef UINT8 tBTA_DM_INQ_MODE;
+
+/* Inquiry Filter Type */
+#define BTA_DM_INQ_CLR          BTM_CLR_INQUIRY_FILTER          /* Clear inquiry filter. */
+#define BTA_DM_INQ_DEV_CLASS    BTM_FILTER_COND_DEVICE_CLASS    /* Filter on device class. */
+#define BTA_DM_INQ_BD_ADDR      BTM_FILTER_COND_BD_ADDR         /* Filter on a specific  BD address. */
+
+typedef UINT8 tBTA_DM_INQ_FILT;
+
+/* Inquiry filter device class condition */
+typedef struct
+{
+    DEV_CLASS       dev_class;        /* device class of interest */
+    DEV_CLASS       dev_class_mask;   /* mask to determine the bits of device class of interest */
+} tBTA_DM_COD_COND;
+
+/* Inquiry Filter Condition */
+typedef union
+{
+    BD_ADDR              bd_addr;            /* BD address of  device to filter. */
+    tBTA_DM_COD_COND     dev_class_cond;     /* Device class filter condition */
+} tBTA_DM_INQ_COND;
+
+/* Inquiry Parameters */
+typedef struct
+{
+    tBTA_DM_INQ_MODE    mode;           /* Inquiry mode, limited or general. */
+    UINT8               duration;       /* Inquiry duration in 1.28 sec units. */
+    UINT8               max_resps;      /* Maximum inquiry responses.  Set to zero for unlimited responses. */
+    BOOLEAN             report_dup;     /* report duplicated inquiry response with higher RSSI value */
+    tBTA_DM_INQ_FILT    filter_type;    /* Filter condition type. */
+    tBTA_DM_INQ_COND    filter_cond;    /* Filter condition data. */
+} tBTA_DM_INQ;
+
+/* Security Callback Events */
+#define BTA_DM_ENABLE_EVT               0       /* Enable Event */
+#define BTA_DM_DISABLE_EVT              1       /* Disable Event */
+#define BTA_DM_PIN_REQ_EVT              2       /* PIN request. */
+#define BTA_DM_AUTH_CMPL_EVT            3       /* Authentication complete indication. */
+#define BTA_DM_AUTHORIZE_EVT            4       /* Authorization request. */
+#define BTA_DM_LINK_UP_EVT              5       /* Connection UP event */
+#define BTA_DM_LINK_DOWN_EVT            6       /* Connection DOWN event */
+#define BTA_DM_SIG_STRENGTH_EVT         7       /* Signal strength for bluetooth connection */
+#define BTA_DM_BUSY_LEVEL_EVT           8       /* System busy level */
+#define BTA_DM_BOND_CANCEL_CMPL_EVT     9       /* Bond cancel complete indication */
+#define BTA_DM_SP_CFM_REQ_EVT           10      /* Simple Pairing User Confirmation request. */
+#define BTA_DM_SP_KEY_NOTIF_EVT         11      /* Simple Pairing Passkey Notification */
+#define BTA_DM_SP_RMT_OOB_EVT           12      /* Simple Pairing Remote OOB Data request. */
+#define BTA_DM_SP_KEYPRESS_EVT          13      /* Key press notification event. */
+#define BTA_DM_ROLE_CHG_EVT             14      /* Role Change event. */
+#define BTA_DM_BLE_KEY_EVT              15      /* BLE SMP key event for peer device keys */
+#define BTA_DM_BLE_SEC_REQ_EVT          16      /* BLE SMP security request */
+#define BTA_DM_BLE_PASSKEY_NOTIF_EVT    17      /* SMP passkey notification event */
+#define BTA_DM_BLE_PASSKEY_REQ_EVT      18      /* SMP passkey request event */
+#define BTA_DM_BLE_OOB_REQ_EVT          19      /* SMP OOB request event */
+#define BTA_DM_BLE_LOCAL_IR_EVT         20      /* BLE local IR event */
+#define BTA_DM_BLE_LOCAL_ER_EVT         21      /* BLE local ER event */
+// btla-specific ++
+#define BTA_DM_BLE_AUTH_CMPL_EVT        22      /* BLE Auth complete */
+// btla-specific --
+#define BTA_DM_DEV_UNPAIRED_EVT         23
+#define BTA_DM_HW_ERROR_EVT             24      /* BT Chip H/W error */
+typedef UINT8 tBTA_DM_SEC_EVT;
+
+/* Structure associated with BTA_DM_ENABLE_EVT */
+typedef struct
+{
+    BD_ADDR         bd_addr;            /* BD address of local device. */
+    tBTA_STATUS     status;
+} tBTA_DM_ENABLE;
+
+/* Structure associated with BTA_DM_PIN_REQ_EVT */
+typedef struct
+{
+    BD_ADDR         bd_addr;            /* BD address peer device. */
+    BD_NAME         bd_name;            /* Name of peer device. */
+    DEV_CLASS       dev_class;          /* Class of Device */
+} tBTA_DM_PIN_REQ;
+
+/* Link Key Notification Event (Key Type) definitions */
+#define HCI_LKEY_TYPE_COMBINATION       0x00
+#define HCI_LKEY_TYPE_LOCAL_UNIT        0x01
+#define HCI_LKEY_TYPE_REMOTE_UNIT       0x02
+#define HCI_LKEY_TYPE_DEBUG_COMB        0x03
+#define HCI_LKEY_TYPE_UNAUTH_COMB       0x04
+#define HCI_LKEY_TYPE_AUTH_COMB         0x05
+#define HCI_LKEY_TYPE_CHANGED_COMB      0x06
+
+/* Structure associated with BTA_DM_AUTH_CMPL_EVT */
+typedef struct
+{
+    BD_ADDR         bd_addr;            /* BD address peer device. */
+    BD_NAME         bd_name;            /* Name of peer device. */
+    BOOLEAN         key_present;        /* Valid link key value in key element */
+    LINK_KEY        key;                /* Link key associated with peer device. */
+    UINT8           key_type;           /* The type of Link Key */
+    BOOLEAN         success;            /* TRUE of authentication succeeded, FALSE if failed. */
+    UINT8           fail_reason;        /* The HCI reason/error code for when success=FALSE */
+} tBTA_DM_AUTH_CMPL;
+
+/* Structure associated with BTA_DM_AUTHORIZE_EVT */
+typedef struct
+{
+    BD_ADDR         bd_addr;            /* BD address peer device. */
+    BD_NAME         bd_name;            /* Name of peer device. */
+    tBTA_SERVICE_ID service;            /* Service ID to authorize. */
+// btla-specific ++
+    DEV_CLASS       dev_class;
+// btla-specific --
+} tBTA_DM_AUTHORIZE;
+
+/* Structure associated with BTA_DM_LINK_UP_EVT */
+typedef struct
+{
+    BD_ADDR         bd_addr;            /* BD address peer device. */
+} tBTA_DM_LINK_UP;
+
+/*
+**  Defentions for HCI Error Codes that are past in the events
+*/
+#define HCI_SUCCESS                                     0x00
+#define HCI_PENDING                                     0x00
+#define HCI_ERR_ILLEGAL_COMMAND                         0x01
+#define HCI_ERR_NO_CONNECTION                           0x02
+#define HCI_ERR_HW_FAILURE                              0x03
+#define HCI_ERR_PAGE_TIMEOUT                            0x04
+#define HCI_ERR_AUTH_FAILURE                            0x05
+#define HCI_ERR_KEY_MISSING                             0x06
+#define HCI_ERR_MEMORY_FULL                             0x07
+#define HCI_ERR_CONNECTION_TOUT                         0x08
+#define HCI_ERR_MAX_NUM_OF_CONNECTIONS                  0x09
+#define HCI_ERR_MAX_NUM_OF_SCOS                         0x0A
+#define HCI_ERR_CONNECTION_EXISTS                       0x0B
+#define HCI_ERR_COMMAND_DISALLOWED                      0x0C
+#define HCI_ERR_HOST_REJECT_RESOURCES                   0x0D
+#define HCI_ERR_HOST_REJECT_SECURITY                    0x0E
+#define HCI_ERR_HOST_REJECT_DEVICE                      0x0F
+#define HCI_ERR_HOST_TIMEOUT                            0x10
+#define HCI_ERR_UNSUPPORTED_VALUE                       0x11
+#define HCI_ERR_ILLEGAL_PARAMETER_FMT                   0x12
+#define HCI_ERR_PEER_USER                               0x13
+#define HCI_ERR_PEER_LOW_RESOURCES                      0x14
+#define HCI_ERR_PEER_POWER_OFF                          0x15
+#define HCI_ERR_CONN_CAUSE_LOCAL_HOST                   0x16
+#define HCI_ERR_REPEATED_ATTEMPTS                       0x17
+#define HCI_ERR_PAIRING_NOT_ALLOWED                     0x18
+#define HCI_ERR_UNKNOWN_LMP_PDU                         0x19
+#define HCI_ERR_UNSUPPORTED_REM_FEATURE                 0x1A
+#define HCI_ERR_SCO_OFFSET_REJECTED                     0x1B
+#define HCI_ERR_SCO_INTERVAL_REJECTED                   0x1C
+#define HCI_ERR_SCO_AIR_MODE                            0x1D
+#define HCI_ERR_INVALID_LMP_PARAM                       0x1E
+#define HCI_ERR_UNSPECIFIED                             0x1F
+#define HCI_ERR_UNSUPPORTED_LMP_FEATURE                 0x20
+#define HCI_ERR_ROLE_CHANGE_NOT_ALLOWED                 0x21
+#define HCI_ERR_LMP_RESPONSE_TIMEOUT                    0x22
+#define HCI_ERR_LMP_ERR_TRANS_COLLISION                 0x23
+#define HCI_ERR_LMP_PDU_NOT_ALLOWED                     0x24
+#define HCI_ERR_ENCRY_MODE_NOT_ACCEPTABLE               0x25
+#define HCI_ERR_UNIT_KEY_USED                           0x26
+#define HCI_ERR_QOS_NOT_SUPPORTED                       0x27
+#define HCI_ERR_INSTANT_PASSED                          0x28
+#define HCI_ERR_PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED     0x29
+#define HCI_ERR_DIFF_TRANSACTION_COLLISION              0x2A
+#define HCI_ERR_UNDEFINED_0x2B                          0x2B
+#define HCI_ERR_QOS_UNACCEPTABLE_PARAM                  0x2C
+#define HCI_ERR_QOS_REJECTED                            0x2D
+#define HCI_ERR_CHAN_CLASSIF_NOT_SUPPORTED              0x2E
+#define HCI_ERR_INSUFFCIENT_SECURITY                    0x2F
+#define HCI_ERR_PARAM_OUT_OF_RANGE                      0x30
+#define HCI_ERR_UNDEFINED_0x31                          0x31
+#define HCI_ERR_ROLE_SWITCH_PENDING                     0x32
+#define HCI_ERR_UNDEFINED_0x33                          0x33
+#define HCI_ERR_RESERVED_SLOT_VIOLATION                 0x34
+#define HCI_ERR_ROLE_SWITCH_FAILED                      0x35
+#define HCI_ERR_INQ_RSP_DATA_TOO_LARGE                  0x36
+#define HCI_ERR_SIMPLE_PAIRING_NOT_SUPPORTED            0x37
+#define HCI_ERR_HOST_BUSY_PAIRING                       0x38
+#define HCI_ERR_REJ_NO_SUITABLE_CHANNEL                 0x39
+#define HCI_ERR_CONTROLLER_BUSY                         0x3A
+#define HCI_ERR_UNACCEPT_CONN_INTERVAL                  0x3B
+#define HCI_ERR_DIRECTED_ADVERTISING_TIMEOUT            0x3C
+#define HCI_ERR_CONN_TOUT_DUE_TO_MIC_FAILURE            0x3D
+#define HCI_ERR_CONN_FAILED_ESTABLISHMENT               0x3E
+#define HCI_ERR_MAC_CONNECTION_FAILED                   0x3F
+
+#define HCI_ERR_MAX_ERR                                 0x40
+
+#define HCI_HINT_TO_RECREATE_AMP_PHYS_LINK              0xFF
+
+/* Structure associated with BTA_DM_LINK_DOWN_EVT */
+typedef struct
+{
+    BD_ADDR         bd_addr;            /* BD address peer device. */
+    UINT8           status;             /* connection open/closed */
+} tBTA_DM_LINK_DOWN;
+
+typedef INT8 tBTA_DM_RSSI_VALUE;
+typedef UINT8 tBTA_DM_LINK_QUALITY_VALUE;
+
+/* signal strength mask */
+#define BTA_SIG_STRENGTH_RSSI_MASK          1
+#define BTA_SIG_STRENGTH_LINK_QUALITY_MASK  2
+
+typedef UINT8 tBTA_SIG_STRENGTH_MASK;
+
+/* Structure associated with BTA_DM_SIG_STRENGTH_EVT */
+typedef struct
+{
+    BD_ADDR         bd_addr;            /* BD address peer device. */
+    tBTA_SIG_STRENGTH_MASK mask;        /* mask for the values that are valid */
+    tBTA_DM_RSSI_VALUE  rssi_value;
+    tBTA_DM_LINK_QUALITY_VALUE link_quality_value;
+
+} tBTA_DM_SIG_STRENGTH;
+
+/* Structure associated with BTA_DM_BUSY_LEVEL_EVT */
+typedef struct
+{
+    UINT8           level;     /* when paging or inquiring, level is 10.
+                                    Otherwise, the number of ACL links */
+} tBTA_DM_BUSY_LEVEL;
+
+// muff1n: only filled with used members
+typedef union
+{
+    tBTA_DM_ENABLE      enable;         /* BTA enabled */
+    tBTA_DM_PIN_REQ     pin_req;        /* PIN request */
+    tBTA_DM_AUTH_CMPL   auth_cmpl;      /* Authentication complete indication */
+    tBTA_DM_AUTHORIZE   authorize;      /* Authorization request */
+    tBTA_DM_LINK_UP     link_up;        /* ACL connection up event */
+    tBTA_DM_LINK_DOWN   link_down;      /* ACL connection down event */
+    tBTA_DM_SIG_STRENGTH sig_strength;  /* rssi and link quality value */
+    tBTA_DM_BUSY_LEVEL  busy_level;     /* System busy level */
+} tBTA_DM_SEC;
+
+typedef void (tBTA_DM_SEC_CBACK)(tBTA_DM_SEC_EVT event, tBTA_DM_SEC *p_data);
+
+/* Search callback events */
+#define BTA_DM_INQ_RES_EVT              0       /* Inquiry result for a peer device. */
+#define BTA_DM_INQ_CMPL_EVT             1       /* Inquiry complete. */
+#define BTA_DM_DISC_RES_EVT             2       /* Discovery result for a peer device. */
+#define BTA_DM_DISC_BLE_RES_EVT         3       /* Discovery result for BLE GATT based service on a peer device. */
+#define BTA_DM_DISC_CMPL_EVT            4       /* Discovery complete. */
+#define BTA_DM_DI_DISC_CMPL_EVT         5       /* Discovery complete. */
+#define BTA_DM_SEARCH_CANCEL_CMPL_EVT   6       /* Search cancelled */
+
+typedef UINT8 tBTA_DM_SEARCH_EVT;
+
+#define BTA_DM_INQ_RES_IGNORE_RSSI      BTM_INQ_RES_IGNORE_RSSI /* 0x7f RSSI value not supplied (ignore it) */
+
+// muff1n: commented some fields out
+/* Structure associated with BTA_DM_INQ_RES_EVT */
+typedef struct
+{
+    BD_ADDR         bd_addr;                /* BD address peer device. */
+    DEV_CLASS       dev_class;              /* Device class of peer device. */
+    //BOOLEAN         remt_name_not_required; /* Application sets this flag if it already knows the name of the device */
+                                            /* If the device name is known to application BTA skips the remote name request */
+    //BOOLEAN         is_limited;             /* TRUE, if the limited inquiry bit is set in the CoD */
+    INT8            rssi;                   /* The rssi value */
+    UINT8           *p_eir;                 /* received EIR */
+} tBTA_DM_INQ_RES;
+
+/* Structure associated with BTA_DM_INQ_CMPL_EVT */
+typedef struct
+{
+    UINT8           num_resps;          /* Number of inquiry responses. */
+} tBTA_DM_INQ_CMPL;
+
+/* Structure associated with BTA_DM_DI_DISC_CMPL_EVT */
+typedef struct
+{
+    BD_ADDR             bd_addr;        /* BD address peer device. */
+    UINT8               num_record;     /* Number of DI record */
+    tBTA_STATUS         result;
+} tBTA_DM_DI_DISC_CMPL;
+
+/* Structure associated with BTA_DM_DISC_RES_EVT */
+typedef struct
+{
+    BD_ADDR             bd_addr;        /* BD address peer device. */
+    BD_NAME             bd_name;        /* Name of peer device. */
+    tBTA_SERVICE_MASK   services;       /* Services found on peer device. */
+// btla-specific ++
+    UINT8           *   p_raw_data;     /* Raw data for discovery DB */
+    UINT32              raw_data_size;  /* size of raw data */
+    tBT_DEVICE_TYPE     device_type;    /* device type in case it is BLE device */
+    UINT32              num_uuids;
+    UINT8               *p_uuid_list;
+// btla-specific --
+    tBTA_STATUS         result;
+} tBTA_DM_DISC_RES;
+
+/* Structure associated with tBTA_DM_DISC_BLE_RES */
+typedef struct
+{
+    BD_ADDR             bd_addr;        /* BD address peer device. */
+    BD_NAME             bd_name;        /* Name of peer device. */
+    tBT_UUID            service;        /* GATT based Services UUID found on peer device. */
+} tBTA_DM_DISC_BLE_RES;
+
+/* Union of all search callback structures */
+typedef union
+{
+    tBTA_DM_INQ_RES     inq_res;        /* Inquiry result for a peer device. */
+    tBTA_DM_INQ_CMPL    inq_cmpl;       /* Inquiry complete. */
+    tBTA_DM_DISC_RES    disc_res;       /* Discovery result for a peer device. */
+    tBTA_DM_DISC_BLE_RES    disc_ble_res;   /* discovery result for GATT based service */
+    tBTA_DM_DI_DISC_CMPL    di_disc;        /* DI discovery result for a peer device */
+} tBTA_DM_SEARCH;
+
+/* Search callback */
+typedef void (tBTA_DM_SEARCH_CBACK)(tBTA_DM_SEARCH_EVT event, tBTA_DM_SEARCH *p_data);
+
+/* type of protocol mode */
+#define BTA_HH_PROTO_RPT_MODE                   (0x00)
+#define BTA_HH_PROTO_BOOT_MODE                  (0x01)
+#define BTA_HH_PROTO_UNKNOWN                    (0xff)
+typedef UINT8   tBTA_HH_PROTO_MODE;
+
+/* BTA HID Host callback events */
+#define BTA_HH_ENABLE_EVT       0       /* HH enabled */
+#define BTA_HH_DISABLE_EVT      1       /* HH disabled */
+#define BTA_HH_OPEN_EVT         2       /* connection opened */
+#define BTA_HH_CLOSE_EVT        3       /* connection closed */
+#define BTA_HH_GET_RPT_EVT      4       /* BTA_HhGetReport callback */
+#define BTA_HH_SET_RPT_EVT      5       /* BTA_HhSetReport callback */
+#define BTA_HH_GET_PROTO_EVT    6       /* BTA_GetProtoMode callback */
+#define BTA_HH_SET_PROTO_EVT    7       /* BTA_HhSetProtoMode callback */
+#define BTA_HH_GET_IDLE_EVT     8       /* BTA_HhGetIdle comes callback */
+#define BTA_HH_SET_IDLE_EVT     9       /* BTA_HhSetIdle finish callback */
+#define BTA_HH_GET_DSCP_EVT     10      /* Get report descripotor */
+#define BTA_HH_ADD_DEV_EVT      11      /* Add Device callback */
+#define BTA_HH_RMV_DEV_EVT      12      /* remove device finished */
+#define BTA_HH_VC_UNPLUG_EVT    13      /* virtually unplugged */
+#define BTA_HH_UPDATE_UCD_EVT   14
+#define BTA_HH_API_ERR_EVT      15      /* API error is caught */
+
+typedef UINT16 tBTA_HH_EVT;
+
+enum
+{
+    BTA_HH_OK,
+    BTA_HH_HS_HID_NOT_READY,    /* handshake error : device not ready */
+    BTA_HH_HS_INVALID_RPT_ID,   /* handshake error : invalid report ID */
+    BTA_HH_HS_TRANS_NOT_SPT,    /* handshake error : transaction not spt */
+    BTA_HH_HS_INVALID_PARAM,    /* handshake error : invalid paremter */
+    BTA_HH_HS_ERROR,            /* handshake error : unspecified HS error */
+    BTA_HH_ERR,                 /* general BTA HH error */
+    BTA_HH_ERR_SDP,             /* SDP error */
+    BTA_HH_ERR_PROTO,           /* SET_Protocol error,
+                                    only used in BTA_HH_OPEN_EVT callback */
+    BTA_HH_ERR_DB_FULL,         /* device database full error, used in
+                                   BTA_HH_OPEN_EVT/BTA_HH_ADD_DEV_EVT */
+    BTA_HH_ERR_TOD_UNSPT,       /* type of device not supported */
+    BTA_HH_ERR_NO_RES,          /* out of system resources */
+    BTA_HH_ERR_AUTH_FAILED,     /* authentication fail */
+    BTA_HH_ERR_HDL
+};
+typedef UINT8 tBTA_HH_STATUS;
+
+/* callback event data for BTA_HH_OPEN_EVT */
+typedef struct
+{
+    BD_ADDR         bda;                /* HID device bd address    */
+    tBTA_HH_STATUS  status;             /* operation status         */
+    UINT8           handle;             /* device handle            */
+} tBTA_HH_CONN;
+
+typedef tBTA_HH_CONN tBTA_HH_DEV_INFO;
+
+/* callback event data */
+typedef struct
+{
+    tBTA_HH_STATUS              status;     /* operation status         */
+    UINT8                       handle;     /* device handle            */
+} tBTA_HH_CBDATA;
+
+// muff1n: only filled with used members
+typedef union
+{
+    tBTA_HH_DEV_INFO        dev_info;           /* BTA_HH_ADD_DEV_EVT, BTA_HH_RMV_DEV_EVT   */
+    tBTA_HH_CONN            conn;               /* BTA_HH_OPEN_EVT      */
+    tBTA_HH_CBDATA          dev_status;         /* BTA_HH_CLOSE_EVT,
+                                                   BTA_HH_SET_PROTO_EVT
+                                                   BTA_HH_SET_RPT_EVT
+                                                   BTA_HH_SET_IDLE_EVT  */
+} tBTA_HH;
+
+/* BTA HH callback function */
+typedef void (tBTA_HH_CBACK) (tBTA_HH_EVT event, tBTA_HH *p_data);
+
+/* General callback function for notifying an application that a synchronous
+** BTM function is complete. The pointer contains the address of any returned data.
+*/
+typedef void (tBTM_CMPL_CB) (void *p1);
+/* Structure returned with local version information */
+
+typedef struct
+{
+    UINT8       hci_version;
+    UINT16      hci_revision;
+    UINT8       lmp_version;
+    UINT16      manufacturer;
+    UINT16      lmp_subversion;
+} tBTM_VERSION_INFO;
+
+/* Structure returned with Vendor Specific Command complete callback */
+typedef struct
+{
+    UINT16  opcode;
+    UINT16  param_len;
+    UINT8   *p_param_buf;
+} tBTM_VSC_CMPL;
+
+#define  BTM_VSC_CMPL_DATA_SIZE  (BTM_MAX_VENDOR_SPECIFIC_LEN + sizeof(tBTM_VSC_CMPL))
+/* Callback function for when device status changes. Appl must poll for
+** what the new state is (BTM_IsDeviceUp). The event occurs whenever the stack
+** has detected that the controller status has changed. This asynchronous event
+** is enabled/disabled by calling BTM_RegisterForDeviceStatusNotif().
+*/
+enum
+{
+    BTM_DEV_STATUS_UP,
+    BTM_DEV_STATUS_DOWN,
+    BTM_DEV_STATUS_CMD_TOUT
+};
+typedef UINT8 tBTM_DEV_STATUS;
+
+typedef void (tBTM_DEV_STATUS_CB) (tBTM_DEV_STATUS status);
+
+/* Callback function for when a vendor specific event occurs. The length and
+** array of returned parameter bytes are included. This asynchronous event
+** is enabled/disabled by calling BTM_RegisterForVSEvents().
+*/
+typedef void (tBTM_VS_EVT_CB) (UINT8 len, UINT8 *p);
+
+/* VSC callback function for notifying an application that a synchronous
+** BTM function is complete. The pointer contains the address of any returned data.
+*/
+typedef void (tBTM_VSC_CMPL_CB) (tBTM_VSC_CMPL *p1);
+
+/* Attributes mask values to be used in HID_HostAddDev API */
+#define HID_VIRTUAL_CABLE        0x0001
+#define HID_NORMALLY_CONNECTABLE 0x0002
+#define HID_RECONN_INIT          0x0004
+#define HID_SDP_DISABLE          0x0008
+#define HID_BATTERY_POWER        0x0010
+#define HID_REMOTE_WAKE          0x0020
+#define HID_SUP_TOUT_AVLBL       0x0040
+#define HID_SSR_MAX_LATENCY      0x0080
+#define HID_SSR_MIN_TOUT         0x0100
+
+#define HID_SEC_REQUIRED         0x8000
+
+#define BTA_HH_VIRTUAL_CABLE           HID_VIRTUAL_CABLE
+#define BTA_HH_NORMALLY_CONNECTABLE    HID_NORMALLY_CONNECTABLE
+#define BTA_HH_RECONN_INIT             HID_RECONN_INIT
+#define BTA_HH_SDP_DISABLE             HID_SDP_DISABLE
+#define BTA_HH_BATTERY_POWER           HID_BATTERY_POWER
+#define BTA_HH_REMOTE_WAKE             HID_REMOTE_WAKE
+#define BTA_HH_SUP_TOUT_AVLBL          HID_SUP_TOUT_AVLBL
+#define BTA_HH_SEC_REQUIRED             HID_SEC_REQUIRED
+typedef UINT16 tBTA_HH_ATTR_MASK;
+
+typedef struct desc_info
+{
+    UINT16 dl_len;
+    UINT8 *dsc_list;
+} tHID_DEV_DSCP_INFO;
+
+typedef tHID_DEV_DSCP_INFO tBTA_HH_DEV_DESCR;
+
+/* Policy settings status */
+#define HCI_DISABLE_ALL_LM_MODES        0x0000
+#define HCI_ENABLE_MASTER_SLAVE_SWITCH  0x0001
+#define HCI_ENABLE_HOLD_MODE            0x0002
+#define HCI_ENABLE_SNIFF_MODE           0x0004
+#define HCI_ENABLE_PARK_MODE            0x0008
+
+/* HCI mode defenitions */
+#define HCI_MODE_ACTIVE                 0x00
+#define HCI_MODE_HOLD                   0x01
+#define HCI_MODE_SNIFF                  0x02
+#define HCI_MODE_PARK                   0x03
+
+/* BTM Power manager status codes */
+enum
+{
+    BTM_PM_STS_ACTIVE = HCI_MODE_ACTIVE,
+    BTM_PM_STS_HOLD   = HCI_MODE_HOLD,
+    BTM_PM_STS_SNIFF  = HCI_MODE_SNIFF,
+    BTM_PM_STS_PARK   = HCI_MODE_PARK,
+    BTM_PM_STS_SSR,     /* report the SSR parameters in HCI_SNIFF_SUB_RATE_EVT */
+    BTM_PM_STS_PENDING,   /* when waiting for status from controller */
+    BTM_PM_STS_ERROR   /* when HCI command status returns error */
+};
+typedef UINT8 tBTM_PM_STATUS;
+
+/* BTM Power manager modes */
+
+enum
+{
+    BTM_PM_MD_ACTIVE = BTM_PM_STS_ACTIVE,
+    BTM_PM_MD_HOLD   = BTM_PM_STS_HOLD,
+    BTM_PM_MD_SNIFF  = BTM_PM_STS_SNIFF,
+    BTM_PM_MD_PARK   = BTM_PM_STS_PARK,
+    BTM_PM_MD_FORCE  = 0x10 /* OR this to force ACL link to a certain mode */
+};
+typedef UINT8 tBTM_PM_MODE;
+
+#define BTM_PM_SET_ONLY_ID  0x80
+
+/* Operation codes */
+#define BTM_PM_REG_SET      1 /* The module wants to set the desired power mode */
+#define BTM_PM_REG_NOTIF    2 /* The module wants to receive mode change event */
+#define BTM_PM_DEREG        4 /* The module does not want to involve with PM anymore */
+
+typedef struct
+{
+    UINT16          max;
+    UINT16          min;
+    UINT16          attempt;
+    UINT16          timeout;
+    tBTM_PM_MODE    mode;
+} tBTM_PM_PWR_MD;
+
+/*************************************
+**  Power Manager Callback Functions
+**************************************/
+typedef void (tBTM_PM_STATUS_CBACK) (BD_ADDR p_bda, tBTM_PM_STATUS status,
+                                     UINT16 value, UINT8 hci_status);
+
+/************************
+**  Stored Linkkey Types
+*************************/
+#define BTM_CB_EVT_RETURN_LINK_KEYS         1
+#define BTM_CB_EVT_READ_STORED_LINK_KEYS    2
+#define BTM_CB_EVT_WRITE_STORED_LINK_KEYS   3
+#define BTM_CB_EVT_DELETE_STORED_LINK_KEYS  4
+
+typedef struct
+{
+    UINT8          event;
+
+} tBTM_STORED_LINK_KEYS_EVT;
+
+
+typedef struct
+{
+    UINT8          event;
+    UINT8          num_keys;
+
+} tBTM_RETURN_LINK_KEYS_EVT;
+
+
+typedef struct
+{
+    BD_ADDR         bd_addr;
+    LINK_KEY        link_key;
+
+} tBTM_BD_ADDR_LINK_KEY_PAIR;
+
+
+typedef struct
+{
+    UINT8          event;
+    UINT8          status;
+    UINT16         max_keys;
+    UINT16         read_keys;
+
+} tBTM_READ_STORED_LINK_KEY_COMPLETE;
+
+
+typedef struct
+{
+    UINT8          event;
+    UINT8          status;
+    UINT8          num_keys;
+
+} tBTM_WRITE_STORED_LINK_KEY_COMPLETE;
+
+
+typedef struct
+{
+    UINT8          event;
+    UINT8          status;
+    UINT16         num_keys;
+
+} tBTM_DELETE_STORED_LINK_KEY_COMPLETE;
+
+// ---
+
+tBTA_STATUS BTA_EnableBluetooth(tBTA_DM_SEC_CBACK *p_cback);
+tBTA_STATUS BTA_DisableBluetooth(void);
+
+// muff1n: most changed prototype so far
+tBTA_STATUS BTA_DmAddDevice(BD_ADDR bd_addr, LINK_KEY link_key,
+                            tBTA_SERVICE_MASK trusted_mask, BOOLEAN is_trusted);
+tBTA_STATUS BTA_DmRemoveDevice(BD_ADDR bd_addr);
+void BTA_DmSearch(tBTA_DM_INQ *p_dm_inq, tBTA_SERVICE_MASK services, tBTA_DM_SEARCH_CBACK *p_cback);
+void BTA_DmSearchCancel(void);
+void BTA_DmPinReply(BD_ADDR bd_addr, BOOLEAN accept, UINT8 pin_len, UINT8 *p_pin);
+BOOLEAN BTA_DmIsDeviceUp(void);
+void BTA_DmSetDeviceName(char *p_name);
+
+// muff1n: disc_mode and conn_mode might be the , based on usage
+void BTA_DmSetVisibility(UINT8, UINT8);
+
+// muff1n: ucd_enabled might be the missing parameter
+void BTA_HhEnable(tBTA_SEC sec_mask, tBTA_HH_CBACK *p_cback);
+// muff1n: possibly takes just a tBTA_HH_DEV_DESCR in this version? i wrote it like that
+void BTA_HhAddDev(BD_ADDR bda, tBTA_HH_ATTR_MASK attr_mask, UINT8 sub_class,
+                  UINT8 app_id, tBTA_HH_DEV_DESCR descr);
+void BTA_HhRemoveDev(UINT8 dev_handle);
+void BTA_HhOpen(BD_ADDR dev_bda, tBTA_HH_PROTO_MODE mode, tBTA_SEC sec_mask);
+void BTA_HhClose(UINT8 dev_handle);
+
+// muff1n: dev_bda is likely the missing parameter, as it is not used
+void BTA_HhSendData(UINT8 dev_handle, BT_HDR *p_data);
+
+void bta_sys_set_trace_level(UINT8 level);
+
+void BTM_DeviceReset(tBTM_CMPL_CB *p_cb);
+
+tBTM_STATUS BTM_EnableTestMode(void);
+
+tBTM_STATUS BTM_ReadStoredLinkKey(BD_ADDR bd_addr, tBTM_CMPL_CB *p_cb);
+tBTM_STATUS BTM_WriteStoredLinkKey(UINT8 num_keys,
+                                   BD_ADDR *bd_addr,
+                                   LINK_KEY *link_key,
+                                   tBTM_CMPL_CB *p_cb);
+tBTM_STATUS BTM_DeleteStoredLinkKey(BD_ADDR bd_addr, tBTM_CMPL_CB *p_cb);
+
+tBTM_STATUS BTM_SetPowerMode(UINT8 pm_id, BD_ADDR remote_bda, tBTM_PM_PWR_MD *p_mode);
+tBTM_STATUS BTM_SetAfhChannels(UINT8 first, UINT8 last);
+
+tBTM_STATUS BTM_VendorSpecificCommand(UINT16 opcode, UINT8 param_len,
+                                      UINT8 *p_param_buf, tBTM_VSC_CMPL_CB *p_cb);
+
+tBTM_STATUS BTM_ReadLocalVersion(tBTM_VERSION_INFO *p_vers);
+tBTM_STATUS BTM_SetDeviceClass(DEV_CLASS dev_class);
+
+tBTM_STATUS btm_remove_acl(BD_ADDR bd_addr);
+
+// muff1n: is_register is probably the missing parameter here
+tBTM_STATUS BTM_RegisterForVSEvents(tBTM_VS_EVT_CB *p_cb);
+tBTM_DEV_STATUS_CB *BTM_RegisterForDeviceStatusNotif(tBTM_DEV_STATUS_CB *p_cb);
+
+tBTM_STATUS BTM_PmRegister(UINT8 mask, UINT8 *p_pm_id, tBTM_PM_STATUS_CBACK *p_cb);
+tBTM_STATUS BTM_WritePageTimeout(UINT16 timeout);
+void BTM_SetDefaultLinkPolicy(UINT16 settings);
+void BTM_SetDefaultLinkSuperTout(UINT16 timeout);
+
+BOOLEAN BTM_SecAddDevice(BD_ADDR bd_addr, DEV_CLASS dev_class, BD_NAME bd_name,
+                         BD_FEATURES features, UINT32 trusted_mask[],
+                         LINK_KEY link_key);
+
+void *GKI_getbuf(UINT16 size);
+
+UINT8 L2CA_SetTraceLevel(UINT8 trace_level);
+
+UINT8 SDP_SetTraceLevel(UINT8 new_level);
+
+/* muff1n: not in bluedroid source; might be older removed API functions */
+void BTA_DmSendHciReset(void);
+void BTA_HhGetAclQueueInfo(void);
+void BTA_Init(void);
+void BTA_CleanUp(void (*p_cb)(tBTA_STATUS status)); // probably
+
+// ---
+/* muff1n: I wrote this definition myself
+ * TODO: would this be part of BLE or WUD?
+ */
+
+struct small_dev_info
+{
+    char        devName[20];    // size 0x14? offset 0x00 // might be 0x13?
+    char        at_0x14[1];     // size 0x??, offset 0x14?
+    char        __pad0[0x20 - (0x14 + 0x01)];
+    LINK_KEY    linkKey;        // size 0x10, offset 0x20
+    char        __pad1[0x10];
+}; // size 0x40
+
+#endif // CONTEXT_BTE_H
diff --git a/include/revolution/wpad/wud.h b/include/revolution/wpad/wud.h
new file mode 100644
index 0000000000..da024b667b
--- /dev/null
+++ b/include/revolution/wpad/wud.h
@@ -0,0 +1,53 @@
+#ifndef _REVOLUTION_WUD_H_
+#define _REVOLUTION_WUD_H_
+
+#include <revolution/types.h>
+#include <revolution/wpad/bte.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define WUD_CHAN0         0
+#define WUD_CHAN1         1
+#define WUD_CHAN2         2
+#define WUD_CHAN3         3
+#define WUD_MAX_CHANNELS  4
+
+#define WUD_CHAN_INVALID  -1
+
+typedef void* WUDAllocFunc(u32 size);
+typedef int WUDFreeFunc(void* ptr);  // signature from petari. not sure what the int is, though
+
+typedef void WUDSyncDeviceCallback(s32 result, s32 num);  // what is result?
+typedef void WUDClearDeviceCallback(signed);
+
+typedef struct WUDDevInfo WUDDevInfo;
+typedef void WUDHidConnectCallback(WUDDevInfo* devInfo, u8 isOpenEvent);
+typedef void WUDHidReceiveCallback(u8 dev_handle, u8* p_rpt, u16 len);
+
+struct WUDDevInfo {
+    /* 0x00 */ struct small_dev_info small;
+    /* 0x40 */ BD_ADDR devAddr;
+    /* 0x46 */ LINK_KEY linkKey;
+    /* 0x56 */ u8 devHandle;
+    /* 0x57 */ u8 subclass;
+    /* 0x58 */ u8 appID;
+    /* 0x59 */ u8 at_0x59;
+    /* 0x5a */ u8 at_0x5a; /* unknown */
+    /* 0x5b */ u8 at_0x5b;
+    /* 0x5c */ u8 at_0x5c;
+    u8 at_0x5d[1]; // padding?
+    /* 0x5e */ tBTA_HH_ATTR_MASK hhAttrMask;
+}; // size 0x60
+
+u8 WUDGetBufferStatus(void);
+u8 _WUDGetLinkNumber(void);
+u16 _WUDGetQueuedSize(s8 dev_handle);
+u16 _WUDGetNotAckedSize(s8 dev_handle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _REVOLUTION_WUD_H_