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authorPheenoh <pheenoh@gmail.com>2021-01-03 03:51:44 -0500
committerPheenoh <pheenoh@gmail.com>2021-01-03 03:51:44 -0500
commit777bf2d3eb7d8b83b6dcac697d9be66960f784f8 (patch)
tree062abe73a72655701eaba3777ea0cbec142ef77b /include
parent47c40cce41c4b44dacaaeb5589329bc2b015ee9e (diff)
dSv_info_c::isSwitch OK
Diffstat (limited to 'include')
-rw-r--r--include/d/d_save/d_save/asm/func_80035360.s53
-rw-r--r--include/d/d_save/d_save/asm/func_8003542C.s51
2 files changed, 52 insertions, 52 deletions
diff --git a/include/d/d_save/d_save/asm/func_80035360.s b/include/d/d_save/d_save/asm/func_80035360.s
index eaec14e015..02fc67854d 100644
--- a/include/d/d_save/d_save/asm/func_80035360.s
+++ b/include/d/d_save/d_save/asm/func_80035360.s
@@ -56,55 +56,4 @@ lbl_80035414:
/* 8003541C 0003235C 80 01 00 14 */ lwz r0, 0x14(r1)
/* 80035420 00032360 7C 08 03 A6 */ mtlr r0
/* 80035424 00032364 38 21 00 10 */ addi r1, r1, 0x10
-/* 80035428 00032368 4E 80 00 20 */ blr
-/* 8003542C 0003236C 94 21 FF F0 */ stwu r1, -0x10(r1)
-/* 80035430 00032370 7C 08 02 A6 */ mflr r0
-/* 80035434 00032374 90 01 00 14 */ stw r0, 0x14(r1)
-/* 80035438 00032378 93 E1 00 0C */ stw r31, 0xc(r1)
-/* 8003543C 0003237C 93 C1 00 08 */ stw r30, 8(r1)
-/* 80035440 00032380 7C 7E 1B 78 */ mr r30, r3
-/* 80035444 00032384 7C 9F 23 78 */ mr r31, r4
-/* 80035448 00032388 2C 1F FF FF */ cmpwi r31, -1
-/* 8003544C 0003238C 41 82 00 0C */ beq lbl_80035458
-/* 80035450 00032390 2C 1F 00 FF */ cmpwi r31, 0xff
-/* 80035454 00032394 40 82 00 0C */ bne lbl_80035460
-lbl_80035458:
-/* 80035458 00032398 38 60 00 00 */ li r3, 0
-/* 8003545C 0003239C 48 00 00 6C */ b lbl_800354C8
-lbl_80035460:
-/* 80035460 000323A0 2C 1F 00 80 */ cmpwi r31, 0x80
-/* 80035464 000323A4 40 80 00 10 */ bge lbl_80035474
-/* 80035468 000323A8 38 7E 09 58 */ addi r3, r30, 0x958
-/* 8003546C 000323AC 4B FF F4 21 */ bl revSwitch__12dSv_memBit_cFi
-/* 80035470 000323B0 48 00 00 58 */ b lbl_800354C8
-lbl_80035474:
-/* 80035474 000323B4 2C 1F 00 C0 */ cmpwi r31, 0xc0
-/* 80035478 000323B8 40 80 00 14 */ bge lbl_8003548C
-/* 8003547C 000323BC 38 7E 09 78 */ addi r3, r30, 0x978
-/* 80035480 000323C0 38 9F FF 80 */ addi r4, r31, -128
-/* 80035484 000323C4 4B FF F7 91 */ bl revSwitch__12dSv_danBit_cFi
-/* 80035488 000323C8 48 00 00 40 */ b lbl_800354C8
-lbl_8003548C:
-/* 8003548C 000323CC 7C A3 2B 78 */ mr r3, r5
-/* 80035490 000323D0 4B FF 85 21 */ bl dStage_roomControl_c_NS_getZoneNo
-/* 80035494 000323D4 2C 1F 00 E0 */ cmpwi r31, 0xe0
-/* 80035498 000323D8 40 80 00 1C */ bge lbl_800354B4
-/* 8003549C 000323DC 54 63 28 34 */ slwi r3, r3, 5
-/* 800354A0 000323E0 38 63 09 B6 */ addi r3, r3, 0x9b6
-/* 800354A4 000323E4 7C 7E 1A 14 */ add r3, r30, r3
-/* 800354A8 000323E8 38 9F FF 40 */ addi r4, r31, -192
-/* 800354AC 000323EC 4B FF F8 CD */ bl revSwitch__13dSv_zoneBit_cFi
-/* 800354B0 000323F0 48 00 00 18 */ b lbl_800354C8
-lbl_800354B4:
-/* 800354B4 000323F4 54 63 28 34 */ slwi r3, r3, 5
-/* 800354B8 000323F8 38 63 09 B6 */ addi r3, r3, 0x9b6
-/* 800354BC 000323FC 7C 7E 1A 14 */ add r3, r30, r3
-/* 800354C0 00032400 38 9F FF 20 */ addi r4, r31, -224
-/* 800354C4 00032404 4B FF F9 39 */ bl revOneSwitch__13dSv_zoneBit_cFi
-lbl_800354C8:
-/* 800354C8 00032408 83 E1 00 0C */ lwz r31, 0xc(r1)
-/* 800354CC 0003240C 83 C1 00 08 */ lwz r30, 8(r1)
-/* 800354D0 00032410 80 01 00 14 */ lwz r0, 0x14(r1)
-/* 800354D4 00032414 7C 08 03 A6 */ mtlr r0
-/* 800354D8 00032418 38 21 00 10 */ addi r1, r1, 0x10
-/* 800354DC 0003241C 4E 80 00 20 */ blr \ No newline at end of file
+/* 80035428 00032368 4E 80 00 20 */ blr \ No newline at end of file
diff --git a/include/d/d_save/d_save/asm/func_8003542C.s b/include/d/d_save/d_save/asm/func_8003542C.s
new file mode 100644
index 0000000000..c6a5fda5ec
--- /dev/null
+++ b/include/d/d_save/d_save/asm/func_8003542C.s
@@ -0,0 +1,51 @@
+/* 8003542C 0003236C 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 80035430 00032370 7C 08 02 A6 */ mflr r0
+/* 80035434 00032374 90 01 00 14 */ stw r0, 0x14(r1)
+/* 80035438 00032378 93 E1 00 0C */ stw r31, 0xc(r1)
+/* 8003543C 0003237C 93 C1 00 08 */ stw r30, 8(r1)
+/* 80035440 00032380 7C 7E 1B 78 */ mr r30, r3
+/* 80035444 00032384 7C 9F 23 78 */ mr r31, r4
+/* 80035448 00032388 2C 1F FF FF */ cmpwi r31, -1
+/* 8003544C 0003238C 41 82 00 0C */ beq lbl_80035458
+/* 80035450 00032390 2C 1F 00 FF */ cmpwi r31, 0xff
+/* 80035454 00032394 40 82 00 0C */ bne lbl_80035460
+lbl_80035458:
+/* 80035458 00032398 38 60 00 00 */ li r3, 0
+/* 8003545C 0003239C 48 00 00 6C */ b lbl_800354C8
+lbl_80035460:
+/* 80035460 000323A0 2C 1F 00 80 */ cmpwi r31, 0x80
+/* 80035464 000323A4 40 80 00 10 */ bge lbl_80035474
+/* 80035468 000323A8 38 7E 09 58 */ addi r3, r30, 0x958
+/* 8003546C 000323AC 4B FF F4 21 */ bl revSwitch__12dSv_memBit_cFi
+/* 80035470 000323B0 48 00 00 58 */ b lbl_800354C8
+lbl_80035474:
+/* 80035474 000323B4 2C 1F 00 C0 */ cmpwi r31, 0xc0
+/* 80035478 000323B8 40 80 00 14 */ bge lbl_8003548C
+/* 8003547C 000323BC 38 7E 09 78 */ addi r3, r30, 0x978
+/* 80035480 000323C0 38 9F FF 80 */ addi r4, r31, -128
+/* 80035484 000323C4 4B FF F7 91 */ bl revSwitch__12dSv_danBit_cFi
+/* 80035488 000323C8 48 00 00 40 */ b lbl_800354C8
+lbl_8003548C:
+/* 8003548C 000323CC 7C A3 2B 78 */ mr r3, r5
+/* 80035490 000323D0 4B FF 85 21 */ bl dStage_roomControl_c_NS_getZoneNo
+/* 80035494 000323D4 2C 1F 00 E0 */ cmpwi r31, 0xe0
+/* 80035498 000323D8 40 80 00 1C */ bge lbl_800354B4
+/* 8003549C 000323DC 54 63 28 34 */ slwi r3, r3, 5
+/* 800354A0 000323E0 38 63 09 B6 */ addi r3, r3, 0x9b6
+/* 800354A4 000323E4 7C 7E 1A 14 */ add r3, r30, r3
+/* 800354A8 000323E8 38 9F FF 40 */ addi r4, r31, -192
+/* 800354AC 000323EC 4B FF F8 CD */ bl revSwitch__13dSv_zoneBit_cFi
+/* 800354B0 000323F0 48 00 00 18 */ b lbl_800354C8
+lbl_800354B4:
+/* 800354B4 000323F4 54 63 28 34 */ slwi r3, r3, 5
+/* 800354B8 000323F8 38 63 09 B6 */ addi r3, r3, 0x9b6
+/* 800354BC 000323FC 7C 7E 1A 14 */ add r3, r30, r3
+/* 800354C0 00032400 38 9F FF 20 */ addi r4, r31, -224
+/* 800354C4 00032404 4B FF F9 39 */ bl revOneSwitch__13dSv_zoneBit_cFi
+lbl_800354C8:
+/* 800354C8 00032408 83 E1 00 0C */ lwz r31, 0xc(r1)
+/* 800354CC 0003240C 83 C1 00 08 */ lwz r30, 8(r1)
+/* 800354D0 00032410 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 800354D4 00032414 7C 08 03 A6 */ mtlr r0
+/* 800354D8 00032418 38 21 00 10 */ addi r1, r1, 0x10
+/* 800354DC 0003241C 4E 80 00 20 */ blr \ No newline at end of file