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authorTriang3l <triang3l@yandex.ru>2024-05-12 20:26:14 +0300
committerTriang3l <triang3l@yandex.ru>2024-05-12 20:26:14 +0300
commit3189a0e259938fc3dbedc16a63a0b860e772dc7d (patch)
tree15cb02feabbbed89aebf9ceb70a6b6b74a4d6618
parenta3304d252fac72f951ec3ce8b56a010edae05f63 (diff)
[GPU] Check memexport stream constant upper bits in range gathering
-rw-r--r--src/xenia/gpu/draw_util.cc9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/xenia/gpu/draw_util.cc b/src/xenia/gpu/draw_util.cc
index 1b5671fcb..b9f70ef1d 100644
--- a/src/xenia/gpu/draw_util.cc
+++ b/src/xenia/gpu/draw_util.cc
@@ -659,7 +659,14 @@ void AddMemExportRanges(const RegisterFile& regs, const Shader& shader,
for (uint32_t constant_index : shader.memexport_stream_constants()) {
xenos::xe_gpu_memexport_stream_t stream =
regs.GetMemExportStream(float_constants_base + constant_index);
- if (!stream.index_count) {
+ // Safety checks for stream constants potentially not set up if the export
+ // isn't done on the control flow path taken by the shader (not checking the
+ // Y component because the index is more likely to be constructed
+ // arbitrarily).
+ // The hardware validates the upper bits of eA according to the
+ // IPR2015-00325 sequencer specification.
+ if (stream.const_0x1 != 0x1 || stream.const_0x4b0 != 0x4B0 ||
+ stream.const_0x96 != 0x96 || !stream.index_count) {
continue;
}
const FormatInfo& format_info =