diff options
| author | Joel Linn <jl@conductive.de> | 2020-11-20 20:34:06 +0100 |
|---|---|---|
| committer | Triang3l <hwguy.siplus@gmail.com> | 2020-11-21 21:55:52 +0300 |
| commit | 923678dad7ccd9203ad2200f2bcbd66b292dbb67 (patch) | |
| tree | 76fe4522ac2e36cf9932335cdc678834da25c505 /docs/gpu.md | |
| parent | f6dc9ad517ad91d4cdb98cfac483a09bc7ce072a (diff) | |
[GPU] Add performance counter registers.
v3: Document registers referenced by D3D in `gpu.md`.
Diffstat (limited to 'docs/gpu.md')
| -rw-r--r-- | docs/gpu.md | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/docs/gpu.md b/docs/gpu.md index 903c9b6e2..0ba3c13b1 100644 --- a/docs/gpu.md +++ b/docs/gpu.md @@ -119,6 +119,87 @@ Registers documented at [src/xenia/gpu/register_table.inc](../src/xenia/gpu/regi PM4 commands documented at [src/xenia/gpu/xenos.h](../src/xenia/gpu/xenos.h#L521). +#### Performance Counters that may be read back by D3D + +They are 64-bit values and have a high and low 32-bit register as well as a `SELECT` register each: + +- CP_PERFCOUNTER0 + +- RBBM_PERFCOUNTER0 +- RBBM_PERFCOUNTER1 + +- SQ_PERFCOUNTER0 +- SQ_PERFCOUNTER1 +- SQ_PERFCOUNTER2 +- SQ_PERFCOUNTER3 + +- VGT_PERFCOUNTER0 +- VGT_PERFCOUNTER1 +- VGT_PERFCOUNTER2 +- VGT_PERFCOUNTER3 + +- VC_PERFCOUNTER0 +- VC_PERFCOUNTER1 +- VC_PERFCOUNTER2 +- VC_PERFCOUNTER3 + +- PA_SU_PERFCOUNTER0 +- PA_SU_PERFCOUNTER1 +- PA_SU_PERFCOUNTER2 +- PA_SU_PERFCOUNTER3 + +- PA_SC_PERFCOUNTER0 +- PA_SC_PERFCOUNTER1 +- PA_SC_PERFCOUNTER2 +- PA_SC_PERFCOUNTER3 + +- HZ_PERFCOUNTER0 +- HZ_PERFCOUNTER1 + +- TCR_PERFCOUNTER0 +- TCR_PERFCOUNTER1 + +- TCM_PERFCOUNTER0 +- TCM_PERFCOUNTER1 + +- TCF_PERFCOUNTER0 +- TCF_PERFCOUNTER1 +- TCF_PERFCOUNTER2 +- TCF_PERFCOUNTER3 +- TCF_PERFCOUNTER4 +- TCF_PERFCOUNTER5 +- TCF_PERFCOUNTER6 +- TCF_PERFCOUNTER7 +- TCF_PERFCOUNTER8 +- TCF_PERFCOUNTER9 +- TCF_PERFCOUNTER10 +- TCF_PERFCOUNTER11 + +- TP0_PERFCOUNTER0 +- TP0_PERFCOUNTER1 +- TP1_PERFCOUNTER0 +- TP1_PERFCOUNTER1 +- TP2_PERFCOUNTER0 +- TP2_PERFCOUNTER1 +- TP3_PERFCOUNTER0 +- TP3_PERFCOUNTER1 + +- SX_PERFCOUNTER0 + +- BC_PERFCOUNTER0 +- BC_PERFCOUNTER1 +- BC_PERFCOUNTER2 +- BC_PERFCOUNTER3 + +- MC0_PERFCOUNTER0 +- MC1_PERFCOUNTER0 + +- MH_PERFCOUNTER0 +- MH_PERFCOUNTER1 +- MH_PERFCOUNTER2 + +- BIF_PERFCOUNTER0 + ### Shaders * [LLVM R600 Tables](https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600Instructions.td) |