diff options
| author | Sintendo <bram.speeckaert@gmail.com> | 2020-04-19 22:55:43 +0200 |
|---|---|---|
| committer | Sintendo <bram.speeckaert@gmail.com> | 2020-04-21 22:06:46 +0200 |
| commit | f1c3ab359d8113fb03bb682dc0f0171b17c137fe (patch) | |
| tree | c4e66bd0db9ab5ca24b6021c7bb8a0fc4594f4ec /Source/Core | |
| parent | 72fbdf1a6bafe8a01c58deae79fbae44535a34f4 (diff) | |
Jit64: addx - Deduplicate branches part 2
No functional change, just simplify some repeated logic in the case
where we're dealing with exactly one immediate and one simple register
when overflow isn't needed.
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp index 445f536d11..62cfb48594 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp @@ -1339,13 +1339,11 @@ void Jit64::addx(UGeckoInstruction inst) { LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg())); } - else if (Ra.IsSimpleReg() && Rb.IsImm() && !inst.OE) + else if ((Ra.IsSimpleReg() || Rb.IsSimpleReg()) && (Ra.IsImm() || Rb.IsImm()) && !inst.OE) { - LEA(32, Rd, MDisp(Ra.GetSimpleReg(), Rb.SImm32())); - } - else if (Rb.IsSimpleReg() && Ra.IsImm() && !inst.OE) - { - LEA(32, Rd, MDisp(Rb.GetSimpleReg(), Ra.SImm32())); + RCOpArg& Rimm = Ra.IsImm() ? Ra : Rb; + RCOpArg& Rreg = Ra.IsImm() ? Rb : Ra; + LEA(32, Rd, MDisp(Rreg.GetSimpleReg(), Rimm.SImm32())); } else { |